Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/CORE_MPI.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/CORE_MPI.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/CORE_MPI.vhd (revision 74) @@ -101,5 +101,5 @@ copying : out std_logic; Ram_rd_en : out STD_LOGIC; - ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0); ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0)); end component; @@ -189,5 +189,5 @@ fifo_full : IN std_logic; Rec_Rdy : OUT std_logic; - Rec_Data : OUT Typ_PortIO(0 to 3); + Rec_Data : buffer Typ_PortIO(0 to 3); Rec_Ack : IN std_logic; fifo_data : OUT std_logic_vector(Word-1 downto 0); @@ -234,5 +234,5 @@ Rec_Data : IN Typ_PortIO(0 to 3); Snd_data : OUT Typ_PortIO(0 to 3); - Snd_Start : OUT std_logic; + Snd_Start : buffer std_logic; Rec_Ack : OUT std_logic; I_fifo_wr_en: out STD_LOGIC; @@ -442,9 +442,9 @@ pushout(1)<=IsMain; pushout(2)<=SizeSet; -pushout(3)<=RankSet; +pushout(3)<=Ex4_result(6); --Spawn in progress on main pushout(4)<=Initialized; pushout(5)<=Ex1_result(1); -- -pushout(6)<=LibState(3); --Spawn - +pushout(6)<=LibState(3); --Spawned child +pushout(7)<=Ex4_result(7); --Spawn complete MPI_CORE_EX0_FSM: EX0_FSM PORT MAP( instruction => i_fifo1_data_out, @@ -527,5 +527,5 @@ when 0 => if InitReq='1' and Initialized='0' then Next_St_ex1<=1; - elsif InitReq='1' and Initialized='1' then + elsif Initialized='1' then Next_St_ex1 <=2; elsif fifo_instr='1' then --cas d'une instruction directe qui est présente @@ -538,14 +538,14 @@ Next_St_ex1<=4; end if; - when 2 => if Ex1_rdy='0' then + when 2 => if Ex1_rdy='0' then --ex1 est libre et actif Next_St_ex1<=3; end if; - when 3 => if Ex1_rdy='1' then - Next_St_ex1<=0; - end if; - if initreq='1' then - Next_St_ex1<=1; + when 3 => if Ex1_rdy='1' and Initialized='0'then --ex1 est occupé et actif + Next_St_ex1<=0; + elsif Ex1_rdy='1' and Initialized='1' then + Next_St_ex1<=2; end if; + when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau --compter quelques cycles d'horloges pour attendre initreq2 @@ -612,5 +612,5 @@ when 0 => Ex_en(2)<='0'; -LibState(3)<='0'; +--LibState(3)<='0'; when 1|2 => Ex_en(2) <='1'; @@ -764,5 +764,5 @@ Dma_rd_address2<=Dma_wr_address2; ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP( - instruction => instruction, + instruction => x"00", --pas utiliser ResOut => RankSize, clk =>clk , @@ -837,5 +837,6 @@ end case; end process; - mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4,ex2_ram_wr,ex4_ram_wr) + mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4, + ex1_ram_wr,ex2_ram_wr,ex4_ram_wr) begin case dma_wr_grant is @@ -874,5 +875,6 @@ NOC3.port_in_full<=switch_port_in_full; mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2, - ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in) + ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in,ex4_i_fifo2_data_in,ex4_i_fifo2_wr_en, + instruction,ex2_result) begin Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX1_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX1_FSM.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX1_FSM.vhd (revision 74) @@ -173,5 +173,6 @@ -- processus de transistion entre les etats fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, - pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address) + pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address, + fifo_src,dest_address,packet_type) variable tempval : std_logic_vector(Word-1 downto 0); variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé @@ -190,4 +191,6 @@ run_init<='1'; Next_ex1_state<=ex1_init_run; + else + run_init<='0'; end if; --lecture du registre status de la mib MPI @@ -602,5 +605,5 @@ end if; - when ex1_get3 =>if n<3 then --ecriture de la fin d'envoie + when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie if dma_wr_grant = '1' then -- fin du post de mpi_get @@ -611,5 +614,5 @@ end if; - elsif n=3 then + elsif n=2 then n_i<=0; Next_ex1_state <= ex1_get4; @@ -645,18 +648,20 @@ rd_ok<='1'; src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + n_i<=1; end if; elsif n=3 then if dma_rd_grant='1' and dma_wr_grant='1' then - n_i<=n+1; - tempval:=Ram_data_in; - rd_ok<='1'; - wr_ok<='0'; - dma_wr<='1'; - dma_rd<='1'; + n_i<=n+1; + tempval:=Ram_data_in; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; else - dma_wr<='0'; - dma_rd<='0'; - n_i<=n-1; + dma_wr<='0'; + dma_rd<='0'; + n_i<=n-1; end if; src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); @@ -664,5 +669,6 @@ if dma_wr_grant = '1' and dma_rd_grant='1' then n_i<=n+1; - + rd_ok<='0'; + wr_ok<='1'; tempval(6):='1'; --SET du bit Windows Busy --car réception Get tempval(1):='1'; -- SET du bit DReceiving @@ -671,9 +677,10 @@ rd_ok<='0'; wr_ok<='1'; + n_i<=1; end if; dma_wr<='1'; dma_rd<='1'; elsif n=5 then - n_i<=0; + n_i<=0; Next_ex1_state <= fifo_select; dma_wr<='0'; @@ -779,5 +786,5 @@ when ex1_init_run=> if n=0 then if snd_start='1' then --le module ex4 veut envoyer des données - if snd_data(0)(7 downto 4)=MPI_INIT or snd_data(0)(7 downto 4)=MPI_SPAWN then + n_i<=n+1; @@ -785,4 +792,10 @@ mem(i)<=snd_data(i); end loop; + if snd_data(0)(7 downto 4)=MPI_INIT or + snd_data(0)(7 downto 4)=MPI_SPAWN or + snd_data(0)(7 downto 4)=MPI_ACK then + + else + report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !"; end if; P_len_i<=x"04"; @@ -818,5 +831,5 @@ if run_init='1' then Next_EX1_state<=fifo_select; - run_init<='0'; + --run_init<='0'; end if; end if; @@ -824,10 +837,13 @@ - when ex1_init2 => + when ex1_init2 => -- écriture dans le registre status reg. + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); if n=0 then --envoie du message Spawn Ack sur le réseau if instruction(6)='1' then --Spawned=1 ? - n_i<=1; + n_i<=1; --envoie du message Spawn à main lib + Data_to_send<="01010000"; --init+spawn else n_i<=4; --écrire le résultat de la fn + Data_to_send<="00010000"; --init seul end if; @@ -841,4 +857,5 @@ snd_start1<='1'; n_i<=n+1; + fifo_copy<='0'; elsif n=3 then if snd_comp='1' then @@ -847,10 +864,16 @@ n_i<=n+1; end if; - elsif n=4 then + elsif n=4 then --écriture du registre status + dma_wr<='1'; wr_ok<='1'; if dma_wr_grant = '1' then -- fin du mpi_init n_i<=n+1; end if; - elsif n=5 then + elsif n=5 then + wr_ok<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=6 then Next_ex1_state <= ex1_init3; n_i<=0; @@ -858,6 +881,5 @@ end if; - -- écriture dans le registre status reg. - src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + when ex1_init3 =>--if AppInitAck='1' then Next_ex1_state <= fifo_select; @@ -871,9 +893,10 @@ -- sortie de la machine à etat ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, - pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok) + pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok, + fifo_rd) variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); begin -- code fonctionnel - case Next_ex1_state is + case ex1_state is when fifo_select => priority_rotation <='1'; -- on peut changer la priorité fifo_rd_en <= '0'; @@ -928,5 +951,5 @@ when decode_packet_type => priority_rotation <='0'; fifo_rd_en <= rd_ok; - switch_port_in_data <= (others =>'0'); + switch_port_in_data <= Data_To_Send; switch_port_in_wr_en <= '0'; AppInitReq<='0'; @@ -1163,11 +1186,11 @@ fifo_rd_en <= '0'; switch_port_in_data <= noc_fifo_in; - switch_port_in_wr_en <= push; - AppInitReq<='1'; + switch_port_in_wr_en <= fifo_wr; + AppInitReq<='0'; dma_rd_request <= '0'; dma_wr_request <= '1'; Ram_rd<='0'; Ram_wr<=wr_ok; - Ram_data_out<="00010000"; -- le résultat de l'exécution + Ram_data_out<=Data_to_send; -- le résultat de l'exécution -- dans le registre status Result <=(others=>'0');-- Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd (revision 74) @@ -55,5 +55,5 @@ fifo_full : in STD_LOGIC; Rec_Rdy : OUT std_logic; - Rec_Data : OUT Typ_PortIO(0 to 3); + Rec_Data : buffer Typ_PortIO(0 to 3); Rec_Ack : IN std_logic; AppRank : in STD_LOGIC_VECTOR(3 downto 0); @@ -99,4 +99,5 @@ BitVal : IN std_logic; start : in std_logic; + whole : in std_logic; done : out std_logic; dma_wr_grant : IN std_logic; @@ -113,5 +114,5 @@ -- définition du type etat de la machine à etat type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, -fetch_addresses,ex2_spawn,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, +fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, @@ -133,4 +134,5 @@ signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); signal sb_BitVal,sb_start,sb_done : std_logic:='0'; +signal sb_whole : std_logic:='0'; --écrire le mot entier signal sb_Ram_data_in : std_logic_vector(7 downto 0); signal sb_dma_wr_request : std_logic; @@ -141,23 +143,6 @@ signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); -- deuxième module pour set busy bit -signal bu_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); -signal bu_BitVal,bu_start,bu_done : std_logic:='0'; -signal bu_Ram_data_in : std_logic_vector(7 downto 0); -signal bu_dma_wr_request : std_logic; -signal bu_dma_rd_request : std_logic; -signal bu_ram_rd : std_logic; -signal bu_ram_wr : std_logic; -signal bu_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); -signal bu_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); signal Set_Wbusy : std_logic:='0'; --choix du Mux -signal b_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); -signal b_BitVal,b_start,b_done : std_logic:='0'; -signal b_Ram_data_in : std_logic_vector(7 downto 0); -signal b_dma_wr_request : std_logic; -signal b_dma_rd_request : std_logic; -signal b_ram_rd : std_logic; -signal b_ram_wr : std_logic; -signal b_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); -signal b_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); +signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl --********************************************* @@ -176,6 +161,6 @@ signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés signal WStart,WPost,WBUSY ,RGET: std_logic:='0'; -- -signal Rec_WPost, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0'); -signal Waited_Get : mem32(0 to 15); +signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0'); +signal Waited_Get,Waited_Get_i : mem32(0 to 15); Signal Rec_Data_i : Typ_PortIO(0 to 3); signal Get_Instr,Put_instr :memory(0 to 8); @@ -230,20 +215,18 @@ Ram_data_out =>sb_ram_data_out, Start =>sb_start, + whole=>sb_whole, done =>sb_done ); ---b_BitVal<=bu_Bitval when Set_Wbusy='1' else Sb_BitVal; ---b_BitMask<=bu_BitMask when Set_Wbusy='1' else Sb_BitVal; ---b_start<= bu_start when Set_wBusy='1' else sb_start; ---b_ram_rd<=bu_ram_rd when Set_Wbusy='1' else Sb_ram_rd; ---b_ram_wr<=bu_ram_wr when Set_Wbusy='1' else Sb_ram_wr; ---b_dma_ram_request_rd<=bu__dma_ram_request_rd when Set_Wbusy='1' else Sb_dma_ram_request_rd; ---b_dma_ram_request_wr<=bu_dma_ram_request_wr when Set_Wbusy='1' else Sb_dma_ram_request_wr; + -- processus de transistion entre les etats ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, - switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, - sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy) + switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, + sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, + dest_ack,rec_wpost,Gcomp,rec_data) variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée variable tempval : std_logic_vector(Word-1 downto 0); variable n_e,i:natural range 0 to 15 :=0; +variable mode_get,match_get:std_logic:='0'; +--=================================================================- procedure read_nocdat_fsm(sdata_avail: std_logic; signal rd,wr:out std_logic; @@ -280,12 +263,21 @@ Ex2_on<='0'; barrier_counter <= "0000"; - --n_i<=n; + GPost_Set_i<=GPost_Set; + Rec_WPost_i<=Rec_WPost; + GPost_i<=GPost; + GComp_i<=GComp; dest_address_i<=dest_address; --- else + for i in 0 to 15 loop + Waited_get_i(i)<=Waited_get(i); + end loop; + Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non n_i<=n; --valeur par défaut de n_i P_len_i<=P_len; + for i in 0 to 3 loop + Rec_Data_i(i)<=Rec_Data(i); + end loop; case ex2_state is - when Ex2_ready => if Instruction_en='1' then + when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then Next_Ex2_state <= fetch_packet_type; end if; @@ -298,5 +290,5 @@ rd_ok<='1'; else - Next_Ex2_state <= Ex2_Ready; + --Next_Ex2_state <= Ex2_Ready; rd_ok<='0'; end if; @@ -340,5 +332,7 @@ Next_Ex2_state <= ex2_Wsync; elsif packet_type = MPI_SPAWN then - Next_Ex2_state <= ex2_spawn; + Next_Ex2_state <= ex2_spawn1; + wr_ok<='0'; + rd_ok<='0'; else Next_Ex2_state <= decode_packet_type; @@ -401,8 +395,8 @@ else dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); - Waited_get(ptr_get)(7 downto 0)<=Get_instr(0); --id - Waited_get(ptr_get)(15 downto 8)<=Get_instr(1); --longueur - Waited_get(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas - Waited_get(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut + Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id + Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur + Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas + Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut RGET<='1'; @@ -469,10 +463,25 @@ sb_bitMask<=x"20";--cinquième bit à un sb_bitval<='1'; + sb_whole<='0';--Modifier un seul bit ! if sb_done='1' then n_i<=1; sb_start<='0'; sb_bitval<='0'; + dest_address_i<=dest_address+1; end if; + elsif n=1 then + sb_start<='1'; + sb_bitMask<=Rec_Data(2); + sb_bitval<='1'; + sb_whole<='1'; + if sb_done='1' then + n_i<=n+1; + sb_start<='0'; + sb_bitval<='0'; + sb_whole<='0'; + end if; + + elsif n=2 then Next_Ex2_state<=Ex2_Ready; n_i<=0; @@ -481,5 +490,5 @@ when ex2_Wsync => rd_ok<='0'; if n<2 then --réception de la synchronisation. - n_e:=n_i; + n_e:=n; read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); n_i<=n_e; @@ -526,30 +535,48 @@ when Ex2_Wcomp => dma_rd<='1'; rd_ok<='1'; - If Dma_rd_grant='1' then + if n=0 then n_i<=n+1; --cycle d'attente pour la RAM + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + GComp_i(i)<='1'; elsif n=1 then - dest_address_i <= dest_address+1; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + If Dma_rd_grant='1' then n_i<=2; + end if; elsif n=2 then - + If Dma_rd_grant='1' then --creer un délai sur ces signaux par rapport à dest_adress - n_i<=n+1; - rd_ok<='1'; - dest_address_i <= dest_address; - GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard + n_i<=n+1; + rd_ok<='1'; + dest_address_i <= dest_address+1; + GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard + + else + n_i<=1; + end if; elsif n=3 then + If Dma_rd_grant='1' then GPost_i(15 downto 8)<=Ram_data_out; n_i<=n+1; rd_ok<='1'; dma_rd<='1'; + end if; elsif n=4 then GPost_i(15 downto 8)<=Ram_data_out; + rd_ok<='1'; + dma_rd<='1'; + n_i<=n+1; + elsif n=5 then rd_ok<='0'; - dma_rd<='1'; + dma_rd<='0'; n_i<=0; + If GPost=GComp then --le même nombre de post que de COmpleted ? + GPost_Set_i<='1'; + end if; + Next_ex2_state <= ex2_set_busy; end if; - end if; + when ex2_init1 => if n<2 then -- execution du mpi Init @@ -568,12 +595,7 @@ result_i<=(others=>'0'); elsif n=2 then - --if switch_data_available='1' then n_i<=n+1; rd_ok<='0'; --- --P_len <=P_len -1; --- --- else --- rd_ok<='0'; --- end if; + elsif n=3 then rd_ok<='0'; -- normalement plus rien à lire @@ -588,5 +610,8 @@ elsif data_to_ram(7 downto 4)=INIT_REGISTER then Result_i<=data_to_ram; - wr_ok<='1'; --permet d'activer Init de Ex_4 + wr_ok<='0'; --permet d'activer Init de Ex_4 + report "Mise à jour des données d'initialisation"; + Next_Ex2_state<=ex2_ready; + n_i<=0; elsif data_to_ram(7 downto 4)=INIT_SPAWN then Result_i<=data_to_ram; @@ -645,5 +670,5 @@ n_i<=1; i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0))); - Rec_WPost(i)<='1'; --indiquer que ce port a emis des données ! + --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! if unsigned( P_len) > 0 then @@ -705,17 +730,22 @@ if n=0 then if RGET='1' then - for i in 1 to Ptr_get loop - if waited_get(i-1)(3 downto 0)=rec_data_i(0)(3 downto 0) and - waited_get(i-1)(15 downto 8)=(rec_data_i(1)-2) and - waited_get(i-1)(23 downto 16)=rec_data_i(2) and - waited_get(i-1)(31 downto 24)=rec_data_i(3) then - if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data_i(0)(7 downto 4)=MPI_PUT) then + L1: for i in 1 to 15 loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then received_get(i-1)<='1'; dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); - end if; + mode_get:='1'; + match_get:='1'; + end if; else - end if; - end loop; + end if; + end if; + exit L1 when i= Ptr_get; + end loop L1; end if; @@ -725,13 +755,19 @@ elsif n=1 then - + if match_get='0' then + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + end if; if dma_rd_grant='1' then if RGET='1' then --si on est en mode attente d'un Get RGET<='0'; --Supposons tous les Gets reçus ! - test_wcomp:for i in 1 to Ptr_get loop --Tous les Get reçus ? + test_wcomp:for i in 1 to 15 loop --Tous les Get reçus ? + if Ptr_get>=i then if received_get(i-1)='0' then RGET<='1'; --Non ! end if; - end loop; + end if; + exit test_wcomp when i=Ptr_get; + end loop test_wcomp; end if; @@ -746,6 +782,8 @@ tempval:=Ram_data_out; tempval(4):='1'; --SET du bit DReceived - --si get ack est détecté - --tempval(6):=WBusy or RGET; -- Bit 6 Busy=0 si dernier get reçu !! + if Mode_Get='1' then --si get ack est détecté + tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! + mode_get:='1'; + end if; data_to_ram<=tempval; rd_ok<='0'; @@ -774,4 +812,6 @@ rd_ok<='0'; wr_ok<='0'; + mode_get:='0'; + match_get:='0'; end if; @@ -782,5 +822,5 @@ Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put - when ex2_spawn => + when ex2_spawn1 => if n<2 then @@ -788,12 +828,19 @@ read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); n_i<=n_e; + Rec_Data_i(2)<=Switch_port_out_data; elsif n=2 then + Rec_Data_i(3)<=Switch_port_out_data; Result_i<=Switch_port_out_data; Data_to_ram<=Switch_port_out_data; n_i<=n+1; + rd_ok<='1'; elsif n=3 then if data_to_ram(7 downto 4)=SPAWN_LOAD then Result_i<=data_to_ram; wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=SPAWN_COMP then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=SPAWN_ERR then Result_i<=data_to_ram; @@ -804,7 +851,9 @@ end if; n_i<=n+1; + rd_ok<='0'; elsif n=4 then + wr_ok<='1'; if AppInitAck='1' then - wr_ok<='1'; + wr_ok<='0'; rd_ok<='0'; n_i<=n+1; @@ -816,5 +865,6 @@ Next_Ex2_state <=Ex2_Ready; end if; - + when Ex2_Spawn2=> + Next_Ex2_state <=Ex2_Ready; when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch --ack_state<=next_ack_state; --MAE d'envoie de AR @@ -896,6 +946,6 @@ rd_ok<='0'; end if; - i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0))); - Rec_WPost(i)<='1'; --indiquer que ce port a emis des données ! + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! --préparer en avance l'adresse de lecture/écriture @@ -971,11 +1021,15 @@ dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); n_i<=1; - if Gpost>0 then + if Gpost_Set='1' then if (rec_wpost=gpost) and RGET='0' then Wbusy<='0'; + Gpost_Set_i<='0'; + GComp_i<=(others=>'0'); + rec_wpost_i<=(others=>'0');--reset des messages reçu else Wbusy<='1'; end if; else + n_i<=2; end if; @@ -1047,6 +1101,7 @@ -- sortie de la machine à etat -- - ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram, - switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request,n) + ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, + switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, + appInitAck,n) variable transact : std_logic_vector(Word-1 downto 0); begin @@ -1353,5 +1408,5 @@ Ready<='0'; - when ex2_spawn => fifo_wr_en <= '0'; + when ex2_spawn1 => fifo_wr_en <= '0'; switch_port_out_rd_en <= rd_ok;--switch_data_available; packet_received <= '0'; @@ -1364,4 +1419,17 @@ Ram_data_in<=(others =>'0'); AppInitReq<=wr_ok; + when ex2_Spawn2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + + Ram_data_in<=data_to_ram; + + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; when ex2_init1 => fifo_wr_en <= '0'; switch_port_out_rd_en <= rd_ok;--switch_data_available; @@ -1419,8 +1487,8 @@ end process; - ex2_fsm_sync:process(clk) + ex2_fsm_sync:process(clk,reset) begin - if rising_edge(clk) then + if reset = '1' then ex2_state <= Ex2_Ready; @@ -1430,4 +1498,5 @@ GPost<=(others =>'0'); else + if rising_edge(clk) then ex2_state<=next_ex2_state; ack_state<=next_ack_state; --MAE d'envoie de AR @@ -1438,5 +1507,11 @@ Instr_ack<=Instr_ack_i; Ptr_Get<=Ptr_Get_i; + Rec_Wpost<=Rec_WPost_i; GPost<=GPost_i; + GComp<=GComp_i; + GPost_set<=GPost_Set_i; + For i in 0 to 15 loop + Waited_get(i)<=Waited_get_i(i); + end loop; for i in 0 to 3 loop Rec_Data(i)<=Rec_Data_i(i); @@ -1445,5 +1520,5 @@ end if; end process ex2_fsm_sync; -snd_ack:process (ack_state,reset,fifo_full,instr_ack) +snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,Packet_type) --ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu begin @@ -1524,17 +1599,5 @@ --end if; end process; -Win_busy:process(Rec_wpost,GPost,RGET) -begin - -- if Gpost>0 then --- if rec_wpost=gpost and RGET='0' then --- Wbusy<='0'; --- else --- Wbusy<='1'; --- end if; --- end if; --- if RGET='1' then --- WBusy<='1'; --- end if; -end process Win_busy; + end Behavioral; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX3_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX3_FSM.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX3_FSM.vhd (revision 74) @@ -51,5 +51,5 @@ signal size : unsigned(Word-1 downto 0) := nprocs; begin -instruction_signal <= instruction(3 downto 0); +instruction_signal <= instruction(7 downto 4); ex3_fsm_process : process(clk) begin Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX4_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX4_FSM.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX4_FSM.vhd (revision 74) @@ -55,5 +55,5 @@ Rec_Data : IN Typ_PortIO(0 to 3); Snd_data : OUT Typ_PortIO(0 to 3); - Snd_Start : OUT std_logic; + Snd_Start : buffer std_logic; Rec_Ack : OUT std_logic; dma_wr_grant : in STD_LOGIC; @@ -111,5 +111,5 @@ type typ_receiv is (r_wait,r_dlen,r_drop,r_glen,r_data,r_pulse,r_end); type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout); - + type typ_mem16 is array(natural range <>) of std_logic_vector(15 downto 0);-- signal etsnd : typ_send; signal etrec:typ_receiv; --pour la machine à état de réception @@ -126,4 +126,7 @@ signal tosend,tosend4 :std_logic_vector(Word-1 downto 0); signal PeerStat : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres Lib initialisées + signal SpawnReq,SpawnReq_Q : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres HT qui ont appelés le Spawn + signal Spawn_grp,Spawn_grp_Q :typ_mem16(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); --un max de quatre groupes de fils est prévu + signal Grp_id,grp_id_i :natural range 0 to 3:=0; --id du groupe des HT fils signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port --signaux pour les états des MAE @@ -136,6 +139,10 @@ signal SpawnOn,SpawnInit :std_logic:='0'; --indique que le Spawn est activé signal SpawnNbReq,SpawnNbAck,SpawnNBAck_i : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement - signal SpawnCmd :std_logic_vector(Word-1 downto 0); + signal SpawnNbReq_Q : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement + signal SpawnCmd0,SpawnCmd1, SpawnCmd2 :std_logic_vector(Word-1 downto 0):=(others=>'0'); + signal SpawnCmd0_Q,SpawnCmd1_Q, SpawnCmd2_Q :std_logic_vector(Word-1 downto 0):=(others=>'0'); signal SpawnDest :std_logic_vector(3 downto 0); + Signal Ht_Start,Ht_Start_i : natural range 0 to 15:=0; + Signal vPeerStat,vPeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); signal IsMain_i,Initialized_i,HCL_init: std_logic:='0'; signal DS_RDY ,BCast_Rdy,Send_RDY,CM_RDY:std_logic:='0'; @@ -150,5 +157,5 @@ --Signaux des résultats et de l'état signal PortNum_i,MyPort : std_logic_vector(3 downto 0); -- - signal NocMax : std_logic_vector(3 downto 0); -- Nombre de ports du réseau -1 ? + signal NocMax : std_logic_vector(3 downto 0):=(others=>'0'); -- Nombre de ports du réseau -1 ? signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE signal AppSize_i:std_logic_vector(3 downto 0) ;--taille de l'application @@ -162,9 +169,9 @@ signal Datalen : natural range 0 to 7:=0; --indique la longueur des données --other outputs - signal StatAsked_i,RankAsked_i,EquFlag_i,MainResp_i,RankSent_i,Result_i:std_logic; - signal snd_start_i:std_logic;--version interne des signaux de sortie + signal StatAsked_i,RankAsked_i,EquFlag_i,MainResp_i,RankSent_i,Result_i:std_logic:='0'; + signal snd_start_i:std_logic:='0';--version interne des signaux de sortie --signal BCast_Rdy_i : std_logic; signal cdlen,dcount : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd - signal timeout,timeout_i : natural range 0 to 1023:=0; + signal timeout,timeout_i : natural range 0 to 4095:=0; signal PortStat : std_logic_vector(3 downto 0):=(others=>'0'); signal PeerPort : natural range 0 to 15:=0; -- désigne le port qui emet une requête @@ -219,13 +226,23 @@ StatAsked<=StatAsked_i; n<=n_i; + Ht_Start<=Ht_Start_i; + Grp_Id<=Grp_Id_i; + vPeerStat<=vPeerStat_i; SpawnNbAck<=SpawnNbAck_i; AppSize<=AppSize_i; Ready<=Rdy; snd_start<=snd_start_i; + SpawnNbReq_q<=SpawnNbReq; + SpawnReq_Q<=SpawnReq; + SpawnCmd0_Q<=SpawnCmd0; + SpawnCmd1_Q<=SpawnCmd1; + SpawnCmd2_Q<=SpawnCmd2; + Spawn_grp_q<=Spawn_grp; end if; end process; - Init2_DECODE: process (stinit2, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, - SpawnOn,Ram_NextAdress,PeerRTS,PortSTAT,dma_rd,dma_wr,Send_rdy,I_Send_rdy,rd_ok,wr_ok,Instruction) + Init2_DECODE: process (stinit2,n, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, + SpawnOn,Ram_NextAdress,PeerRTS,PortSTAT,dma_rd,dma_wr,Send_rdy,I_Send_rdy,rd_ok,wr_ok,Instruction, + MainPort,PeerStat,SpawnCmd0,SpawnCmd1,SpawnCmd2,SpawnInit,BCast_rdy) variable nextr,nextadr : natural :=0;--to_integer(unsigned(Ram_NextAdress)); variable nport : natural range 0 to 15:=0; @@ -466,5 +483,5 @@ RTS_cmd<='0'; RTS_I<='0'; - CTR<='1'; + CTR<=not MainResp; ResultOut<=(others=>'0'); PortNum_i<=DataReceived(0)(3 downto 0); --adresse du Main Port @@ -609,5 +626,5 @@ DS_ACK<=DS_RDY; BCAST<='0'; - CTR<='1'; --cette mise à 1 permet de ctrler la fin de réception + CTR<='0'; --cette mise à 1 permet de ctrler la fin de réception rdy<='0'; ram_wr<=wr_ok; @@ -620,8 +637,8 @@ dma_wr_request <=dma_wr; RankAsked_i<='0'; - if SpawnInit='1' then - ResultOut<=("01000000");--spawn completed + if n>=3 then + ResultOut<=("00000010");--spawn completed else - ResultOut<=("00000010");--spawn message received + ResultOut<=("00000000");--spawn message received end if; @@ -629,5 +646,5 @@ RTS_cmd<='0'; --RTS_DAT<='1'; --à tester - RTS_I<='1'; -- pour le timing + RTS_I<=PeerRTS; -- pour le timing Result_En<='0'; DS_ACK<='0'; @@ -637,15 +654,15 @@ ram_wr<=wr_ok; ram_rd<=rd_ok; - DataToSend(0)<=MPI_SPAWN & SpawnDest; + DataToSend(0)<=SpawnCmd0; DataToSend(1)<="00000100"; - DataToSend(2)<=PeerStat(7 downto 0); - DataToSend(3)<=SpawnCmd; -- SPAWN_LOAD & MyPort ; + DataToSend(2)<=SpawnCmd1; + DataToSend(3)<=SpawnCmd2; -- SPAWN_LOAD & MyPort ; Send_Ack<=Send_Rdy; I_Send_Ack<=I_Send_rdy; RankAsked_i<='0'; if SpawnInit='1' then - ResultOut<=("01000000"); --spawn completed + ResultOut<=("10000000"); --spawn completed else - ResultOut<=("00000010");--spawn message received + ResultOut<=("01000000");--spawn in progress end if; When ErrSpawn => @@ -705,9 +722,10 @@ --================== NEXT_STInit2_DECODE: process (stInit2,AppReq,Instruction_en, AppAck,PortNumFlag,EquFlag,MainResp,StatAsked,RankAsked,RankSent,CM_RDY, CmdReceived, - BCast_Rdy, DS_RDY, DataReceived, Send_RDY, I_Send_RDY,TimeOut,Dma_rd_grant,Dma_wr_grant,cpt,n,clk_cyl,IsMain_i,SpawnOn) + BCast_Rdy, DS_RDY, DataReceived,Ht_Start,vPeerStat, Send_RDY, I_Send_RDY,TimeOut,Dma_rd_grant,Dma_wr_grant,cpt,n,clk_cyl,IsMain_i,SpawnOn, + Instruction,Hcl_Init,Spawn_done,mainport,PeerStat,PeerRTS,Rec_Data,SpawnInit,grp_id,SpawnNbReq,Ram_data_out,Spawn_grp,MyPort) variable InitTimeOut :natural:=0; variable LastPort,Ht_hole : std_logic:='0'; - variable i,htloc,ht_Start : natural range 0 to 15:=0; - variable vPeerStat : std_logic_vector(15 downto 0); + variable i,nbSpawn,htloc,Ht_Id : natural range 0 to 15:=0; + --variable vPeerStat : std_logic_vector(15 downto 0); variable vPortStat,nulvect : std_logic_vector(3 downto 0):="0000"; variable tempval : std_logic_vector(Word-1 downto 0); @@ -717,4 +735,14 @@ --insert statements to decode next_state --below is a simple example + vPeerStat_i<=vPeerStat; + SpawnNbReq<=SpawnNbReq_q; + SpawnReq<=SpawnReq_q; + Ht_Start_i<=Ht_Start; + SpawnCmd0<=SpawnCmd0_Q; + SpawnCmd1<=SpawnCmd1_Q; + SpawnCmd2<=SpawnCmd2_Q; + for i in 0 to 3 loop + Spawn_grp(i)<=Spawn_grp_q(i); + end loop; case (stInit2) is @@ -736,6 +764,6 @@ Next_stInit2 <=SendApp; end if; - elsif portNumFlag='1' and IsMain_i='0' then - Next_stInit2 <=AskPeerStat; --recevoir les nouvelles données sur l'état d'initialisation + elsif HCL_Init='1' and IsMain_i='0' then + Next_stInit2 <=SendApp; --ignorer ce message simplement else Next_stInit2 <=GetPortNum; -- initialiser la bibliothèque normalement @@ -841,4 +869,5 @@ Next_stInit2<=GetPeerStat; StatAsked_i<='1'; + MainResp<='0'; n_i<=0; End if; @@ -857,5 +886,5 @@ end if; - elsif TimeOut=800 then + elsif TimeOut=1800 then --essayer de redemander les statistiques Timeout_i<=0; @@ -927,4 +956,10 @@ TimeOut_i<=0; -- prépare le traitement de la prochaine requête -- d'attente des ports + elsif Timeout=800 then + assert true report "Impossible d'envoyer le rang" + severity failure; + timeout_i<=0; + else + TimeOut_i<=TimeOut+1; end if; When RegRank => @@ -1005,12 +1040,12 @@ if statAsked='1' then -- Next_stInit2<=ReadNoc; - -- else + Next_stInit2<=SendApp; --terminer l'application end if; - elsif TimeOut_i=100 then + elsif TimeOut=100 then Next_stInit2 <=EndInit; else - TimeOut_i<=TimeOut_i+1; + TimeOut_i<=TimeOut+1; end if; else @@ -1026,23 +1061,34 @@ if n=0 then - SpawnNbReq<=to_integer(unsigned(Instruction(3 downto 0))); -- sauver le nombre de HT à créer + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + vPeerStat_i<=PeerStat; --récupérer la situation actuelle des tâches créées if IsMain_i='1' and SpawnInit='0' then - n_i<=1; + SpawnNbReq<=to_integer(unsigned(Instruction(3 downto 0))); -- sauver le nombre de HT à créer + + n_i<=1; + SpawnReq(ht_id)<='1'; --Note l'id de HT qui a appelé le Spawn elsif IsMain_i='1' and SpawnInit='1' then -- il faut envoyer les acquittements - vPeerStat:=PeerStat; --récupérer la situation actuelle des tâches créées - Ht_start:=0; --compte le nombre de tâches chargées + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + Spawn_grp(grp_id)(ht_id)<='1'; --noter le port du Fils Spawné dans ce groupe + Ht_start_i<=0; --compte le nombre de tâches chargées n_i<=6; + else if SpawnOn='1' then --if IsMain_i='0' then -- il faut juste charger puis activer la tâche n_i<=7; - end if; + end if; + assert true + Report "SpawnLoad : Cas non prévu !" + severity failure; end if; elsif n=1 then - ht_hole:='0'; - L1: for i in 0 to 7 loop + if PeerStat=SpawnReq then --tous les Hts ont appelés Spawn ? + ht_hole:='0'; + L1: for i in 0 to 15 loop if vPeerStat(i)='0' then SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à activer - vPeerStat(i):='1'; - Ht_Start:=Ht_Start+1; + SpawnCmd0<=MPI_SPAWN & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='1'; + Ht_Start_i<=Ht_Start+1; Ht_Hole:='1'; -- une place a été trouvé else @@ -1053,9 +1099,14 @@ if Ht_hole='0' then -- toutes les tâches n'ont pas été créés -- aller à la fin ! en signalant une erreur! - SpawnCMd<=Spawn_Err & "0001"; --erreur pas assez de ports sur le NoC - n_i<=7; + SpawnCMd2<=Spawn_Err & "0001"; --erreur pas assez de ports sur le NoC + n_i<=9; else n_i<=n+1; - SpawnCmd<=SPAWN_START & MyPort; + SpawnCmd1<=PeerStat(7 downto 0); + SpawnCmd2<=SPAWN_START & MyPort; + end if; + else --Tous les Hts n'ont pas appelé Spawn encore + Next_stInit2<=SendApp; --on termine normalement + n_i<=0; end if; elsif n=2 then @@ -1069,5 +1120,5 @@ elsif n=4 then if SpawnInit='0' then - if Ht_Start=SpawnNbReq then + if Ht_Start>=SpawnNbReq then n_i<=n+1; else @@ -1075,47 +1126,68 @@ end if; else - n_i<=6; -- passer au contact du HT suivant + n_i<=7; -- passer au contact du HT suivant end if; elsif n=5 then - -- donner le résultat du Spawn - Next_stinit2<=SendApp; - n_i<=0; + -- Aller à la fin le résultat du Spawn + + n_i<=10; elsif n=6 then + nbSpawn:=0; + for i in 0 to 15 loop + if Spawn_grp(grp_id)(i)='1' then + nbSpawn:=nbSpawn+1; + end if; + end loop; + if nbSpawn=SpawnNbReq then + n_i<=n+1; --aller renvoyer les réponses + else + n_i<=10; --fin du Spawn + + end if; + elsif n=7 then Ht_hole:='0'; -L2: for i in 0 to 7 loop - if PeerStat(i)='1' then +L2: for i in 0 to 7 loop --for i in Ht_start to 7 loop + if i>=Ht_start then + if vPeerStat(i)='1' and Spawn_grp(grp_id)(i)='0' then --on avertit les membres du groupe parent + --mais pas ceux du groupe Fils ! SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à avertir - vPeerStat(i):='1'; - Ht_Start:=Ht_Start+1; + SpawnCmd0<=MPI_ACK & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='0'; + Ht_Start_i<=i+1; -- le prochain Ht à prévenir Ht_Hole:='1'; -- Une tâche doit être avertie - n_i<=n+1; else Ht_hole:='0'; -- end if; + end if; exit L2 when ht_hole='1'; end loop L2; + n_i<=n+1; + elsif n=8 then if Ht_hole='1' then -- - -- aller à la fin ! en signalant une erreur! - SpawnCMd<=Spawn_COMP & "0001"; -- fin du Spawn - n_i<=2; --envoyer la la donnée sur le réseau + -- un HT existant à prévenir ! + SpawnCmd1<=Spawn_grp(grp_id)(7 downto 0); + SpawnCMd2<=MPI_SPAWN & MyRank; -- fin du Spawn + n_i<=2; --envoyer la donnée sur le réseau + elsif vpeerstat /=spawn_grp(grp_id) then --il ne reste plus de membres à prévenir ? + n_i<=7; --on est sorti mais ce n'est pas la fin + else -- fin du Spawn car tous ont été averti - n_i<=8; - - end if; - - - elsif Ismain_i='1' and SpawnInit='1' then - if SpawnNbAck+1=SpawnNbReq then - -- il faut envoyer un message à tous les noeuds pour avertir de la fin du Spawn - - else - SpawnNbAck_i<=SpawnNbAck+1; - Next_stInit2<=SendApp; --on attend le suivant - end if; - end if; + n_i<=10; + SpawnNbReq<=0; + SpawnReq<=(others=>'0'); + vPeerStat_i<=(others=>'0'); + grp_id_i<=grp_id+1; --incrementer le compteur de groupes************ + end if; + elsif n=9 then + assert true report "error in Spawn command" + severity failure; + elsif n=10 then + n_i<=0; + Next_stInit2<=SendApp; + end if; When SpawnApp=> --Mise à jour du bit 6 du registre status du COre. - if n <3 then + if n>=0 and n <4 then dma_wr<='1'; --demander un accès exclusif au bus @@ -1129,22 +1201,22 @@ if DS_RDY='1' then --- if Datareceived(3)(7 downto 4)=SPAWN_START then + n_i<=n+1; else - n_i<=6; --erreur instruction incorrecte + Next_stInit2<=ErrSpawn; + n_i<=0; --erreur instruction incorrecte end if; - if dma_rd_grant='1' then - n_i<=n+1; - end if; + rd_ok<='1'; wr_ok<='0'; end if; - elsif n=1 then + elsif n=1 or n=2 then if dma_rd_grant='1' then n_i<=n+1; - + tempval:=Ram_data_out; end if; rd_ok<='1'; wr_ok<='0'; - - elsif n=2 then + + elsif n=3 then if dma_rd_grant='1' and dma_wr_grant='1' then n_i<=n+1; @@ -1159,16 +1231,22 @@ wr_ok<='0'; end if; - elsif n=3 then + elsif n=4 then if spawninit='0' then Spawn_done<='1'; end if; + rd_ok<='0'; + wr_ok<='0'; + n_i<=0; Next_stInit2<=EndInit; end if; When ErrSpawn => + assert true + report "Ex4/stInit2/SpawnApp:Erreur lors de Spawn" + severity failure; Next_stInit2<=Init; When EndInit=> - + StatAsked_i<='0'; --reset de ces variables Next_stInit2<=Init; end case; @@ -1232,5 +1310,5 @@ begin -- - if rising_edge(clk) then + if reset='1' then etrec<=r_wait; @@ -1239,4 +1317,5 @@ bad_paquet:='0'; else + if rising_edge(clk) then case etrec is when r_wait => @@ -1254,4 +1333,9 @@ bad_paquet:='0'; SpawnOn<='1'; --le spawn est actif + elsif Instruction_en='0' and CTR='0' and Hcl_init= '0' then + --il faut éliminer ce paquet qui est inoportun ! + Bad_paquet:='1'; + etrec<=r_dlen; --il faut ignorer cette donnée et quitter + dcount:=1; elsif CTR='1' then if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN or ptype=INIT_REGISTER then @@ -1356,14 +1440,12 @@ --rPort_out_rd_en <='0'; - SpawnOn<='0'; -- annuler le signal de Spawn - if DS_ACK='1' or rtimeout> 30 or CTR='0' or bad_paquet='1' then + + if DS_ACK='1' or rtimeout> 30 or (CTR='0' and SpawnOn='0') or bad_paquet='1' then DS_RDY<='0'; + SpawnOn<='0'; etrec<=r_wait; else DS_RDY<=DS_RDY; - end if; - - - + end if; end case; end if;--reset='1' @@ -1548,5 +1630,5 @@ begin - if rising_edge(clk) then + if reset='1' then etcmd<=cmdstart; @@ -1554,4 +1636,5 @@ -- sorigport<=origport; else + if rising_edge(clk) then case etcmd is when cmdstart => @@ -1723,6 +1806,7 @@ i_send_val:process(HCL_Init,Send_RDY,RTS_I,Snd_Ack,I_send_ack,DataToSend,Bcast_rdy,Bcast) begin +snd_start_i<=snd_start; if HCL_Init='1' then - if RTS_I='1' and i_send_ack='0' then + if RTS_I='1' and snd_ack='0' then snd_start_i<='1'; elsif i_send_ack='1' then @@ -1741,4 +1825,7 @@ end if; i_send_rdy<=send_rdy; + for i in 0 to 3 loop + Snd_data(i)<=(others=>'0'); + end loop; end if; end process; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/FIFO_64_FWFT.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/FIFO_64_FWFT.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/FIFO_64_FWFT.vhd (revision 74) @@ -66,5 +66,5 @@ signal push_address_counter : std_logic_vector(5 downto 0); signal pop_address_counter : std_logic_vector(5 downto 0); -signal fifo_counter : std_logic_vector(5 downto 0); +signal fifo_counter : std_logic_vector(5 downto 0):=(others=>'0'); --autre signaux signal rd_ready : std_logic:='0'; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_4.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_4.vhd (revision 74) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_4.vhd (revision 74) @@ -0,0 +1,526 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:04:21 04/22/2013 +-- Design Name: +-- Module Name: HT_process - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +library NocLib ; +use std.textio.all; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +--entity HT_process is +-- generic (Task_id : natural:=0); +-- Port ( clk : in STD_LOGIC; +-- reset : in STD_LOGIC; +-- en : in std_logic; -- active la tâche +-- Interf_i : in core_i; --signaux pour l'interface IO +-- Interf_o : out core_o; --signaux pour l'interface IO +-- mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire +-- mem_i : in typ_dpram_i -- signaux pour l'accès à la mémoire +-- ); +--end HT_process; + +architecture A2 of HT_process is + + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart, + putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout); + signal sram : typ_dpram; + signal MyGroup:mpi_group; + signal MyWin : mpi_win; + signal MyRank :std_logic_vector(3 downto 0); + signal intercomm,array_of_errcodes : natural; + signal ct_state:natural:=0; +signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque +signal RunState : typ_mae; + +begin + +--MAE du PE +--======================================================================= +-- Interf<=Libr; + + + pPutGet:process(clk,reset,en) + + constant DATAPTR : natural :=256; + variable nb_rma:natural range 0 to 15:=0; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen,dcount : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable mywin : Mpi_win; + variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn + variable comm : natural :=0; + variable Spawn_on: std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + + --======================================================= + --variables pour la création du fichier de résultats + -- synthesis translate_off + type char_file is file of character; + file f: text; + variable status :file_open_status ; + variable char_count: integer range 0 to 65536 := 0; + variable str: string (1 to 79) ; + variable L: line; + variable fopened: std_logic:='0'; + + constant simres : time :=1 ps; --simulation resolution + constant realres : real :=1.0e-3; --ramener le temps en ns + -- returns real value of time parameter using pure VHDL + function rt(t : time) return real is + begin + return real(t/simres) * realres; + end; + -- synthesis translate_on +--====================================================== + begin + --=== Partie combinatoire du process =================================== + + --=== Fin de la partie combinatoire du process ========================== + + + + --end loop; + + if (clk'event and clk='1') and en='1' then + + + if reset='1' then + RunState<=start; + + else + --========================================================== + --affectation des entrées sorties mémoires + sram.i.data_out<=mem_I.data_out; + mem_o.addr_wr<=sram.O.addr_wr; + mem_o.addr_rd<=sram.O.addr_rd ; + mem_o.we<=sram.O.we; + mem_o.ena<=sram.O.ena; + mem_o.enb<=sram.O.enb; + mem_o.data_in<=sram.O.data_in; + --affectation des entrées sorties MPI_HCL + Interf_o.Instr_EN<=Libr.O.instr_en; + Interf_o.Membusy<=Libr.O.MemBusy; + Interf_o.Instruction<=Libr.O.Instruction; + Libr.i.Instr_ack<=Interf_i.Instr_ack; + Libr.i.InitOk<=Interf_i.InitOk; + Libr.i.Hold_Req<=Interf_i.Hold_req; + Libr.I.Spawned<=Interf_i.Spawned; + --Libr.i.Hold_Ack<=Interf_i.Hold_Ack; + Libr.i.RamSel<=Interf_i.RamSel; + --ct_state<=ct; --pour débogage + --============================================================ + + case RunState is + when start => + --Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=Fillmem; + end if; + --Ram_busy<='0'; + Libr.O.MemBusy<='0'; + Libr.O.Instr_En<='0'; + + adresse:=10;--DATAPTR; + + adresse_rd:=0; + timeout:=0; + --dcount<=0; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + -- synthesis translate_off + if fopened='0' then + file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE); + --while not endfile(c_file_handle) loop + --end if; + + --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); + --report l.all; + -- writeline (f, l) ; + fopened:='1'; + end if; + -- synthesis translate_on + when Fillmem => + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='0'; + if Libr.I.Ramsel='0' then + + sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + Libr.O.Instr_En<='0'; + dcount:=dcount+1; + + if dcount=250 then + bfill:=bfill+1; + + if bfill=4 then + RunState<=InitApp; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=250*bfill+10; + + dcount:=0; + ct:=0; + RunState<=Fillmem; + Libr.O.Instr_En<='0'; + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='0'; + when InitApp => + --code pour Init + dlen:=15; + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Init(ct,Libr,Clk,SRam); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + + when GetRank => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + + if ct=0 then + RunState<=WinCreate; + -- synthesis translate_off + write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when Wincreate => --par défaut la fenêtre 0 est utilisée ! + case MyRank is + when x"0"=> + Mygroup.grp<=x"0002";-- rank 1 + MyGroup.nb<=2; + destRank:=1; + DestAdr:=X"043F"; + nb_rma:=1; + when x"1" => + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + DestAdr:=X"043F"; + when x"2" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"044F"; + when x"3" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"045F"; + when others => --cas des processus spawn + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + end case; + RunState<=WinPost; + when WinPost => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin); + + if ct=0 then + if spawn_on='1' then + RunState<=WinWait; + else + RunState<=WinStart; + end if; + -- synthesis translate_off + write (l,string'("Dlen; ;WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinStart => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=PutData; + -- synthesis translate_off + write (l,string'("Dlen; ;WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when putdata => --construire le packet pour le Put + + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + --DestAdr:=X"033F"; + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=GetData; + -- synthesis translate_off + report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now)); + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when getdata => --positionnement du mot de longueur des données + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"006D"; + DestAdr:=X"1400"; + if unsigned(MyRank) = 0 then + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + else + + --pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win); + end if; + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + if unsigned(MyRank)/=0 then + RunState<=wincompleted; + else + nb_rma:=nb_rma+1; + if nb_rma=2 then + RunState<=wincompleted; + nb_rma:=0; + end if; + end if; + -- synthesis translate_off + assert ct/=0 report "GET_END " & integer'image(destrank) + severity Warning ; + write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinCompleted => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_Complete(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + RunState<=WinWait; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when WinWait => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_wait(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if Libr.I.Spawned='1' then + RunState<=Finalize; + elsif spawn_on='1' then + RunState<=Finalize; + else + RunState<=MpiSpawn; + end if; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + + when MpiSpawn => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + --(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + + maxprocs:=2; + pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if unsigned(MyRank)=0 then + Spawn_on:='1'; + Mygroup.grp<=x"000C";-- rank 3,4 + destRank:=0; + runstate<=WinPost; + else + RunState<=Finalize; + end if; + + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when finalize => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + if ct=0 then + RunState<=start; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + file_close(f); + -- synthesis translate_on + end if; + + when st_timeout => + + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + + RunState<=start; + end case; + ct_state<=ct; --pour débogage + end if; + end if; + + end process pPutGet; + +end a2; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_process.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_process.vhd (revision 74) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_process.vhd (revision 74) @@ -0,0 +1,512 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:04:21 04/22/2013 +-- Design Name: +-- Module Name: HT_process - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +library NocLib ; +use std.textio.all; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity HT_process is + generic (Task_id : natural:=0); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + en : in std_logic; -- active la tâche + Interf_i : in core_i; --signaux pour l'interface IO + Interf_o : out core_o; --signaux pour l'interface IO + mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire + mem_i : in typ_dpram_i -- signaux pour l'accès à la mémoire + ); +end HT_process; + +architecture Behavioral of HT_process is + + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart, + putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout); + signal sram : typ_dpram; + signal MyGroup:mpi_group; + signal MyWin : mpi_win; + signal MyRank :std_logic_vector(3 downto 0); + signal intercomm,array_of_errcodes : natural; + signal ct_state:natural:=0; +signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque +signal RunState : typ_mae; + +begin + +--MAE du PE +--======================================================================= +-- Interf<=Libr; + + + pPutGet:process(clk,reset,en) + + constant DATAPTR : natural :=256; + variable nb_rma:natural range 0 to 15:=0; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen,dcount : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable mywin : Mpi_win; + variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn + variable comm : natural :=0; + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + + --======================================================= + --variables pour la création du fichier de résultats + -- synthesis translate_off + type char_file is file of character; + file f: text; + variable status :file_open_status ; + variable char_count: integer range 0 to 65536 := 0; + variable str: string (1 to 79) ; + variable L: line; + variable fopened: std_logic:='0'; + + constant simres : time :=1 ps; --simulation resolution + constant realres : real :=1.0e-3; --ramener le temps en ns + -- returns real value of time parameter using pure VHDL + function rt(t : time) return real is + begin + return real(t/simres) * realres; + end; + -- synthesis translate_on +--====================================================== + begin + --=== Partie combinatoire du process =================================== + + --=== Fin de la partie combinatoire du process ========================== + + + + --end loop; + + if (clk'event and clk='1') and en='1' then + + + if reset='1' then + RunState<=start; + + else + --========================================================== + --affectation des entrées sorties mémoires + sram.i.data_out<=mem_I.data_out; + mem_o.addr_wr<=sram.O.addr_wr; + mem_o.addr_rd<=sram.O.addr_rd ; + mem_o.we<=sram.O.we; + mem_o.ena<=sram.O.ena; + mem_o.enb<=sram.O.enb; + mem_o.data_in<=sram.O.data_in; + --affectation des entrées sorties MPI_HCL + Interf_o.Instr_EN<=Libr.O.instr_en; + Interf_o.Membusy<=Libr.O.MemBusy; + Interf_o.Instruction<=Libr.O.Instruction; + Libr.i.Instr_ack<=Interf_i.Instr_ack; + Libr.i.InitOk<=Interf_i.InitOk; + Libr.i.Hold_Req<=Interf_i.Hold_req; + Libr.I.Spawned<=Interf_i.Spawned; + --Libr.i.Hold_Ack<=Interf_i.Hold_Ack; + Libr.i.RamSel<=Interf_i.RamSel; + --ct_state<=ct; --pour débogage + --============================================================ + + case RunState is + when start => + --Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=Fillmem; + end if; + --Ram_busy<='0'; + Libr.O.MemBusy<='0'; + Libr.O.Instr_En<='0'; + iack:='0'; + adresse:=10;--DATAPTR; + + adresse_rd:=0; + timeout:=0; + --dcount<=0; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + -- synthesis translate_off + if fopened='0' then + file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE); + --while not endfile(c_file_handle) loop + --end if; + + --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); + --report l.all; + -- writeline (f, l) ; + fopened:='1'; + end if; + -- synthesis translate_on + when Fillmem => + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='0'; + if Libr.I.Ramsel='0' then + + sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + Libr.O.Instr_En<='0'; + dcount:=dcount+1; + + if dcount=250 then + bfill:=bfill+1; + + if bfill=4 then + RunState<=InitApp; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=250*bfill+10; + + dcount:=0; + ct:=0; + RunState<=Fillmem; + Libr.O.Instr_En<='0'; + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='0'; + when InitApp => + --code pour Init + dlen:=15; + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Init(ct,Libr,Clk,SRam); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + + when GetRank => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + + if ct=0 then + RunState<=WinCreate; + -- synthesis translate_off + write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when Wincreate => --par défaut la fenêtre 0 est utilisée ! + case MyRank is + when x"0"=> + Mygroup.grp<=x"000E";-- rank 1,2,3 + MyGroup.nb<=2; + destRank:=1; + DestAdr:=X"043F"; + nb_rma:=1; + when x"1" => + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + DestAdr:=X"043F"; + when x"2" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"044F"; + when x"3" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"045F"; + when others => --cas des processus spawn + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + end case; + RunState<=WinPost; + when WinPost => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin); + + if ct=0 then + RunState<=WinStart; + -- synthesis translate_off + write (l,string'("Dlen; ;WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinStart => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=PutData; + -- synthesis translate_off + write (l,string'("Dlen; ;WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when putdata => --construire le packet pour le Put + + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + --DestAdr:=X"033F"; + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=GetData; + -- synthesis translate_off + report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now)); + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when getdata => --positionnement du mot de longueur des données + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"006D"; + DestAdr:=X"1400"; + if unsigned(MyRank) = 0 then + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + else + + --pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win); + end if; + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + if unsigned(MyRank)/=0 then + RunState<=wincompleted; + else + nb_rma:=nb_rma+1; + if nb_rma=2 then + RunState<=wincompleted; + nb_rma:=0; + end if; + end if; + -- synthesis translate_off + assert ct/=0 report "GET_END " & integer'image(destrank) + severity Warning ; + write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinCompleted => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_Complete(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + RunState<=WinWait; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when WinWait => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_wait(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if unsigned(Myrank)>3 then + RunState<=Finalize; + else + RunState<=MpiSpawn; + end if; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + + when MpiSpawn => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + --(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + + maxprocs:=2; + pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + RunState<=Finalize; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when finalize => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + if ct=0 then + RunState<=start; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + file_close(f); + -- synthesis translate_on + end if; + + when st_timeout => + + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + + RunState<=start; + end case; + ct_state<=ct; --pour débogage + end if; + end if; + + end process pPutGet; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/Hold_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/Hold_FSM.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/Hold_FSM.vhd (revision 74) @@ -53,5 +53,5 @@ end if; end process hold_sync; - Ramsel_state:process(clk,reset)--,HoldState,Hold_Req,ram_Busy,Front_HReq,Front_RBusy) + Ramsel_state:process(clk)--,HoldState,Hold_Req,ram_Busy,Front_HReq,Front_RBusy) begin @@ -65,7 +65,9 @@ case HoldState is when Ht_free => - if Hold_Req='1' and ram_busy='0' then + if Hold_Req='1' and ram_busy='0' then HolDState <=Core_lock; elsif Hold_Req='0' and ram_busy='1' then + HoldState <=HT_lock; + elsif Hold_Req='1' and ram_busy='1' then HoldState <=HT_lock; else Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise (revision 74) @@ -23,7 +23,25 @@ + + + + + + + + + + + + + + + + + + @@ -147,7 +165,5 @@ - - @@ -157,6 +173,4 @@ - - @@ -292,14 +306,9 @@ - - - - - - - - - - + + + + + @@ -367,17 +376,17 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -445,5 +454,5 @@ - + @@ -452,33 +461,33 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -486,19 +495,14 @@ - + + + + + + + + - - - - - - - - - - - - @@ -506,58 +510,30 @@ - - - - - - - - + + + + + + + + - - - + + + + - - - + + - - - - - - - - + + + + - - - - - - - - - - - - - - - - - - - - - - - - Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise (revision 74) @@ -376,5 +376,5 @@ - + @@ -444,7 +444,7 @@ - - - + + + @@ -522,10 +522,10 @@ - + - + @@ -538,8 +538,8 @@ - - - - + + + + @@ -567,5 +567,5 @@ - + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_NOC.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_NOC.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_NOC.vhd (revision 74) @@ -116,5 +116,5 @@ -- instancier le switch et connecter les différents ports -switch_gen1: SWITCH_GEN generic map (NPROC) +sw_gen1: SWITCH_GEN generic map (NPROC) PORT MAP ( Port_in => Noc_PortIn, @@ -133,5 +133,5 @@ ); end generate; - connect_core: for i in 1 to nproc generate -- nproc +HCL_c: for i in 1 to nproc generate -- nproc hardmpi:core_mpi port map ( Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_RMA.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_RMA.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_RMA.vhd (revision 74) @@ -43,4 +43,8 @@ procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; AdrVect:in std_logic_vector; Data:in std_logic_vector); + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic); + end MPI_Rma; @@ -86,11 +90,11 @@ if interf.I.ramsel='0' then Interf.O.membusy<='0'; - SysRam.O.we<='1'; - SysRam.O.ena<='1'; - SysRam.O.enb<='0'; + --SysRam.O.we<='1'; + --SysRam.O.ena<='1'; + SysRam.O.enb<='1'; wr_state:=interf.S.Intstate1; WritePtr (put_adr,wr_state,SysRam); interf.S.Intstate1<=wr_state; - if wr_state =4 then + if wr_state =0 then -- fin de l'écriture du pointeur en mémoire dcount:=4; @@ -251,4 +255,6 @@ variable i,wcount,dcount : natural range 0 to 255:=0; variable adresse :natural; +variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0'); +variable bitval : std_logic:='0'; variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; @@ -270,4 +276,5 @@ if dcount =0 then dcount:=dcount+1; + Interf.S.IntState1<=0; elsif dcount>=1 and dcount <=3 then if interf.I.ramsel='0' then @@ -279,8 +286,11 @@ Interf.S.IntState1<=wcount; Interf.O.membusy<='1'; - if wcount =4 then + if wcount =0 then dcount:=4; Interf.S.Intstate1<=1; - end if; + end if; + else + Interf.S.IntState1<=0; + end if; @@ -318,6 +328,5 @@ dcount:=dcount+1; - else - dcount:=dcount-1; + end if; elsif dcount=7 then @@ -330,6 +339,4 @@ dcount:=dcount+1; - else - dcount:=dcount-1; end if; elsif dcount=8 then @@ -342,6 +349,4 @@ Interf.O.membusy<='1'; dcount:=dcount+1; - else - dcount:=dcount-1; end if; elsif dcount=9 then @@ -352,29 +357,42 @@ SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - Interf.O.membusy<='0'; + Interf.O.membusy<='1'; dcount:=dcount+1; end if; - elsif dcount=10 then + elsif dcount=10 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+7; + SysRam.O.Data_in<=x"00"; -- résultat du GET + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.S.IntState2<=0; + dcount:=dcount+1; + end if; + elsif dcount=11 then SysRam.O.we<='1'; SysRam.O.ena<='1'; SysRam.O.enb<='1'; - adresse:=core_base_adr+1; - SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); - SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; - Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction - if interf.I.ramsel='0' then - dcount:=dcount+1; - end if; - elsif dcount=11 then + addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + wcount:=Interf.S.IntState2; + wdata:=x"01";bitval:='1'; + setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval); + Interf.S.IntState2<=wcount; + if wcount=0 then + dcount:=dcount+1; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + end if; + + elsif dcount=12 then if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction dcount:=dcount+1; config_reg:=SysRam.I.Data_out and x"f6"; - SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + --SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; end if; adresse:=core_base_adr+1; - SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); --SysRam.O.Ram_busy<='0'; --?? @@ -383,5 +401,5 @@ SysRam.O.enb<='1'; Interf.O.membusy<='0'; - elsif dcount=12 then + elsif dcount=13 then adresse:=core_base_adr+1; @@ -389,4 +407,7 @@ SysRam.O.ena<='1'; -- préparer l'écriture du résultat du get SysRam.O.enb<='1'; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then config_reg:=SysRam.I.Data_out and x"f6"; @@ -395,8 +416,6 @@ Interf.O.membusy<='1'; end if; - SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); - SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - - elsif dcount=13 then + + elsif dcount=14 then SysRam.O.we<='1'; @@ -408,8 +427,51 @@ config_reg:=SysRam.I.Data_out and x"f6"; SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=18;--dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=15 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy dcount:=dcount+1; - Interf.O.membusy<='0'; + Interf.O.membusy<='1'; end if; - elsif dcount=14 then + elsif dcount=16 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=17 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; + SysRam.O.Data_in<=config_reg ; --; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount>=18 and dcount <=21 then SysRam.O.we<='0'; SysRam.O.ena<='0'; @@ -420,14 +482,32 @@ if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! dcount:=dcount+1; - end if; end if; + elsif dcount>=22 and dcount <=24 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI Get bien reçu ! + dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème ! + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + else + -- dcount:=1;--recommencer l'envoi + end if; + end if; - elsif dcount=15 then + elsif dcount=25 then dcount:=0; --fin normale de la fonction Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; end if; - - + NExtCtx:=dcount; end if; @@ -494,4 +574,5 @@ if interf.I.ramsel='0' then Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); NextCtx:=4; Interf.O.membusy<='1'; @@ -505,4 +586,5 @@ if interf.I.ramsel='0' then Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); NextCtx:=0; Interf.O.membusy<='0'; @@ -722,9 +804,21 @@ SysRam.O.Data_in<=x"01"; NextCtx:=NextCtx+1; - Interf.O.membusy<='0'; + Interf.O.membusy<='1'; end if; - elsif NextCtx=3 then + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then NextCtx:=0; Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; end if; @@ -735,5 +829,5 @@ variable wcount: natural range 0 to 255:=0; variable LRam : typ_dpRam; -variable SyncDest : natural range 0 to 15; --destination du message de synchronisation +variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation variable W0 :std_logic_vector(Word-1 downto 0); variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); @@ -741,12 +835,12 @@ begin -- - --pMPI_Win_Wait(NextCtx, Interf, SysRam, Win ); wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); LRam:=SysRam; -- nécessaire pour le débogage if NextCtx =0 then - SysRam.O.we<='1'; - SysRam.O.ena<='1'; - SysRam.O.enb<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.MemBusy<='1'; --occuper la mémoire Interf.S.IntState1<=0; NextCtx:=1; @@ -766,10 +860,11 @@ Interf.O.Instr_En<='0'; Interf.O.membusy<='1'; - + SysRam.O.we<='1'; + SysRam.O.ena<='1'; wcount:=Interf.S.IntState1; - WritePtr (wcompl_adr,wcount,SysRam); + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir Interf.S.IntState1<=wcount; - if wcount =4 then + if wcount =0 then NextCtx:=2; Interf.S.IntState1<=0; @@ -779,48 +874,79 @@ adresse:=core_wcompl_adr; SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - end if; + end if; + else + Interf.S.IntState1<=0; --recommencer l'écriture du pointeur end if; elsif NextCtx=2 then - SysRam.O.we<='1'; - SysRam.O.ena<='1'; - SysRam.O.enb<='0'; + if Interf.I.Ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; adresse:=core_wcompl_adr; - NextCtx:=9; --aller à la fin de la fonction - for i in interf.s.intState2 to 7 loop + NextCtx:=10; --aller à la fin de la fonction + i:=0; + l1:for i in 0 to 7 loop + -- i:=i+1; + if i>=interf.s.intState2 then if interf.s.gstart(i)='1' then SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); Interf.S.tmem(0)(i)<='0'; --ce dest a été traité ! - NextCtx:=3; + NextCtx:=4; Interf.S.IntState2<=i+1; - exit; + exit l1; end if; - end loop; + end if; + exit l1 when i=7; + end loop l1; + end if; elsif NextCtx=3 then - SysRam.O.we<='1'; - SysRam.O.ena<='1'; - SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + SysRam.O.Data_in<= Interf.S.tmem(2); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if wcount=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=4 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; adresse:=core_wcompl_adr+1; SysRam.O.Data_in<= x"04" ; SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); NextCtx:=NextCtx+1; - elsif NextCtx=4 then - SysRam.O.we<='1'; - SysRam.O.ena<='1'; - SysRam.O.enb<='0'; + elsif NextCtx=5 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; adresse:=core_wcompl_adr+2; Interf.O.Instruction<=x"04";--longueur de l'instruction SysRam.O.Data_in<=x"00" ;-- SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - NextCtx:=5; - elsif NextCtx=5 then - SysRam.O.we<='1'; - SysRam.O.ena<='1'; - SysRam.O.enb<='0'; + NextCtx:=6; + elsif NextCtx=6 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; adresse:=core_wcompl_adr+3; SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - NextCtx:=6; - elsif NextCtx=6 then + NextCtx:=7; + elsif NextCtx=7 then SysRam.O.we<='1'; SysRam.O.ena<='1'; @@ -829,7 +955,7 @@ SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - NextCtx:=7; - - elsif NextCtx=7 then --fin de la fonction + NextCtx:=NextCtx+1; + + elsif NextCtx=8 then --fin de la fonction SysRam.O.we<='0'; SysRam.O.ena<='0'; @@ -839,9 +965,9 @@ Interf.O.Instr_En<='1'; SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen)); - NextCtx:=8; - elsif NextCtx=8 then --acquittement de la copie des données dans le tampon + NextCtx:=NextCtx+1; + elsif NextCtx=9 then --acquittement de la copie des données dans le tampon if Interf.I.Instr_ack='1' then Interf.O.Instr_En<='0'; - NextCtx:=9; + NextCtx:=10; end if; SysRam.O.we<='0'; @@ -849,5 +975,5 @@ SysRam.O.enb<='1'; - elsif NextCtx=9 then --lecture de la fin de WComplete + elsif NextCtx=10 then --lecture de la fin de WComplete SysRam.O.we<='0'; SysRam.O.ena<='0'; @@ -860,9 +986,9 @@ elsif Interf.S.tmem(0)=0 then if interf.I.ramsel='0' then - NextCtx:=10; + NextCtx:=NextCtx+1; SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); end if; end if; - elsif NextCtx=10 then --test de la fin des transferts + elsif NextCtx=11 then --test de la fin des transferts if interf.I.ramsel='0' then SysRam.O.we<='0'; @@ -878,7 +1004,8 @@ end if; - elsif NextCtx=11 then + elsif NextCtx=12 then Interf.S.IntState1<=0; -- initialisation du compteur d'état Interf.S.IntState2<=0; + SysRam.O.enb<='0'; NextCtx:=0; --fin de la fonction end if; @@ -900,8 +1027,10 @@ end if; if NextCtx =0 then - NextCtx:=NextCtx+1; + if pgroup.grp=0 then --rien à faire nextCtx:=5; Interf.S.GPost<=(others=>'0'); + else + NextCtx:=NextCtx+1; end if; elsif NextCtx=1 then @@ -990,7 +1119,7 @@ SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); If Interf.S.Gpost=0 then - NextCtx:=9; --rien à synchroniser + NextCtx:=5; --rien à synchroniser end if; - elsif (NextCtx>=2) and (NextCtx <=7) then + elsif (NextCtx>=2) and (NextCtx <=3) then if interf.I.ramsel='0' then SysRam.O.we<='0'; @@ -1002,5 +1131,5 @@ NextCtx:=1; end if; - elsif NextCtx=8 then + elsif NextCtx=4 then if interf.I.ramsel='0' then SysRam.O.we<='0'; @@ -1008,5 +1137,5 @@ SysRam.O.enb<='1'; SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); - + if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0 --il faut un DSent=1 pour Put ou un DSending pour Get @@ -1019,8 +1148,10 @@ else NextCtx:=NextCtx; --on attend - end if; + end if; + else + NextCtx:=2; --retour à l'atente du Bit ! end if; - elsif NextCtx=9 then + elsif NextCtx=5 then SysRam.O.we<='0'; SysRam.O.ena<='0'; @@ -1157,18 +1288,56 @@ SysRam.O.ena<='0'; SysRam.O.enb<='1'; - elsif NextCtx=11 then --lecture de la fin de l'initialisation SysRam.O.we<='0'; SysRam.O.ena<='0'; SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=12 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; if interf.I.ramsel='0' then - SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); - if SysRam.I.Data_out(6)='1' then --spawned + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if SysRam.I.Data_out(5)='1' then --spawned NextCtx:=NextCtx+1; intercomm<=1; end if; Interf.O.membusy<='0'; - end if; - elsif NextCtx =12 then + else + NextCtx:=11; + end if; + elsif NextCtx=13 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx=14 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx =15 then Interf.O.Instr_En<='0'; Interf.O.membusy<='0'; @@ -1218,5 +1387,5 @@ Interf.S.IntState1<=wcount; - if wcount =4 then + if wcount =0 then NextCtx:=2; Interf.S.IntState1<=0; @@ -1432,4 +1601,90 @@ end procedure; +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is +--cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable tempdata:std_logic_vector(Word-1 downto 0); + + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + + SysRam.O.Addr_rd<=adrVect; + SysRam.O.Addr_Wr<=adrVect; + elsif dcount=1 then + if interf.I.ramsel='0' then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + end if; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=2 then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + Interf.O.membusy<='1'; + end if; + elsif dcount=4 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + if BitVal='1' then + TempData:=Tempdata or BitMask; + else + TempData:=TempData and not (BitMAsk); + end if; + SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=5 then --attente d'écriture + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + --SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + + end if; + + NextCtx:=dcount; +end procedure; @@ -1462,5 +1717,5 @@ end if; adresse:=Core_base_adr+2; - + AdrToSet:=AdrVect; if dcount=0 then SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); @@ -1468,17 +1723,24 @@ SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); elsif dcount=1 then - SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.We<='1';SysRam.O.Ena<='1'; dcount :=dcount+1; SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=2 then - SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); dcount :=dcount+1; SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); elsif dcount=3 then dcount :=dcount+1; + SysRam.O.We<='1';SysRam.O.Ena<='1'; SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM dcount:=0; + SysRam.O.We<='0';SysRam.O.Ena<='0'; SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); end if; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.ucf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.ucf (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.ucf (revision 74) @@ -2,4 +2,16 @@ #Created by Constraints Editor (xc6slx45-csg324-3) - 2012/12/19 NET "clkm" TNM_NET = clkm; -TIMESPEC TS_clkm = PERIOD "clkm" 10 ns HIGH 50%; +TIMESPEC TS_clkm = PERIOD "clkm" 15 ns HIGH 50%; PIN "reset_IBUF_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; +NET "reset" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET + +# onBoard Leds + NET "result<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0 + NET "result<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P, Sch name = LD1 + NET "result<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2 + NET "result<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P, Sch name = LD3 + NET "result<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4 + NET "result<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5 + NET "result<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6 + NET "result<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7 + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd (revision 74) @@ -70,6 +70,6 @@ end Component; - constant clk_period : time := 10 ns; - constant PROC : positive :=8; + constant clk_period : time := 15 ns; + constant PROC : positive :=4; -- synthesis translate_off --===================signaux pour l'horloge ============================== @@ -133,52 +133,52 @@ Core_Hold_Ack => MPI_Node_in(2).hold_ack ); -PE3: PE generic map (DestId=>2) -Port Map ( -Instruction => MPi_Node_in(3).Instruction, - Instruction_en => MPi_Node_in(3).Instruction_en, - Core_PushOut => MPi_Node_out(3).PushOut, - clk =>clkm, - reset =>reset, - CE => '1', - Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out, - Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in, - Core_RAM_WE => MPI_Node_out(3).ram_we, - Core_RAM_EN => MPI_Node_out(3).ram_en, - -- Core_RAM_ENB => MPI_Node_out(1).ram_en, - Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr, - Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd, - Core_Hold_req => MPI_Node_out(3).hold_req, - Core_Hold_Ack => MPI_Node_in(3).hold_ack -); - -PE4: PE Generic map (DestId=>3) - Port Map ( - Instruction => MPi_Node_in(4).Instruction, - Instruction_en => MPi_Node_in(4).Instruction_en, - Core_PushOut => MPi_Node_out(4).PushOut, - clk =>clkm, - reset =>reset, - CE => '1', - Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, - Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, - Core_RAM_WE => MPI_Node_out(4).ram_we, - Core_RAM_EN => MPI_Node_out(4).ram_en, - --Core_RAM_ENB => MPI_Node_out(2).ram_en, - Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, - Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, - Core_Hold_req => MPI_Node_out(4).hold_req, - Core_Hold_Ack => MPI_Node_in(4).hold_ack -); +--PE3: PE generic map (DestId=>2) +--Port Map ( +--Instruction => MPi_Node_in(3).Instruction, +-- Instruction_en => MPi_Node_in(3).Instruction_en, +-- Core_PushOut => MPi_Node_out(3).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(3).ram_we, +-- Core_RAM_EN => MPI_Node_out(3).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(3).hold_req, +-- Core_Hold_Ack => MPI_Node_in(3).hold_ack +--); +-- +--PE4: PE Generic map (DestId=>3) +-- Port Map ( +-- Instruction => MPi_Node_in(4).Instruction, +-- Instruction_en => MPi_Node_in(4).Instruction_en, +-- Core_PushOut => MPi_Node_out(4).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(4).ram_we, +-- Core_RAM_EN => MPI_Node_out(4).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(4).hold_req, +-- Core_Hold_Ack => MPI_Node_in(4).hold_ack +--); MPI_Node_in(1).reset<=reset; MPI_Node_in(1).clk<=clkm; MPI_Node_in(2).reset<=reset; MPI_Node_in(2).clk<=clkm; -MPI_Node_in(3).reset<=reset; -MPI_Node_in(3).clk<=clkm; -MPI_Node_in(4).reset<=reset; -MPI_Node_in(4).clk<=clkm; +--MPI_Node_in(3).reset<=reset; +--MPI_Node_in(3).clk<=clkm; +--MPI_Node_in(4).reset<=reset; +--MPI_Node_in(4).clk<=clkm; Result<=MPi_Node_out(1).PushOut; -PE_Dyn:for i in 5 to 6 generate -PE_i: PE Generic map (DestId=>i) +PE_Dyn:for i in 3 to 4 generate +PE_i: PE Generic map (DestId=>i-1) Port Map ( Instruction => MPi_Node_in(i).Instruction, Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest_summary.html (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest_summary.html (revision 74) @@ -3,5 +3,5 @@ - + @@ -14,9 +14,9 @@ - + - + @@ -47,5 +47,5 @@ - +
SWITCH_GEN Project Status (08/05/2013 - 19:22:45)
MultiMPITest Project Status (01/14/2014 - 19:51:11)
Project File:MultiMPITest Implementation State:Placed and Routed (Stopped)Synthesized
Target Device:xc6slx75-3csg484xc6slx45-3csg324
  • Errors:
  
  • Final Timing Score:
   
@@ -55,373 +55,9 @@  
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers5,73693,2966% 
    Number used as Flip Flops4,343   
    Number used as Latches1,393   
    Number used as Latch-thrus0   
    Number used as AND/OR logics0   
Number of Slice LUTs24,02146,64851% 
    Number used as logic13,76546,64829% 
        Number using O6 output only10,469   
        Number using O5 output only570   
        Number using O5 and O62,726   
        Number used as ROM0   
    Number used as Memory10,17611,07291% 
        Number used as Dual Port RAM10,144   
            Number using O6 output only10,144   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Single Port RAM32   
            Number using O6 output only32   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Shift Register0   
    Number used exclusively as route-thrus80   
        Number with same-slice register load6   
        Number with same-slice carry load66   
        Number with other load8   
Number of occupied Slices7,51511,66264% 
Number of LUT Flip Flop pairs used24,661   
    Number with an unused Flip Flop19,19824,66177% 
    Number with an unused LUT64024,6612% 
    Number of fully used LUT-FF pairs4,82324,66119% 
    Number of unique control sets1,854   
    Number of slice register sites lost
        to control set restrictions		7,68893,2968% 
Number of bonded IOBs103283% 
Number of RAMB16BWERs01720% 
Number of RAMB8BWERs43441% 
Number of BUFIO2/BUFIO2_2CLKs0320% 
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs1166% 
    Number used as BUFGs1   
    Number used as BUFGMUX0   
Number of DCM/DCM_CLKGENs0120% 
Number of ILOGIC2/ISERDES2s04420% 
Number of IODELAY2/IODRP2/IODRP2_MCBs04420% 
Number of OLOGIC2/OSERDES2s04420% 
Number of BSCANs040% 
Number of BUFHs03840% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s01320% 
Number of ICAPs010% 
Number of MCBs040% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs060% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets5.62   
- 
- - - - - - - - - - - - - - - - - -
Performance Summary [-]
Final Timing Score: Pinout Data:Pinout Report
Routing Results: - Clock Data:Clock Report
Timing Constraints:   
+ @@ -431,17 +67,17 @@ Report NameStatusGenerated ErrorsWarningsInfos -Synthesis ReportCurrentMon 5. Aug 19:05:19 201303217 Warnings (3094 new)383 Infos (383 new) -Translation ReportCurrentMon 5. Aug 19:05:51 20130323 Warnings (0 new)0 -Map ReportCurrentMon 5. Aug 19:21:47 201302114 Warnings (0 new)8 Infos (0 new) -Place and Route ReportCurrentMon 5. Aug 19:22:37 2013    +Synthesis ReportCurrentTue 14. Jan 19:05:30 2014    +Translation ReportCurrentTue 14. Jan 19:05:50 2014    +Map ReportCurrentTue 14. Jan 19:07:24 2014    +Place and Route ReportOut of DateMon 13. Jan 19:36:05 201401659 Warnings (0 new)0 +CPLD Fitter Report (Text)      Power Report      -Post-PAR Static Timing ReportOut of DateSat 3. Aug 11:21:28 2013002 Infos (0 new) -Bitgen ReportOut of DateWed 19. Dec 13:42:44 201201106 Warnings (565 new)0 +Post-PAR Static Timing ReportOut of DateMon 13. Jan 19:37:30 2014002 Infos (0 new) +Bitgen ReportOut of DateTue 14. Jan 07:39:01 2014000  
- - + @@ -449,4 +85,4 @@ -
Date Generated: 08/05/2013 - 19:22:46
+
Date Generated: 01/14/2014 - 20:09:39
Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd (revision 74) @@ -107,11 +107,13 @@ signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO signal Lib_Init : std_logic; -- l'initialisation est terminée - signal Lib_Enable : std_logic; + signal Lib_Enable : std_logic:='0'; + signal Ex1_run,Ex4_run : std_logic:='0'; --indique que ces modules sont en fin d'exécution signal Hold_Ack : std_logic; signal en_task : std_logic; + signal ht_reset :std_logic; --signaux pour la gestion de la MAE type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinStart, putdata,getdata,WinCompleted,finalize,st_timeout); type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); -signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal dcount : natural range 0 to 255:=0; signal count,count_i : natural range 0 to 15:=0; @@ -136,5 +138,5 @@ port map ( clk=>clk, - reset=>reset, + reset=>ht_reset, en=>en_task, Interf_i =>Libr.i, @@ -159,5 +161,5 @@ ram_we<= Core_ram_we; ram_din <= Core_ram_data_in; - pe_ram_do<=(others=>'0'); + pe_ram_do<=(others=>'U'); Core_ram_data_out<=ram_do; @@ -169,5 +171,5 @@ ram_we<= pe_ram_we; ram_din <=pe_ram_din; - Core_ram_data_out<=(others=>'0'); + Core_ram_data_out<=(others=>'U'); pe_ram_do<=ram_do; end case ; @@ -186,16 +188,27 @@ Lib_init<=Core_Pushout(4); -- Initialized Lib_Enable<=Core_Pushout(6);-- HT activée par la Librairie. - -horloge_ht:process (reset,ce,lib_enable,clk) +Ex1_Run<=Core_Pushout(5); -- fin de l'exécution de Ex1 +Ex4_Run<=Core_pushout(7); -- fin de l'exécution de Ex4 pour Spawn +horloge_ht:process (reset,en_task,clk) begin if reset='1' then clk_ht<='0'; +count<=0; +Ht_reset<='1'; else -if ce='1' then -clk_ht<=clk; -elsif lib_enable='1' then -clk_ht<=clk; +if en_task='1' then + clk_ht<=clk; + if count=10 then --circuit de reset pour la HT + ht_reset<='0'; + else + if rising_edge(clk) then + count<=count+1; + end if; + ht_reset<='1'; + end if; else -clk_ht<='0'; + count<=0; + clk_ht<='0'; + Ht_reset<='1'; end if; end if; @@ -205,5 +218,5 @@ clk=>clk , reset =>reset, -Ram_Busy=>Libr.O.membusy, +Ram_Busy=>Ram_busy, Hold_Ack=>Hold_Ack, Hold_req =>Core_Hold_Req, @@ -221,17 +234,31 @@ --==========MPI HCL signals ============================ -affect:process (clk,Core_hold_req,RamSel_i,Core_pushout,Libr) +affect:process (clk,en_task,Lib_enable,Core_hold_req,RamSel_i,Core_pushout,Libr.O) begin --if (clk'event and clk='1') then +if en_task='1' then Instruction<=Libr.O.Instruction; Ram_busy<=Libr.O.membusy; PE_Instr_EN<=Libr.O.instr_en; +else --si le HT n'est pas activé ces valeurs sont à 0 ! + Instruction<=(others=>'0'); + Ram_busy<='0'; + PE_Instr_EN<='0'; +end if; Libr.I.Instr_ack<=Core_pushout(0); Libr.I.InitOk<=Core_pushout(4); -Libr.I.Spawned<=Core_pushout(6); +if Lib_enable='1' then +Libr.I.Spawned<='1'; +else + Libr.I.Spawned<='0'; +end if; Libr.I.Hold_Req<=Core_Hold_req; --Libr.I.Hold_Ack<=Hold_Ack; Libr.I.RamSel<=RamSel_i; --end if; +assert Lib_enable/='1' +report "Spawn Activé" +severity WARNING ; + end process affect; --======================================================================= Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/_xmsgs/netgen.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/_xmsgs/netgen.xmsgs (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/_xmsgs/netgen.xmsgs (revision 74) @@ -6,5 +6,8 @@ users do not edit the contents of this file. --> -The generated VHDL netlist contains Xilinx UNISIM simulation primitives and has to be used with UNISIM library for correct compilation and simulation. +The -bd option used but no BMM information found in the design. + + +Error occured in update of design BRAMS. Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgc =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgc (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgc (revision 74) @@ -15,7 +15,7 @@ - xc5vlx50t - virtex5 - ff1136 + xc6slx75 + spartan6 + csg484 -3 Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgp =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgp (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/ipcore_dir/coregen.cgp (revision 74) @@ -1,7 +1,7 @@ SET designentry = VHDL SET BusFormat = BusFormatAngleBracketNotRipped -SET devicefamily = virtex5 -SET device = xc5vlx50t -SET package = ff1136 +SET devicefamily = spartan6 +SET device = xc6slx75 +SET package = csg484 SET speedgrade = -3 SET FlowVendor = Foundation_ISE Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 74) @@ -363,11 +363,11 @@ - MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) - - 26 + xc6slx75-3csg484 + + 1 0 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035b000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035b0000000100000000000000000000000100000000 false - MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) + xc6slx75-3csg484 @@ -376,5 +376,4 @@ Configure Target Device Implement Design/Map - Implement Design/Place & Route Implement Design/Place & Route/Back-annotate Pin Locations Implement Design/Place & Route/Generate IBIS Model @@ -383,11 +382,11 @@ - Implement Design - - 1 + View/Edit Routed Design (FPGA Editor) + + 17 0 000000ff0000000000000001000000010000000000000000000000000000000000000000000000014b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000 false - Implement Design + View/Edit Routed Design (FPGA Editor) @@ -396,11 +395,11 @@ - C:\Core MPI\CORE_MPI\SWITCH_GEN.ucf - - 51 + C:\Core MPI\CORE_MPI\EX4_FSM.vhd + + 12 0 000000ff00000000000000010000000000000002010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000 false - C:\Core MPI\CORE_MPI\SWITCH_GEN.ucf + C:\Core MPI\CORE_MPI\EX4_FSM.vhd @@ -413,5 +412,5 @@ 50 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000103000000010001000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000 + 000000ff0000000000000001000000000000000001000000000000000000000000000000000000014b000000010001000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000 false C:\Core MPI\CORE_MPI\MultiMPITest.vhd @@ -423,11 +422,11 @@ - - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000228000000010000000100000000000000000000000064ffffffff000000810000000000000001000002280000000100000000 - false - + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000 + false + @@ -540,5 +539,5 @@ mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd) - 9 + 8 0 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002f3000000020000000000000000000000000000000064ffffffff000000810000000000000002000002f30000000100000000000000000000000100000000 Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport (revision 73) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport (revision 74) @@ -2,15 +2,15 @@
- 2013-12-30T18:29:08 - SWITCH_GEN - 2013-12-21T12:27:20 + 2014-01-14T19:54:07 + CORE_MPI + 2014-01-14T19:51:12 C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport C:/Core MPI/CORE_MPI\ - 2013-06-15T13:06:16 + 2014-01-14T19:22:02 false
- + @@ -20,19 +20,19 @@ - + - @@ -47,5 +47,5 @@ @@ -63,5 +63,5 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + - +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSun 5. May 14:45:47 2013
Post-Map Static Timing ReportOut of DateWed 19. Dec 17:30:44 2012
ISIM Simulator LogOut of DateThu 8. Aug 16:31:11 2013
WebTalk ReportOut of DateFri 7. Jun 23:56:05 2013
WebTalk Log FileOut of DateFri 7. Jun 23:56:14 2013
Par Statistics
Total Non-vccgnd Signals=34585
Total Non-vccgnd Design Pins=196031
Total Non-vccgnd Conns=196031
Total Non-vccgnd Timing Constrained Conns=141800
Phase 1 CPU=35.8 sec
Phase 2 CPU=42.4 sec
Phase 3 CPU=263.0 sec
Phase 4 CPU=690.5 sec
Phase 5 CPU=1070.9 sec
Phase 6 CPU=1070.9 sec
Phase 7 CPU=1070.9 sec
Phase 8 CPU=1070.9 sec
Phase 9 CPU=1070.9 sec
Phase 10 CPU=1082.5 sec
AvgWirelenPerPin Fanout 1=5.0
Total Non-vccgnd Signals=41687
Total Non-vccgnd Design Pins=221079
Total Non-vccgnd Conns=221079
Total Non-vccgnd Timing Constrained Conns=170400
Phase 1 CPU=39.4 sec
Phase 2 CPU=47.0 sec
Phase 3 CPU=239.4 sec
Phase 4 CPU=456.1 sec
Phase 5 CPU=1042.1 sec
Phase 6 CPU=1042.1 sec
Phase 7 CPU=1042.1 sec
Phase 8 CPU=1042.1 sec
Phase 9 CPU=1042.1 sec
Phase 10 CPU=1054.7 sec
AvgWirelenPerPin Fanout 1=6.0
AvgWirelenPerPin Fanout 2=4.0
AvgWirelenPerPin Fanout 3=7.0
AvgWirelenPerPin Fanout 4=5.8
AvgWirelenPerPin Fanout 10=4.2
AvgWirelenPerPin Fanout 50=3.4
AvgWirelenPerPin Fanout 100=5.3
AvgWirelenPerPin Fanout 500=6.1
AvgWirelenPerPin Fanout 5000=4.4
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 3=8.0
AvgWirelenPerPin Fanout 4=6.0
AvgWirelenPerPin Fanout 10=4.4
AvgWirelenPerPin Fanout 50=3.1
AvgWirelenPerPin Fanout 100=5.9
AvgWirelenPerPin Fanout 500=3.3
AvgWirelenPerPin Fanout 5000=2.9
AvgWirelenPerPin Fanout 20000=12.8
AvgWirelenPerPin Fanout 50000=0.0
IRR Gamma=57.1819
IRR Gamma=154.5661