Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_DP.vhd
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_DP.vhd	(revision 74)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_DP.vhd	(revision 75)
@@ -41,5 +41,5 @@
 full : out std_logic --set as '1' when the queue is full
 );
-end fifo;
+end fifo_dp;
 
 architecture Behavioral of fifo_dp is
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd	(revision 74)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd	(revision 75)
@@ -109,5 +109,5 @@
 if rd_out_en='1' then
 	Et_out_fsm<=reading;
-elsif tlimit=350 then
+elsif tlimit=5000 then
 	Et_out_fsm<=dropping;
 	tlimit<=0;
@@ -131,4 +131,5 @@
 		sw<='0';
 		Et_out_fsm<=Idle;
+		report "Attention Paquet perdu !à Output_Port_Module";
 		n<=0;
 	end if;
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd	(revision 74)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd	(revision 75)
@@ -57,13 +57,14 @@
  signal n,n_i:natural range 0 to 7;
  signal wr_ok,rd_ok:std_logic:='0';
- signal sfifo_in,Data_to_send : std_logic_vector(Word-1 downto 0);
+ signal wr_ok_i,rd_ok_i:std_logic:='0';
+ signal sfifo_in,Data_to_send,Data_to_send_i  : std_logic_vector(Word-1 downto 0);
  signal spush : std_logic:='0';
  signal err : std_logic_vector(Word-1 downto 0):=(others =>'0');
 begin
 
-Fifo_copy_sync:process(clk)
+Fifo_copy_sync:process(clk,reset)
 
 begin
-if rising_edge(clk) then
+
 
   if reset='1' then
@@ -71,8 +72,13 @@
   Snd_state<=0;
   P_len<=0;
+  Data_to_send<=(others=>'0');
 else
+	if rising_edge(clk) then
   Snd_state<=Next_Snd_state;
   n<=n_i;	
   p_len<=P_len_i;
+  Data_to_send<=Data_to_send_i;
+  wr_ok<=wr_ok_i;
+  rd_ok<=rd_ok_i;
 end if;
 end if;
@@ -81,4 +87,7 @@
 	 Fifo_copy_val:process (Snd_state,Etsnd,copy_mode,data_to_send,rd_ok,wr_ok,spush)
 begin
+	--fifo_out_wr_en<='0';
+	--fifo_in_rd_en<='0';
+	--fifo_out_data_in<=data_to_send;
 	if copy_mode='0' then 
 	  fifo_out_wr_en<=wr_ok;
@@ -95,8 +104,11 @@
 	-- process qui envoie des données en provenance d'un Fifo vers un Fifo
 	FIfo_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,fifo_in_empty,
-	fifo_out_full,Fifo_in_data_out,p_len)
+	fifo_out_full,Fifo_in_data_out,p_len,n,mem,wr_ok,rd_ok)
 	variable onepop:std_logic:='0';
 	begin
 	  	  Next_snd_state<=snd_state; --valeur par defaut
+	  	  Data_To_Send_i<=Data_to_send;
+	  	  wr_ok_i<=wr_ok;
+	  	  rd_ok_i<=rd_ok;
 	  case snd_state is
 
@@ -106,52 +118,60 @@
 	                 n_i<=0;
 	             end if;
-	             wr_ok<='0';rd_ok<='0';onepop:='0';
+	             wr_ok_i<='0';rd_ok_i<='0';onepop:='0';
 	             snd_comp<='0';
-	  when 1=>         if P_len>0 then  
+	 when 1=>         --placer la première donnée sur le bus  
 										    if copy_mode='1' then 
-												if  fifo_in_empty='0' and onepop='0' then
-														data_to_send <=fifo_in_data_out ;
-														rd_Ok<='1';
-															onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
-															
+    												  if  fifo_in_empty='0'  then
+    														  data_to_send_i <=fifo_in_data_out ;		
+    												  end if;
 												else
-															rd_Ok<='0';
-												end if;
+												  data_to_send_i<=mem(n);
+												 end if;
+												 next_snd_state<=2;	
+	  when 2=>         if P_len>0 then  
+										    if copy_mode='1' then 
+    												  if  fifo_in_empty='0' and onepop='0' then
+    														  data_to_send_i <=fifo_in_data_out ;
+    														  rd_Ok_i<='1';
+    															onepop:='1'; --une donnée lue il faut arrêter de dépiler
+    															
+    												  else
+    															rd_Ok_i<='0';
+    												  end if;
 												else
-												  onepop:='1';
-												  data_to_send<=mem(n);
+												  onepop:='1';rd_ok_i<='0'; --pas besoin de signal de lecture ici
+												  data_to_send_i<=mem(n);
 												 end if;
 
-											  if (fifo_out_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:=not onepop;
-													wr_ok<='1';
-													p_len_i<=p_len-1;
-													n_i<=n+1;
-													
+											  if (fifo_out_full = '0') and onepop='1'   then	 							
+											  			wr_ok_i<='1';
+													 onepop:='0';
+													 p_len_i<=p_len-1;
+													 n_i<=n+1;													
 												else
-														wr_Ok<='0';
-													
+														wr_Ok_i<='0';													
 												end if;
 											else
-											 rd_ok<='0';wr_ok<='0';
-											 next_snd_state<=2;
+											 rd_ok_i<='0';
+											 wr_ok_i<='0';
+											 next_snd_state<=3;
 											 snd_comp<='1';
 											end if; 
-		when 2 =>  --fin de la copie
+		when 3 =>  --fin de la copie
 												if  snd_ack='1' then 
 												
-												    next_snd_state<=3;
+												    next_snd_state<=4;
 												end if;
-												wr_ok<='0';rd_ok<='0';
+												wr_ok_i<='0';rd_ok_i<='0';
 												snd_comp<='1';		
-														data_to_send <=(others=>'-');
-	when 3 =>next_snd_state<=0;
+														
+	when 4 =>next_snd_state<=0;
 	         snd_comp<='0';
 															
 when others => next_snd_state<=0;
                   snd_comp<='0';
-                  rd_ok<='0';
-                  wr_ok<='0';
-                  data_to_send <=(others=>'-');
+                  rd_ok_i<='0';
+                  wr_ok_i<='0';
+                  data_to_send_i <=(others=>'U');
   end case;
 	end process FIfo_to_fifo;