Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HCL_Arch_conf.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HCL_Arch_conf.vhd (revision 76) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HCL_Arch_conf.vhd (revision 76) @@ -0,0 +1,30 @@ +-- Package File Template +-- +-- Purpose: This package defines the size of NoC ports and the number +-- of hardware tasks to create with the Mpi HCL environment. +-- The NoC_size parameter may vary from 2 to 16 +-- The STATIC_HT parameter must be less or equal to the NoC_Size parameter +-- The DYN_ALLOWED authorize the binding of HT template environment to all the Noc Ports + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package Hcl_Arch_conf is + + + +-- Declare constants + + constant NOC_SIZE : integer :=4; --(2 to 16)indicates the number of NoC port to instantiate + constant STATIC_HT : integer := 2;--(2 to NOC_SIZE)gives the the number of HT to Hardwire + constant DYN_ALLOWED : std_logic:='1'; --allow the creation of dynamic hardware tasks +-- Declare functions and procedure + +end Hcl_Arch_conf; + + +package body Hcl_Arch_conf is + + + +end Hcl_Arch_conf; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_4.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_4.vhd (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_4.vhd (revision 76) @@ -144,5 +144,5 @@ --Dcount<=0; if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide - RunState<=Fillmem; + RunState<=InitApp; end if; --Ram_busy<='0'; @@ -185,5 +185,5 @@ if bfill=4 then - RunState<=InitApp; + RunState<=WinCreate; else RunState<=nextfill; @@ -212,8 +212,8 @@ when InitApp => --code pour Init - dlen:=15; + dlen:=1; if ct=0 then -- synthesis translate_off - write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + write (l,string'("Dlen;"& integer'image(dlen) & " ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); report l.all; @@ -251,7 +251,7 @@ if ct=0 then - RunState<=WinCreate; + RunState<=FillMem; -- synthesis translate_off - write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + write (l,string'("Dlen;" & integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -288,5 +288,5 @@ if ct=0 then -- synthesis translate_off - write (l,string'("Dlen; ;WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -303,5 +303,5 @@ end if; -- synthesis translate_off - write (l,string'("Dlen; ;WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -312,5 +312,5 @@ if ct=0 then -- synthesis translate_off - write (l,string'("Dlen; ;WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -326,5 +326,5 @@ RunState<=PutData; -- synthesis translate_off - write (l,string'("Dlen; ;WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_5.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_5.vhd (revision 76) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_5.vhd (revision 76) @@ -0,0 +1,493 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:04:21 04/22/2013 +-- Design Name: +-- Module Name: HT_process - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +library NocLib ; +use std.textio.all; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + + + +architecture A_Count of HT_process is + + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart, + putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout); + signal sram : typ_dpram; + signal MyGroup:mpi_group; + signal MyWin : mpi_win; + signal MyRank :std_logic_vector(3 downto 0); + signal intercomm,array_of_errcodes : natural; + signal ct_state:natural:=0; +signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque +signal RunState : typ_mae; +component count_32 is +port (clk,reset,upDn,load,start:in std_logic; +loadval :in std_logic_vector(31 downto 0); +outval : out std_logic_vector(31 downto 0)); +end component count_32; +signal rescount,updn,load,start :std_logic:='0'; +signal loadval,outval :std_logic_vector(31 downto 0):=(others=>'0'); + +begin + +--MAE du PE +--======================================================================= +-- Interf<=Libr; + + + pPutGet:process(clk,reset,en) + + constant DATAPTR : natural :=256; + variable nb_rma:natural range 0 to 15:=0; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen,dcount : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable mywin : Mpi_win; + variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn + variable comm : natural :=0; + variable Spawn_on: std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + + --======================================================= + --variables pour la création du fichier de résultats + -- synthesis translate_off + type char_file is file of character; + file f: text; + variable status :file_open_status ; + variable char_count: integer range 0 to 65536 := 0; + variable str: string (1 to 79) ; + variable L: line; + variable fopened: std_logic:='0'; + + constant simres : time :=1 ps; --simulation resolution + constant realres : real :=1.0e-3; --ramener le temps en ns + -- returns real value of time parameter using pure VHDL + function rt(t : time) return real is + begin + return real(t/simres) * realres; + end; + -- synthesis translate_on +--====================================================== + begin + --=== Partie combinatoire du process =================================== + + --=== Fin de la partie combinatoire du process ========================== + + + + --end loop; + + if (clk'event and clk='1') and en='1' then + + + if reset='1' then + RunState<=start; + + else + --========================================================== + --affectation des entrées sorties mémoires + sram.i.data_out<=mem_I.data_out; + mem_o.addr_wr<=sram.O.addr_wr; + mem_o.addr_rd<=sram.O.addr_rd ; + mem_o.we<=sram.O.we; + mem_o.ena<=sram.O.ena; + mem_o.enb<=sram.O.enb; + mem_o.data_in<=sram.O.data_in; + --affectation des entrées sorties MPI_HCL + Interf_o.Instr_EN<=Libr.O.instr_en; + Interf_o.Membusy<=Libr.O.MemBusy; + Interf_o.Instruction<=Libr.O.Instruction; + Libr.i.Instr_ack<=Interf_i.Instr_ack; + Libr.i.InitOk<=Interf_i.InitOk; + Libr.i.Hold_Req<=Interf_i.Hold_req; + Libr.I.Spawned<=Interf_i.Spawned; + --Libr.i.Hold_Ack<=Interf_i.Hold_Ack; + Libr.i.RamSel<=Interf_i.RamSel; + --ct_state<=ct; --pour débogage + --============================================================ + + case RunState is + when start => + --Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=InitApp; + end if; + --Ram_busy<='0'; + Libr.O.MemBusy<='0'; + Libr.O.Instr_En<='0'; + + adresse:=10;--DATAPTR; + + adresse_rd:=0; + timeout:=0; + --dcount<=0; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + -- synthesis translate_off + if fopened='0' then + file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE); + --while not endfile(c_file_handle) loop + --end if; + + --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); + --report l.all; + -- writeline (f, l) ; + fopened:='1'; + end if; + -- synthesis translate_on + when ReadData1 => + readmem(ct,libr,sram,x"0010",V); + if ct=0 then + reset_count<=v(0); + UpDn<=v(1); + Load<=v(2); + RunState<=ReadData2 + end if; + when readData2 => + readmem(ct,libr,sram,x"0011",loadval); + if ct=0 then + RunState<=WinCreate; + + end if; + + when InitApp => + --code pour Init + dlen:=1; + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & " ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Init(ct,Libr,Clk,SRam); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + + when GetRank => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + + if ct=0 then + RunState<=FillMem; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when Wincreate => --par défaut la fenêtre 0 est utilisée ! + case MyRank is + when x"0"=> + Mygroup.grp<=x"0002";-- rank 1 + MyGroup.nb<=2; + destRank:=1; + DestAdr:=X"043F"; + nb_rma:=1; + when x"1" => + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + DestAdr:=X"043F"; + when x"2" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"044F"; + when x"3" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"045F"; + when others => --cas des processus spawn + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + end case; + RunState<=WinPost; + when WinPost => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin); + + if ct=0 then + if spawn_on='1' then + RunState<=WinWait; + else + RunState<=WinStart; + end if; + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinStart => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=PutData; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when putdata => --construire le packet pour le Put + + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + --DestAdr:=X"033F"; + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=GetData; + -- synthesis translate_off + report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now)); + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when getdata => --positionnement du mot de longueur des données + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"006D"; + DestAdr:=X"1400"; + if unsigned(MyRank) = 0 then + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + else + + --pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win); + end if; + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + if unsigned(MyRank)/=0 then + RunState<=wincompleted; + else + nb_rma:=nb_rma+1; + if nb_rma=2 then + RunState<=wincompleted; + nb_rma:=0; + end if; + end if; + -- synthesis translate_off + assert ct/=0 report "GET_END " & integer'image(destrank) + severity Warning ; + write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinCompleted => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_Complete(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + RunState<=WinWait; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when WinWait => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_wait(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if Libr.I.Spawned='1' then + RunState<=Finalize; + elsif spawn_on='1' then + RunState<=Finalize; + else + RunState<=MpiSpawn; + end if; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + + when MpiSpawn => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + --(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + + maxprocs:=2; + pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if unsigned(MyRank)=0 then + Spawn_on:='1'; + Mygroup.grp<=x"000C";-- rank 3,4 + destRank:=0; + runstate<=WinPost; + else + RunState<=Finalize; + end if; + + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when finalize => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + if ct=0 then + RunState<=start; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + file_close(f); + -- synthesis translate_on + end if; + + when st_timeout => + + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + + RunState<=start; + end case; + ct_state<=ct; --pour débogage + end if; + end if; + + end process pPutGet; + +end a_count; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_process.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_process.vhd (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/HT_process.vhd (revision 76) @@ -144,5 +144,5 @@ --Dcount<=0; if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide - RunState<=Fillmem; + RunState<=InitApp; end if; --Ram_busy<='0'; @@ -185,5 +185,5 @@ if bfill=4 then - RunState<=InitApp; + RunState<=WinCreate; else RunState<=nextfill; @@ -212,5 +212,5 @@ when InitApp => --code pour Init - dlen:=15; + dlen:=10; if ct=0 then -- synthesis translate_off @@ -251,7 +251,7 @@ if ct=0 then - RunState<=WinCreate; + RunState<=Fillmem; -- synthesis translate_off - write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + write (l,string'("Dlen;"& integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -288,5 +288,5 @@ if ct=0 then -- synthesis translate_off - write (l,string'("Dlen; ;WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -299,5 +299,5 @@ RunState<=WinStart; -- synthesis translate_off - write (l,string'("Dlen; ;WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -308,5 +308,5 @@ if ct=0 then -- synthesis translate_off - write (l,string'("Dlen; ;WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; @@ -322,5 +322,5 @@ RunState<=PutData; -- synthesis translate_off - write (l,string'("Dlen; ;WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); report l.all; writeline (f, l) ; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/IP_Timer.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/IP_Timer.prj (revision 76) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/IP_Timer.prj (revision 76) @@ -0,0 +1,2 @@ +vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" +vhdl work "IP_Timer.vhd" Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/IP_Timer.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/IP_Timer.vhd (revision 76) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/IP_Timer.vhd (revision 76) @@ -0,0 +1,73 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:11:13 01/16/2014 +-- Design Name: +-- Module Name: IP_Timer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity IP_Timer is + +port (clk,reset,upDn,load,start:in std_logic; +loadval :in std_logic_vector(31 downto 0); +outval : out std_logic_vector(31 downto 0); +zero : out std_logic); + +end IP_Timer; + +architecture Behavioral of IP_Timer is +signal count: std_logic_vector(31 downto 0); +signal z:std_logic:='1'; +begin +process (clk) +begin + if clk='1' and clk'event then + if reset='1' then + count <= (others => '0'); + z<='1'; + elsif start='1' then + if load='1' then + count <= loadval; + else + if UpDn='1' then + count <= count + 1; + else + count <= count - 1; + end if; + end if; + if count=0 then + z<='1'; + else + z<='0'; + end if; + end if; + end if; +end process; +OutVal<=count; +zero<=z; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise (revision 76) @@ -103,6 +103,21 @@ + + + + + + + + + + + + + + + @@ -165,5 +180,7 @@ + + @@ -194,4 +211,5 @@ + @@ -306,9 +324,9 @@ - - - - - + + + + + @@ -355,6 +373,9 @@ + + + @@ -376,17 +397,17 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -433,6 +454,9 @@ + + + @@ -454,5 +478,5 @@ - + @@ -461,78 +485,13 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + - - - - - - - - - - - - - - - - Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.xise (revision 76) @@ -314,4 +314,16 @@ + + + + + + + + + + + + @@ -444,7 +456,7 @@ - - - + + + @@ -497,6 +509,6 @@ - - + + @@ -522,5 +534,5 @@ - + @@ -538,8 +550,8 @@ - - - - + + + + @@ -567,5 +579,5 @@ - + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.ucf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.ucf (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.ucf (revision 76) @@ -2,8 +2,8 @@ #Created by Constraints Editor (xc6slx45-csg324-3) - 2012/12/19 NET "clkm" TNM_NET = clkm; -TIMESPEC TS_clkm = PERIOD "clkm" 15 ns HIGH 50%; +TIMESPEC TS_clkm = PERIOD "clkm" 18 ns HIGH 50%; PIN "reset_IBUF_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; NET "reset" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET - +NET "clk" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK # onBoard Leds NET "result<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0 @@ -15,3 +15,3 @@ NET "result<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6 NET "result<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7 - +# Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd (revision 76) @@ -29,5 +29,5 @@ use NocLib.CoreTypes.all; use work.Packet_type.all; - +use work.Hcl_Arch_conf.all; USE ieee.numeric_std.ALL; @@ -90,5 +90,5 @@ BEGIN - Xbar: MPI_NOC GENERIC MAP (NPROC=>PROC) + Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE) PORT MAP ( MPI_Node_in => MPI_Node_in, @@ -96,41 +96,41 @@ ); -PE1: PE generic map (DestId=>0) -Port Map ( -Instruction => MPi_Node_in(1).Instruction, - Instruction_en => MPi_Node_in(1).Instruction_en, - Core_PushOut => MPi_Node_out(1).PushOut, - clk =>clkm, - reset =>reset, - CE => '1', - Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out, - Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in, - Core_RAM_WE => MPI_Node_out(1).ram_we, - Core_RAM_EN => MPI_Node_out(1).ram_en, - -- Core_RAM_ENB => MPI_Node_out(1).ram_en, - Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr, - Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd, - Core_Hold_req => MPI_Node_out(1).hold_req, - Core_Hold_Ack => MPI_Node_in(1).hold_ack -); - -PE2: PE Generic map (DestId=>1) - Port Map ( - Instruction => MPi_Node_in(2).Instruction, - Instruction_en => MPi_Node_in(2).Instruction_en, - Core_PushOut => MPi_Node_out(2).PushOut, - clk =>clkm, - reset =>reset, - CE => '1', - Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out, - Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in, - Core_RAM_WE => MPI_Node_out(2).ram_we, - Core_RAM_EN => MPI_Node_out(2).ram_en, - --Core_RAM_ENB => MPI_Node_out(2).ram_en, - Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr, - Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd, - Core_Hold_req => MPI_Node_out(2).hold_req, - Core_Hold_Ack => MPI_Node_in(2).hold_ack -); +--PE1: PE generic map (DestId=>0) +--Port Map ( +--Instruction => MPi_Node_in(1).Instruction, +-- Instruction_en => MPi_Node_in(1).Instruction_en, +-- Core_PushOut => MPi_Node_out(1).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(1).ram_we, +-- Core_RAM_EN => MPI_Node_out(1).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(1).hold_req, +-- Core_Hold_Ack => MPI_Node_in(1).hold_ack +--); +-- +--PE2: PE Generic map (DestId=>1) +-- Port Map ( +-- Instruction => MPi_Node_in(2).Instruction, +-- Instruction_en => MPi_Node_in(2).Instruction_en, +-- Core_PushOut => MPi_Node_out(2).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(2).ram_we, +-- Core_RAM_EN => MPI_Node_out(2).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(2).hold_req, +-- Core_Hold_Ack => MPI_Node_in(2).hold_ack +--); --PE3: PE generic map (DestId=>2) --Port Map ( @@ -170,8 +170,8 @@ -- Core_Hold_Ack => MPI_Node_in(4).hold_ack --); -MPI_Node_in(1).reset<=reset; -MPI_Node_in(1).clk<=clkm; -MPI_Node_in(2).reset<=reset; -MPI_Node_in(2).clk<=clkm; +--MPI_Node_in(1).reset<=reset; +--MPI_Node_in(1).clk<=clkm; +--MPI_Node_in(2).reset<=reset; +--MPI_Node_in(2).clk<=clkm; --MPI_Node_in(3).reset<=reset; --MPI_Node_in(3).clk<=clkm; @@ -179,6 +179,29 @@ --MPI_Node_in(4).clk<=clkm; Result<=MPi_Node_out(1).PushOut; -PE_Dyn:for i in 3 to 4 generate -PE_i: PE Generic map (DestId=>i-1) +PE_s:for i in 1 to STATIC_HT generate +S: PE Generic map (DestId=>i-1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '1', + Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, + Core_RAM_WE => MPI_Node_out(i).ram_we, + Core_RAM_EN => MPI_Node_out(i).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, + Core_Hold_req => MPI_Node_out(i).hold_req, + Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate PE_s; +dyn_HT: if dyn_allowed='1' generate +PE_D:for i in STATIC_HT+1 to NOC_SIZE generate +D: PE Generic map (DestId=>i-1) Port Map ( Instruction => MPi_Node_in(i).Instruction, @@ -200,4 +223,5 @@ MPI_Node_in(i).reset<=reset; MPI_Node_in(i).clk<=clkm; -end generate PE_Dyn; +end generate PE_D; +end generate dyn_HT; END; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest_summary.html (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest_summary.html (revision 76) @@ -3,5 +3,5 @@ - + @@ -14,5 +14,5 @@ - + @@ -67,9 +67,8 @@ - - - + + + - @@ -80,4 +79,6 @@ + + @@ -85,4 +86,4 @@ -
Date Generated: 01/14/2014 - 20:09:39
+
Date Generated: 01/16/2014 - 19:06:43
Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd (revision 76) @@ -78,4 +78,5 @@ ); end COMPONENT HT_process; + COMPONENT Hold_FSM is @@ -144,5 +145,5 @@ mem_i =>sram.i, mem_o =>sram.o ); - + --================================================================ --MUX de la RAM Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/SWITCH_GEN.ucf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/SWITCH_GEN.ucf (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/SWITCH_GEN.ucf (revision 76) @@ -2,3 +2,3 @@ #Created by Constraints Editor (xc6slx45-csg324-3) - 2013/01/04 NET "clk" TNM_NET = clk; -TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50%; +TIMESPEC TS_clk = PERIOD "clk" 18 ns HIGH 50%; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/SetBit.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/SetBit.vhd (revision 76) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/SetBit.vhd (revision 76) @@ -0,0 +1,166 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:30:11 08/01/2013 +-- Design Name: +-- Module Name: SetBit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +--use work.packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SetBit is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + BitMask : in std_logic_vector(Word-1 downto 0); + BitVal : in std_logic; + whole : in std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + start : in std_logic; + done : out std_logic; + ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0)); +end SetBit; + +architecture Behavioral of SetBit is +signal n,State,Next_State:natural range 0 to 15 :=0; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +begin +PSetBit_sync:process(clk,reset) + +begin +if rising_edge(clk) then +if reset='1' then + n<=0; + State<=0; +else + State<=Next_State; +end if; +end if; +end process; + +PSetBit:process (State,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out) + variable tempval : std_logic_vector(Word-1 downto 0); + begin + Next_State<=State; + + +if State >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; +case State is +when 0 => + rd_ok<='0'; + Wr_ok<='0'; + done<='0'; + if start='1' and whole='1' then + Next_State<=5; + wr_ok<='1'; + ram_data_in<=bitmask; + elsif start='1' then + Next_State<=State+1; + end if; + +when 1=> if dma_rd_grant='1' then + Next_State<=State+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 2|3=> + if dma_rd_grant='1' then --cycle d'attente + Next_State<=State+1; + else + Next_State<=1; --recommencer l'attente si perte de priorité + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 4 => + if dma_rd_grant='1' and dma_wr_grant='1' then + Next_State<=6; + tempval:=Ram_data_out; + if bitval='1' then + tempval:= tempval or BitMask; + else + tempval:= tempval and not (BitMask); + end if; + if whole='1' then + ram_data_in<=bitmask; + else + ram_data_in<=tempval; + end if; + rd_ok<='1'; + wr_ok<='1'; + else + Next_State<=State; + report "SetBit:Impossible d'avoir accès en R/W à la RAM"; + end if; + When 5 => + if dma_wr_grant='1' then + if whole='1' then + ram_data_in<=bitmask; + else + ram_data_in<=tempval; + end if; + Next_State<=6; + end if; + wr_ok<='1'; + When 6=> + done<='1'; + if start='0' then + Next_State<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + wr_ok<='1'; + When others => + Next_State<=0; + rd_ok<='0'; + wr_ok<='0'; + done<='0'; +end case; + +end process PSetBit; +dma_rd_request <= dma_rd; +dma_wr_request <=dma_wr; +Ram_wr<=wr_ok; +Ram_rd<=rd_ok; +--Ram_data_out<=data_to_ram; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 76) @@ -17,4 +17,6 @@ /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_CORE_EX2_FSM - EX2_FSM - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/sw_gen1 - SWITCH_GEN - Behavioral/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description/MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description @@ -187,4 +189,6 @@ /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE3 - PE - Behavioral/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_PKG + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/sw_gen1 - SWITCH_GEN - Behavioral/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description @@ -243,4 +247,5 @@ /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/conversions/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd + /Unassigned User Library Modules/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral @@ -378,15 +383,13 @@ Implement Design/Place & Route/Back-annotate Pin LocationsImplement Design/Place & Route/Generate IBIS Model - Implement Design/Place & Route/Generate Post-Place & Route Static Timing - User Constraints - - - View/Edit Routed Design (FPGA Editor) - - 17 + + + Synthesize - XST + + 20000000ff0000000000000001000000010000000000000000000000000000000000000000000000014b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000false - View/Edit Routed Design (FPGA Editor) + Synthesize - XST @@ -395,11 +398,11 @@ - C:\Core MPI\CORE_MPI\EX4_FSM.vhd - - 12 + C:\Core MPI\CORE_MPI\MultiMPITest.ucf + + 52 0 000000ff00000000000000010000000000000002010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000 false - C:\Core MPI\CORE_MPI\EX4_FSM.vhd + C:\Core MPI\CORE_MPI\MultiMPITest.ucf @@ -412,5 +415,5 @@ 50 0 - 000000ff0000000000000001000000000000000001000000000000000000000000000000000000014b000000010001000100000000000000000000000064ffffffff0000008100000000000000010000014b0000000100000000 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000103000000010001000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000 false C:\Core MPI\CORE_MPI\MultiMPITest.vhd @@ -419,8 +422,8 @@ 1 - Design Utilities - - - + Design Utilities/Compile HDL Simulation Libraries + + + Design Utilities 0 @@ -428,5 +431,5 @@ 000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000 false - + Design Utilities @@ -442,8 +445,8 @@ /FIFO - TOP_HIER C:|Core MPI|CORE_MPI|FIfo_mem.vhd /Image_Pkg C:|Core MPI|CORE_MPI|image_pkg.vhd - /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/MPI_CORE_EX2_FSM - EX2_FSM - Behavioral /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral /MPI_NOC - structural C:|Core MPI|CORE_MPI|MPI_NOC.vhd @@ -537,11 +540,11 @@ - mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd) - - 8 - 0 - 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002f3000000020000000000000000000000000000000064ffffffff000000810000000000000002000002f30000000100000000000000000000000100000000 - false - mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd) + Unassigned User Library Modules + + 2 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035b000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035b0000000100000000000000000000000100000000 + false + Unassigned User Library Modules @@ -551,5 +554,5 @@ - + Update All Schematic Files 0 @@ -557,5 +560,5 @@ 000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000 false - + Update All Schematic Files @@ -564,5 +567,5 @@ - ModelSim Simulator + 0 @@ -570,8 +573,8 @@ 000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000 false - ModelSim Simulator + 000000ff0000000000000002000000d1000000d101000000050100000002 - Behavioral Simulation + Implementation @@ -762,10 +765,38 @@ 1 - - 0 - 0 - - false - + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000 + false + + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000 + false + + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000 + false + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport (revision 75) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport (revision 76) @@ -2,15 +2,15 @@
- 2014-01-14T19:54:07 - CORE_MPI - 2014-01-14T19:51:12 + 2014-01-15T10:32:39 + MultiMPITest + 2014-01-15T10:32:39 C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport C:/Core MPI/CORE_MPI\ - 2014-01-14T19:22:02 + 2014-01-15T10:26:54 false
- + @@ -25,14 +25,14 @@ - @@ -47,5 +47,5 @@ @@ -63,5 +63,5 @@ -
MultiMPITest Project Status (01/14/2014 - 19:51:11)
FIFO Project Status (01/16/2014 - 15:56:56)
Project File:MultiMPITest Implementation State:SynthesizedMapped
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue 14. Jan 19:05:30 2014   
Translation ReportCurrentTue 14. Jan 19:05:50 2014   
Map ReportCurrentTue 14. Jan 19:07:24 2014   
Synthesis ReportCurrentWed 15. Jan 15:00:16 2014   
Translation ReportCurrentWed 15. Jan 15:06:05 2014036 Warnings (0 new)0
Map ReportCurrentWed 15. Jan 15:07:45 2014X 3 Errors (2 new)08 Infos (3 new)
Place and Route ReportOut of DateMon 13. Jan 19:36:05 201401659 Warnings (0 new)0
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportOut of DateMon 13. Jan 19:37:30 2014002 Infos (0 new)
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu 8. Aug 16:31:11 2013
Post-Map Static Timing ReportOut of DateWed 19. Dec 17:30:44 2012
Post-Place and Route Simulation Model ReportOut of DateTue 14. Jan 07:44:23 2014
WebTalk ReportOut of DateFri 7. Jun 23:56:05 2013
WebTalk Log FileOut of DateFri 7. Jun 23:56:14 2013