Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd
===================================================================
--- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd	(revision 74)
+++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MultiMPITest.vhd	(revision 76)
@@ -29,5 +29,5 @@
 use NocLib.CoreTypes.all;
 use work.Packet_type.all;
-
+use work.Hcl_Arch_conf.all;
 USE ieee.numeric_std.ALL;
  
@@ -90,5 +90,5 @@
  
 BEGIN
- Xbar: MPI_NOC GENERIC MAP (NPROC=>PROC)
+ Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE)
 		PORT MAP (
           MPI_Node_in => MPI_Node_in,
@@ -96,41 +96,41 @@
         );
 
-PE1: PE generic map (DestId=>0)
-Port Map (
-Instruction => MPi_Node_in(1).Instruction,
-           Instruction_en => MPi_Node_in(1).Instruction_en,
-			  Core_PushOut => MPi_Node_out(1).PushOut,
-           clk =>clkm,
-           reset =>reset,
-			  CE => '1',
-           Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out,
-           Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in,
-           Core_RAM_WE => MPI_Node_out(1).ram_we,
-           Core_RAM_EN => MPI_Node_out(1).ram_en,
-          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
-           Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr,
-           Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd,
-           Core_Hold_req => MPI_Node_out(1).hold_req,
-           Core_Hold_Ack => MPI_Node_in(1).hold_ack
-);
-
-PE2: PE 	Generic map (DestId=>1)
-			Port Map (
-				Instruction => MPi_Node_in(2).Instruction,
-           Instruction_en => MPi_Node_in(2).Instruction_en,
-			  Core_PushOut => MPi_Node_out(2).PushOut,
-           clk =>clkm,
-           reset =>reset,
-			  CE => '1',
-           Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out,
-           Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in,
-           Core_RAM_WE => MPI_Node_out(2).ram_we,
-           Core_RAM_EN => MPI_Node_out(2).ram_en,
-           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
-           Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr,
-           Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd,
-           Core_Hold_req => MPI_Node_out(2).hold_req,
-           Core_Hold_Ack => MPI_Node_in(2).hold_ack
-);
+--PE1: PE generic map (DestId=>0)
+--Port Map (
+--Instruction => MPi_Node_in(1).Instruction,
+--           Instruction_en => MPi_Node_in(1).Instruction_en,
+--			  Core_PushOut => MPi_Node_out(1).PushOut,
+--           clk =>clkm,
+--           reset =>reset,
+--			  CE => '1',
+--           Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out,
+--           Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in,
+--           Core_RAM_WE => MPI_Node_out(1).ram_we,
+--           Core_RAM_EN => MPI_Node_out(1).ram_en,
+--          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
+--           Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr,
+--           Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd,
+--           Core_Hold_req => MPI_Node_out(1).hold_req,
+--           Core_Hold_Ack => MPI_Node_in(1).hold_ack
+--);
+--
+--PE2: PE 	Generic map (DestId=>1)
+--			Port Map (
+--				Instruction => MPi_Node_in(2).Instruction,
+--           Instruction_en => MPi_Node_in(2).Instruction_en,
+--			  Core_PushOut => MPi_Node_out(2).PushOut,
+--           clk =>clkm,
+--           reset =>reset,
+--			  CE => '1',
+--           Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out,
+--           Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in,
+--           Core_RAM_WE => MPI_Node_out(2).ram_we,
+--           Core_RAM_EN => MPI_Node_out(2).ram_en,
+--           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
+--           Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr,
+--           Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd,
+--           Core_Hold_req => MPI_Node_out(2).hold_req,
+--           Core_Hold_Ack => MPI_Node_in(2).hold_ack
+--);
 --PE3: PE generic map (DestId=>2)
 --Port Map (
@@ -170,8 +170,8 @@
 --           Core_Hold_Ack => MPI_Node_in(4).hold_ack
 --);
-MPI_Node_in(1).reset<=reset;	
-MPI_Node_in(1).clk<=clkm;
-MPI_Node_in(2).reset<=reset;	
-MPI_Node_in(2).clk<=clkm;
+--MPI_Node_in(1).reset<=reset;	
+--MPI_Node_in(1).clk<=clkm;
+--MPI_Node_in(2).reset<=reset;	
+--MPI_Node_in(2).clk<=clkm;
 --MPI_Node_in(3).reset<=reset;	
 --MPI_Node_in(3).clk<=clkm;
@@ -179,6 +179,29 @@
 --MPI_Node_in(4).clk<=clkm;
 Result<=MPi_Node_out(1).PushOut;
-PE_Dyn:for i in 3 to 4 generate
-PE_i: PE 	Generic map (DestId=>i-1)
+PE_s:for i in 1 to STATIC_HT generate
+S: PE 	Generic map (DestId=>i-1)
+			Port Map (
+				Instruction => MPi_Node_in(i).Instruction,
+           Instruction_en => MPi_Node_in(i).Instruction_en,
+			  Core_PushOut => MPi_Node_out(i).PushOut,
+           clk =>clkm,
+           reset =>reset,
+			  CE => '1',
+           Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out,
+           Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in,
+           Core_RAM_WE => MPI_Node_out(i).ram_we,
+           Core_RAM_EN => MPI_Node_out(i).ram_en,
+           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
+           Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr,
+           Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd,
+           Core_Hold_req => MPI_Node_out(i).hold_req,
+           Core_Hold_Ack => MPI_Node_in(i).hold_ack
+);
+MPI_Node_in(i).reset<=reset;	
+MPI_Node_in(i).clk<=clkm;
+end generate PE_s;
+dyn_HT: if dyn_allowed='1' generate
+PE_D:for i in STATIC_HT+1 to NOC_SIZE generate
+D: PE 	Generic map (DestId=>i-1)
 			Port Map (
 				Instruction => MPi_Node_in(i).Instruction,
@@ -200,4 +223,5 @@
 MPI_Node_in(i).reset<=reset;	
 MPI_Node_in(i).clk<=clkm;
-end generate PE_Dyn;
+end generate PE_D;
+end generate dyn_HT;
 END;
