Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec.v =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec.v (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec.v (revision 83) @@ -0,0 +1,43 @@ +// audio_codec.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module audio_codec #( + parameter AUTO_CLOCK_CLOCK_RATE = "-1" + ) ( + input wire clk, // clock.clk + input wire reset, // reset.reset + input wire [31:0] asi_raw_audio_data, // raw_audio.data + output wire asi_raw_audio_ready, // .ready + input wire asi_raw_audio_valid, // .valid + input wire [7:0] avs_ctrl_address, // ctrl.address + input wire avs_ctrl_read, // .read + output wire [31:0] avs_ctrl_readdata, // .readdata + input wire avs_ctrl_write, // .write + input wire [31:0] avs_ctrl_writedata, // .writedata + output wire avs_ctrl_waitrequest, // .waitrequest + output wire [31:0] aso_comp_audio_data, // comp_audio.data + input wire aso_comp_audio_ready, // .ready + output wire aso_comp_audio_valid // .valid + ); + + // TODO: Auto-generated HDL template + + assign asi_raw_audio_ready = 1'b0; + + assign avs_ctrl_waitrequest = 1'b0; + + assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; + + assign aso_comp_audio_valid = 1'b0; + + assign aso_comp_audio_data = 32'b00000000000000000000000000000000; + +endmodule Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec_hw.tcl =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec_hw.tcl (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec_hw.tcl (revision 83) @@ -0,0 +1,163 @@ +# TCL File Generated by Component Editor 13.1 +# Fri Feb 28 16:58:45 CET 2014 +# DO NOT MODIFY + + +# +# audio_codec "audio_codec" v1.0 +# 2014.02.28.16:58:45 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module audio_codec +# +set_module_property DESCRIPTION "" +set_module_property NAME audio_codec +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP smartEEG +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME audio_codec +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL audio_codec +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file audio_codec.v VERILOG PATH audio_codec.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl avs_ctrl_address address Input 8 +add_interface_port ctrl avs_ctrl_read read Input 1 +add_interface_port ctrl avs_ctrl_readdata readdata Output 32 +add_interface_port ctrl avs_ctrl_write write Input 1 +add_interface_port ctrl avs_ctrl_writedata writedata Input 32 +add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point raw_audio +# +add_interface raw_audio avalon_streaming end +set_interface_property raw_audio associatedClock clock +set_interface_property raw_audio associatedReset reset +set_interface_property raw_audio dataBitsPerSymbol 8 +set_interface_property raw_audio errorDescriptor "" +set_interface_property raw_audio firstSymbolInHighOrderBits true +set_interface_property raw_audio maxChannel 0 +set_interface_property raw_audio readyLatency 0 +set_interface_property raw_audio ENABLED true +set_interface_property raw_audio EXPORT_OF "" +set_interface_property raw_audio PORT_NAME_MAP "" +set_interface_property raw_audio CMSIS_SVD_VARIABLES "" +set_interface_property raw_audio SVD_ADDRESS_GROUP "" + +add_interface_port raw_audio asi_raw_audio_data data Input 32 +add_interface_port raw_audio asi_raw_audio_ready ready Output 1 +add_interface_port raw_audio asi_raw_audio_valid valid Input 1 + + +# +# connection point comp_audio +# +add_interface comp_audio avalon_streaming start +set_interface_property comp_audio associatedClock clock +set_interface_property comp_audio associatedReset reset +set_interface_property comp_audio dataBitsPerSymbol 8 +set_interface_property comp_audio errorDescriptor "" +set_interface_property comp_audio firstSymbolInHighOrderBits true +set_interface_property comp_audio maxChannel 0 +set_interface_property comp_audio readyLatency 0 +set_interface_property comp_audio ENABLED true +set_interface_property comp_audio EXPORT_OF "" +set_interface_property comp_audio PORT_NAME_MAP "" +set_interface_property comp_audio CMSIS_SVD_VARIABLES "" +set_interface_property comp_audio SVD_ADDRESS_GROUP "" + +add_interface_port comp_audio aso_comp_audio_data data Output 32 +add_interface_port comp_audio aso_comp_audio_ready ready Input 1 +add_interface_port comp_audio aso_comp_audio_valid valid Output 1 + Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec.v =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec.v (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec.v (revision 83) @@ -0,0 +1,46 @@ +// exg_codec.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module exg_codec #( + parameter AUTO_CLOCK_CLOCK_RATE = "-1" + ) ( + input wire clk, // clock.clk + input wire reset, // reset.reset + input wire [31:0] asi_raw_exg_data, // raw_exg.data + output wire asi_raw_exg_ready, // .ready + input wire asi_raw_exg_valid, // .valid + input wire [7:0] avs_ctrl_address, // ctrl.address + input wire avs_ctrl_read, // .read + output wire [31:0] avs_ctrl_readdata, // .readdata + input wire avs_ctrl_write, // .write + input wire [31:0] avs_ctrl_writedata, // .writedata + output wire avs_ctrl_waitrequest, // .waitrequest + output wire [31:0] aso_raw_exg_data, // raw_exg.data + input wire aso_raw_exg_ready, // .ready + output wire aso_raw_exg_valid, // .valid + output wire [31:0] aso_comp_exg_data, // comp_exg.data + input wire aso_comp_exg_ready, // .ready + output wire aso_comp_exg_valid // .valid + ); + + // TODO: Auto-generated HDL template + + assign asi_raw_exg_ready = 1'b0; + + assign avs_ctrl_waitrequest = 1'b0; + + assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; + + assign aso_comp_exg_valid = 1'b0; + + assign aso_comp_exg_data = 32'b00000000000000000000000000000000; + +endmodule Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber.v =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber.v (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber.v (revision 83) @@ -0,0 +1,47 @@ +// frame_grabber.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module frame_grabber ( + input wire clk, // clock.clk + input wire reset, // reset.reset + input wire [7:0] avs_s0_address, // ctrl.address + input wire avs_s0_read, // .read + output wire [31:0] avs_s0_readdata, // .readdata + input wire avs_s0_write, // .write + input wire [31:0] avs_s0_writedata, // .writedata + output wire avs_s0_waitrequest, // .waitrequest + output wire [31:0] aso_out0_data, // raw_video.data + input wire aso_out0_ready, // .ready + output wire aso_out0_valid, // .valid + + input [11:0] D5M_D, + output D5M_RESETn, + input D5M_FVAL, + input D5M_LVAL, + input D5M_PIXLCLK, + output D5M_SCLK, + inout D5M_SDATA, + input D5M_STROBE, + output D5M_TRIGGER, + output D5M_XCLKIN + ); + + // TODO: Auto-generated HDL template + + assign avs_s0_waitrequest = 1'b0; + + assign avs_s0_readdata = 32'b00000000000000000000000000000000; + + assign aso_out0_valid = 1'b0; + + assign aso_out0_data = 32'b00000000000000000000000000000000; + +endmodule Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber_hw.tcl =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber_hw.tcl (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber_hw.tcl (revision 83) @@ -0,0 +1,165 @@ +# TCL File Generated by Component Editor 13.1 +# Fri Feb 28 17:27:39 CET 2014 +# DO NOT MODIFY + + +# +# frame_grabber "frame_grabber" v1.0 +# 2014.02.28.17:27:39 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module frame_grabber +# +set_module_property DESCRIPTION "" +set_module_property NAME frame_grabber +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP smartEEG +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME frame_grabber +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL frame_grabber +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl avs_s0_address address Input 8 +add_interface_port ctrl avs_s0_read read Input 1 +add_interface_port ctrl avs_s0_readdata readdata Output 32 +add_interface_port ctrl avs_s0_write write Input 1 +add_interface_port ctrl avs_s0_writedata writedata Input 32 +add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point raw_video +# +add_interface raw_video avalon_streaming start +set_interface_property raw_video associatedClock clock +set_interface_property raw_video associatedReset reset +set_interface_property raw_video dataBitsPerSymbol 8 +set_interface_property raw_video errorDescriptor "" +set_interface_property raw_video firstSymbolInHighOrderBits true +set_interface_property raw_video maxChannel 0 +set_interface_property raw_video readyLatency 0 +set_interface_property raw_video ENABLED true +set_interface_property raw_video EXPORT_OF "" +set_interface_property raw_video PORT_NAME_MAP "" +set_interface_property raw_video CMSIS_SVD_VARIABLES "" +set_interface_property raw_video SVD_ADDRESS_GROUP "" + +add_interface_port raw_video aso_out0_data data Output 32 +add_interface_port raw_video aso_out0_ready ready Input 1 +add_interface_port raw_video aso_out0_valid valid Output 1 + + +# +# connection point conduit_camera +# +add_interface conduit_camera conduit end +set_interface_property conduit_camera associatedClock clock +set_interface_property conduit_camera associatedReset "" +set_interface_property conduit_camera ENABLED true +set_interface_property conduit_camera EXPORT_OF "" +set_interface_property conduit_camera PORT_NAME_MAP "" +set_interface_property conduit_camera CMSIS_SVD_VARIABLES "" +set_interface_property conduit_camera SVD_ADDRESS_GROUP "" + +add_interface_port conduit_camera D5M_D export Input 12 +add_interface_port conduit_camera D5M_RESETn export Output 1 +add_interface_port conduit_camera D5M_FVAL export Input 1 +add_interface_port conduit_camera D5M_LVAL export Input 1 +add_interface_port conduit_camera D5M_PIXLCLK export Input 1 +add_interface_port conduit_camera D5M_SCLK export Output 1 +add_interface_port conduit_camera D5M_SDATA export Bidir 1 +add_interface_port conduit_camera D5M_STROBE export Input 1 +add_interface_port conduit_camera D5M_TRIGGER export Output 1 +add_interface_port conduit_camera D5M_XCLKIN export Output 1 + Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/new_component_hw.tcl =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/new_component_hw.tcl (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/new_component_hw.tcl (revision 83) @@ -0,0 +1,191 @@ +# TCL File Generated by Component Editor 13.1 +# Fri Feb 28 17:02:33 CET 2014 +# DO NOT MODIFY + + +# +# exg_codec "exg_codec" v1.0 +# 2014.02.28.17:02:33 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module exg_codec +# +set_module_property DESCRIPTION "" +set_module_property NAME exg_codec +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP smartEEG +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME exg_codec +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL exg_codec +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file exg_codec.v VERILOG PATH exg_codec.v TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter AUTO_CLOCK_CLOCK_RATE STRING -1 +set_parameter_property AUTO_CLOCK_CLOCK_RATE DEFAULT_VALUE -1 +set_parameter_property AUTO_CLOCK_CLOCK_RATE DISPLAY_NAME AUTO_CLOCK_CLOCK_RATE +set_parameter_property AUTO_CLOCK_CLOCK_RATE TYPE STRING +set_parameter_property AUTO_CLOCK_CLOCK_RATE UNITS None +set_parameter_property AUTO_CLOCK_CLOCK_RATE HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl avs_ctrl_address address Input 8 +add_interface_port ctrl avs_ctrl_read read Input 1 +add_interface_port ctrl avs_ctrl_readdata readdata Output 32 +add_interface_port ctrl avs_ctrl_write write Input 1 +add_interface_port ctrl avs_ctrl_writedata writedata Input 32 +add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point raw_exg +# +add_interface raw_exg avalon_streaming end +set_interface_property raw_exg associatedClock clock +set_interface_property raw_exg associatedReset reset +set_interface_property raw_exg dataBitsPerSymbol 8 +set_interface_property raw_exg errorDescriptor "" +set_interface_property raw_exg firstSymbolInHighOrderBits true +set_interface_property raw_exg maxChannel 0 +set_interface_property raw_exg readyLatency 0 +set_interface_property raw_exg ENABLED true +set_interface_property raw_exg EXPORT_OF "" +set_interface_property raw_exg PORT_NAME_MAP "" +set_interface_property raw_exg CMSIS_SVD_VARIABLES "" +set_interface_property raw_exg SVD_ADDRESS_GROUP "" + +add_interface_port raw_exg asi_raw_exg_data data Input 32 +add_interface_port raw_exg asi_raw_exg_ready ready Output 1 +add_interface_port raw_exg asi_raw_exg_valid valid Input 1 + + +# +# connection point comp_exg +# +add_interface comp_exg avalon_streaming start +set_interface_property comp_exg associatedClock clock +set_interface_property comp_exg associatedReset reset +set_interface_property comp_exg dataBitsPerSymbol 8 +set_interface_property comp_exg errorDescriptor "" +set_interface_property comp_exg firstSymbolInHighOrderBits true +set_interface_property comp_exg maxChannel 0 +set_interface_property comp_exg readyLatency 0 +set_interface_property comp_exg ENABLED true +set_interface_property comp_exg EXPORT_OF "" +set_interface_property comp_exg PORT_NAME_MAP "" +set_interface_property comp_exg CMSIS_SVD_VARIABLES "" +set_interface_property comp_exg SVD_ADDRESS_GROUP "" + +add_interface_port comp_exg aso_comp_exg_data data Output 32 +add_interface_port comp_exg aso_comp_exg_ready ready Input 1 +add_interface_port comp_exg aso_comp_exg_valid valid Output 1 + + +# +# connection point raw_exg_out +# +add_interface raw_exg_out avalon_streaming start +set_interface_property raw_exg_out associatedClock clock +set_interface_property raw_exg_out associatedReset reset +set_interface_property raw_exg_out dataBitsPerSymbol 8 +set_interface_property raw_exg_out errorDescriptor "" +set_interface_property raw_exg_out firstSymbolInHighOrderBits true +set_interface_property raw_exg_out maxChannel 0 +set_interface_property raw_exg_out readyLatency 0 +set_interface_property raw_exg_out ENABLED true +set_interface_property raw_exg_out EXPORT_OF "" +set_interface_property raw_exg_out PORT_NAME_MAP "" +set_interface_property raw_exg_out CMSIS_SVD_VARIABLES "" +set_interface_property raw_exg_out SVD_ADDRESS_GROUP "" + +add_interface_port raw_exg_out aso_raw_exg_data data Output 32 +add_interface_port raw_exg_out aso_raw_exg_ready ready Input 1 +add_interface_port raw_exg_out aso_raw_exg_valid valid Output 1 + Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber.v =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber.v (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber.v (revision 83) @@ -0,0 +1,51 @@ +// signal_grabber.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module signal_grabber #( + parameter ctrl_addr_width = 32, + parameter ctrl_data_width = 32, + parameter audio_str_width = 32, + parameter exg_str_width = 32, + parameter etis_si_width = 32 + ) ( + input wire clk, // clock.clk + input wire reset, // reset.reset + input wire [ctrl_addr_width-1:0] avs_ctrl_address, // ctrl.address + input wire avs_ctrl_read, // .read + output wire [31:0] avs_ctrl_readdata, // .readdata + input wire avs_ctrl_write, // .write + input wire [31:0] avs_ctrl_writedata, // .writedata + output wire avs_ctrl_waitrequest, // .waitrequest + output wire [31:0] aso_raw_audio_data, // audio.data + input wire aso_raw_audio_ready, // .ready + output wire aso_raw_audio_valid, // .valid + output wire [31:0] aso_raw_exg_data, // exg.data + input wire aso_raw_exg_ready, // .ready + output wire aso_raw_exg_valid + ); + + // TODO: Auto-generated HDL template + + assign avs_ctrl_waitrequest = 1'b0; + + assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; + + assign aso_raw_audio_valid = 1'b0; + + assign aso_raw_audio_data = 32'b00000000000000000000000000000000; + + assign aso_raw_exg_valid = 1'b0; + + assign aso_raw_exg_data = 32'b00000000000000000000000000000000; + + assign asi_etis_ready = 1'b0; + +endmodule Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber_hw.tcl =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber_hw.tcl (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber_hw.tcl (revision 83) @@ -0,0 +1,208 @@ +# TCL File Generated by Component Editor 13.1 +# Fri Feb 28 17:57:56 CET 2014 +# DO NOT MODIFY + + +# +# signal_grabber "signal_grabber" v1.0 +# 2014.02.28.17:57:56 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module signal_grabber +# +set_module_property DESCRIPTION "" +set_module_property NAME signal_grabber +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP smartEEG +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME signal_grabber +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL signal_grabber +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter ctrl_addr_width POSITIVE 32 "" +set_parameter_property ctrl_addr_width DEFAULT_VALUE 32 +set_parameter_property ctrl_addr_width DISPLAY_NAME ctrl_addr_width +set_parameter_property ctrl_addr_width WIDTH "" +set_parameter_property ctrl_addr_width TYPE POSITIVE +set_parameter_property ctrl_addr_width UNITS None +set_parameter_property ctrl_addr_width ALLOWED_RANGES 1:2147483647 +set_parameter_property ctrl_addr_width DESCRIPTION "" +set_parameter_property ctrl_addr_width HDL_PARAMETER true +add_parameter ctrl_data_width POSITIVE 32 "" +set_parameter_property ctrl_data_width DEFAULT_VALUE 32 +set_parameter_property ctrl_data_width DISPLAY_NAME ctrl_data_width +set_parameter_property ctrl_data_width WIDTH "" +set_parameter_property ctrl_data_width TYPE POSITIVE +set_parameter_property ctrl_data_width UNITS None +set_parameter_property ctrl_data_width ALLOWED_RANGES 1:2147483647 +set_parameter_property ctrl_data_width DESCRIPTION "" +set_parameter_property ctrl_data_width HDL_PARAMETER true +add_parameter audio_str_width POSITIVE 32 "" +set_parameter_property audio_str_width DEFAULT_VALUE 32 +set_parameter_property audio_str_width DISPLAY_NAME audio_str_width +set_parameter_property audio_str_width WIDTH "" +set_parameter_property audio_str_width TYPE POSITIVE +set_parameter_property audio_str_width UNITS None +set_parameter_property audio_str_width ALLOWED_RANGES 1:2147483647 +set_parameter_property audio_str_width DESCRIPTION "" +set_parameter_property audio_str_width HDL_PARAMETER true +add_parameter exg_str_width POSITIVE 32 "" +set_parameter_property exg_str_width DEFAULT_VALUE 32 +set_parameter_property exg_str_width DISPLAY_NAME exg_str_width +set_parameter_property exg_str_width WIDTH "" +set_parameter_property exg_str_width TYPE POSITIVE +set_parameter_property exg_str_width UNITS None +set_parameter_property exg_str_width ALLOWED_RANGES 1:2147483647 +set_parameter_property exg_str_width DESCRIPTION "" +set_parameter_property exg_str_width HDL_PARAMETER true +add_parameter etis_si_width POSITIVE 32 "" +set_parameter_property etis_si_width DEFAULT_VALUE 32 +set_parameter_property etis_si_width DISPLAY_NAME etis_si_width +set_parameter_property etis_si_width WIDTH "" +set_parameter_property etis_si_width TYPE POSITIVE +set_parameter_property etis_si_width UNITS None +set_parameter_property etis_si_width ALLOWED_RANGES 1:2147483647 +set_parameter_property etis_si_width DESCRIPTION "" +set_parameter_property etis_si_width HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl avs_ctrl_address address Input ctrl_addr_width +add_interface_port ctrl avs_ctrl_read read Input 1 +add_interface_port ctrl avs_ctrl_readdata readdata Output 32 +add_interface_port ctrl avs_ctrl_write write Input 1 +add_interface_port ctrl avs_ctrl_writedata writedata Input 32 +add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point raw_audio +# +add_interface raw_audio avalon_streaming start +set_interface_property raw_audio associatedClock clock +set_interface_property raw_audio associatedReset reset +set_interface_property raw_audio dataBitsPerSymbol 8 +set_interface_property raw_audio errorDescriptor "" +set_interface_property raw_audio firstSymbolInHighOrderBits true +set_interface_property raw_audio maxChannel 0 +set_interface_property raw_audio readyLatency 0 +set_interface_property raw_audio ENABLED true +set_interface_property raw_audio EXPORT_OF "" +set_interface_property raw_audio PORT_NAME_MAP "" +set_interface_property raw_audio CMSIS_SVD_VARIABLES "" +set_interface_property raw_audio SVD_ADDRESS_GROUP "" + +add_interface_port raw_audio aso_raw_audio_data data Output 32 +add_interface_port raw_audio aso_raw_audio_ready ready Input 1 +add_interface_port raw_audio aso_raw_audio_valid valid Output 1 + + +# +# connection point raw_exg +# +add_interface raw_exg avalon_streaming start +set_interface_property raw_exg associatedClock clock +set_interface_property raw_exg associatedReset reset +set_interface_property raw_exg dataBitsPerSymbol 8 +set_interface_property raw_exg errorDescriptor "" +set_interface_property raw_exg firstSymbolInHighOrderBits true +set_interface_property raw_exg maxChannel 0 +set_interface_property raw_exg readyLatency 0 +set_interface_property raw_exg ENABLED true +set_interface_property raw_exg EXPORT_OF "" +set_interface_property raw_exg PORT_NAME_MAP "" +set_interface_property raw_exg CMSIS_SVD_VARIABLES "" +set_interface_property raw_exg SVD_ADDRESS_GROUP "" + +add_interface_port raw_exg aso_raw_exg_data data Output 32 +add_interface_port raw_exg aso_raw_exg_ready ready Input 1 +add_interface_port raw_exg aso_raw_exg_valid valid Output 1 + Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger.v =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger.v (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger.v (revision 83) @@ -0,0 +1,48 @@ +// stream_merger.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module stream_merger #( + parameter AUTO_CLOCK_CLOCK_RATE = "-1" + ) ( + input wire clk, // clock.clk + input wire reset, // reset.reset + input wire [7:0] avs_ctrl_address, // ctrl.address + input wire avs_ctrl_read, // .read + output wire [31:0] avs_ctrl_readdata, // .readdata + input wire avs_ctrl_write, // .write + input wire [31:0] avs_ctrl_writedata, // .writedata + output wire avs_ctrl_waitrequest, // .waitrequest + input wire [31:0] asi_raw_video_data, // raw_video.data + output wire asi_raw_video_ready, // .ready + input wire asi_raw_video_valid, // .valid + input wire [31:0] asi_raw_exg_data, // raw_exg.data + output wire asi_raw_exg_ready, // .ready + input wire asi_raw_exg_valid, // .valid + input wire [31:0] asi_comp_video_data, // comp_video.data + output wire asi_comp_video_ready, // .ready + input wire asi_comp_video_valid, // .valid + input wire [31:0] asi_comp_exg_data, // comp_exg.data + output wire asi_comp_exg_ready, // .ready + input wire asi_comp_exg_valid, // .valid + input wire [31:0] asi_comp_audio_data, // comp_audio.data + output wire asi_comp_audio_ready, // .ready + input wire asi_comp_audio_valid // .valid + ); + + // TODO: Auto-generated HDL template + + assign avs_ctrl_waitrequest = 1'b0; + + assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; + + assign asi_in0_ready = 1'b0; + +endmodule Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger_hw.tcl =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger_hw.tcl (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger_hw.tcl (revision 83) @@ -0,0 +1,229 @@ +# TCL File Generated by Component Editor 13.1 +# Fri Feb 28 18:03:07 CET 2014 +# DO NOT MODIFY + + +# +# stream_merger "stream_merger" v1.0 +# 2014.02.28.18:03:07 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module stream_merger +# +set_module_property DESCRIPTION "" +set_module_property NAME stream_merger +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP smartEEG +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME stream_merger +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL stream_merger +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file stream_merger.v VERILOG PATH stream_merger.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl avs_s0_address address Input 8 +add_interface_port ctrl avs_s0_read read Input 1 +add_interface_port ctrl avs_s0_readdata readdata Output 32 +add_interface_port ctrl avs_s0_write write Input 1 +add_interface_port ctrl avs_s0_writedata writedata Input 32 +add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point raw_video +# +add_interface raw_video avalon_streaming end +set_interface_property raw_video associatedClock clock +set_interface_property raw_video associatedReset reset +set_interface_property raw_video dataBitsPerSymbol 8 +set_interface_property raw_video errorDescriptor "" +set_interface_property raw_video firstSymbolInHighOrderBits true +set_interface_property raw_video maxChannel 0 +set_interface_property raw_video readyLatency 0 +set_interface_property raw_video ENABLED true +set_interface_property raw_video EXPORT_OF "" +set_interface_property raw_video PORT_NAME_MAP "" +set_interface_property raw_video CMSIS_SVD_VARIABLES "" +set_interface_property raw_video SVD_ADDRESS_GROUP "" + +add_interface_port raw_video asi_raw_video_data data Input 32 +add_interface_port raw_video asi_raw_video_ready ready Output 1 +add_interface_port raw_video asi_raw_video_valid valid Input 1 + + +# +# connection point raw_exg +# +add_interface raw_exg avalon_streaming end +set_interface_property raw_exg associatedClock clock +set_interface_property raw_exg associatedReset reset +set_interface_property raw_exg dataBitsPerSymbol 8 +set_interface_property raw_exg errorDescriptor "" +set_interface_property raw_exg firstSymbolInHighOrderBits true +set_interface_property raw_exg maxChannel 0 +set_interface_property raw_exg readyLatency 0 +set_interface_property raw_exg ENABLED true +set_interface_property raw_exg EXPORT_OF "" +set_interface_property raw_exg PORT_NAME_MAP "" +set_interface_property raw_exg CMSIS_SVD_VARIABLES "" +set_interface_property raw_exg SVD_ADDRESS_GROUP "" + +add_interface_port raw_exg asi_raw_exg_data data Input 32 +add_interface_port raw_exg asi_raw_exg_ready ready Output 1 +add_interface_port raw_exg asi_raw_exg_valid valid Input 1 + + +# +# connection point comp_video +# +add_interface comp_video avalon_streaming end +set_interface_property comp_video associatedClock clock +set_interface_property comp_video associatedReset reset +set_interface_property comp_video dataBitsPerSymbol 8 +set_interface_property comp_video errorDescriptor "" +set_interface_property comp_video firstSymbolInHighOrderBits true +set_interface_property comp_video maxChannel 0 +set_interface_property comp_video readyLatency 0 +set_interface_property comp_video ENABLED true +set_interface_property comp_video EXPORT_OF "" +set_interface_property comp_video PORT_NAME_MAP "" +set_interface_property comp_video CMSIS_SVD_VARIABLES "" +set_interface_property comp_video SVD_ADDRESS_GROUP "" + +add_interface_port comp_video asi_comp_video_data data Input 32 +add_interface_port comp_video asi_comp_video_ready ready Output 1 +add_interface_port comp_video asi_comp_video_valid valid Input 1 + + +# +# connection point comp_exg +# +add_interface comp_exg avalon_streaming end +set_interface_property comp_exg associatedClock clock +set_interface_property comp_exg associatedReset reset +set_interface_property comp_exg dataBitsPerSymbol 8 +set_interface_property comp_exg errorDescriptor "" +set_interface_property comp_exg firstSymbolInHighOrderBits true +set_interface_property comp_exg maxChannel 0 +set_interface_property comp_exg readyLatency 0 +set_interface_property comp_exg ENABLED true +set_interface_property comp_exg EXPORT_OF "" +set_interface_property comp_exg PORT_NAME_MAP "" +set_interface_property comp_exg CMSIS_SVD_VARIABLES "" +set_interface_property comp_exg SVD_ADDRESS_GROUP "" + +add_interface_port comp_exg asi_comp_exg_data data Input 32 +add_interface_port comp_exg asi_comp_exg_ready ready Output 1 +add_interface_port comp_exg asi_comp_exg_valid valid Input 1 + + +# +# connection point comp_audio +# +add_interface comp_audio avalon_streaming end +set_interface_property comp_audio associatedClock clock +set_interface_property comp_audio associatedReset reset +set_interface_property comp_audio dataBitsPerSymbol 8 +set_interface_property comp_audio errorDescriptor "" +set_interface_property comp_audio firstSymbolInHighOrderBits true +set_interface_property comp_audio maxChannel 0 +set_interface_property comp_audio readyLatency 0 +set_interface_property comp_audio ENABLED true +set_interface_property comp_audio EXPORT_OF "" +set_interface_property comp_audio PORT_NAME_MAP "" +set_interface_property comp_audio CMSIS_SVD_VARIABLES "" +set_interface_property comp_audio SVD_ADDRESS_GROUP "" + +add_interface_port comp_audio asi_comp_audio_data data Input 32 +add_interface_port comp_audio asi_comp_audio_ready ready Output 1 +add_interface_port comp_audio asi_comp_audio_valid valid Input 1 + Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro.v =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro.v (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro.v (revision 83) @@ -0,0 +1,41 @@ +// synchro.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module synchro ( + input wire [7:0] avs_s0_address, // s0.address + input wire avs_s0_read, // .read + output wire [31:0] avs_s0_readdata, // .readdata + input wire avs_s0_write, // .write + input wire [31:0] avs_s0_writedata, // .writedata + output wire avs_s0_waitrequest, // .waitrequest + input wire clk, // clock.clk + input wire reset, // reset.reset + output wire video_trigger, // conduit_sync.export + output wire etis_sync_clock, // .export + output wire etis_sync_clock_start, // .export + output wire [31:0] aso_ts_data, // ts.data + input wire aso_ts_ready, // .ready + output wire aso_ts_valid // .valid + ); + + // TODO: Auto-generated HDL template + + assign avs_s0_waitrequest = 1'b0; + + assign avs_s0_readdata = 32'b00000000000000000000000000000000; + + assign video_trigger = 1'b0; + + assign etis_sync_clock_start = 1'b0; + + assign etis_sync_clock = 1'b0; + +endmodule Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro_hw.tcl =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro_hw.tcl (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro_hw.tcl (revision 83) @@ -0,0 +1,158 @@ +# TCL File Generated by Component Editor 13.1 +# Fri Feb 28 17:08:14 CET 2014 +# DO NOT MODIFY + + +# +# synchro "synchro" v1.0 +# 2014.02.28.17:08:14 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module synchro +# +set_module_property DESCRIPTION "" +set_module_property NAME synchro +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP smartEEG +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME synchro +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL synchro +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file synchro.v VERILOG PATH synchro.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point conduit_sync +# +add_interface conduit_sync conduit end +set_interface_property conduit_sync associatedClock clock +set_interface_property conduit_sync associatedReset "" +set_interface_property conduit_sync ENABLED true +set_interface_property conduit_sync EXPORT_OF "" +set_interface_property conduit_sync PORT_NAME_MAP "" +set_interface_property conduit_sync CMSIS_SVD_VARIABLES "" +set_interface_property conduit_sync SVD_ADDRESS_GROUP "" + +add_interface_port conduit_sync video_trigger export Output 1 +add_interface_port conduit_sync etis_sync_clock export Output 1 +add_interface_port conduit_sync etis_sync_clock_start export Output 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl avs_s0_address address Input 8 +add_interface_port ctrl avs_s0_read read Input 1 +add_interface_port ctrl avs_s0_readdata readdata Output 32 +add_interface_port ctrl avs_s0_write write Input 1 +add_interface_port ctrl avs_s0_writedata writedata Input 32 +add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point ts +# +add_interface ts avalon_streaming start +set_interface_property ts associatedClock clock +set_interface_property ts associatedReset reset +set_interface_property ts dataBitsPerSymbol 8 +set_interface_property ts errorDescriptor "" +set_interface_property ts firstSymbolInHighOrderBits true +set_interface_property ts maxChannel 0 +set_interface_property ts readyLatency 0 +set_interface_property ts ENABLED true +set_interface_property ts EXPORT_OF "" +set_interface_property ts PORT_NAME_MAP "" +set_interface_property ts CMSIS_SVD_VARIABLES "" +set_interface_property ts SVD_ADDRESS_GROUP "" + +add_interface_port ts aso_ts_data data Output 32 +add_interface_port ts aso_ts_ready ready Input 1 +add_interface_port ts aso_ts_valid valid Output 1 + Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec.v =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec.v (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec.v (revision 83) @@ -0,0 +1,49 @@ +// video_codec.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module video_codec #( + parameter AUTO_CLOCK_CLOCK_RATE = "-1" + ) ( + input wire clk, // clock.clk + input wire reset, // reset.reset + input wire [7:0] avs_ctrl_address, // ctrl.address + input wire avs_ctrl_read, // .read + output wire [31:0] avs_ctrl_readdata, // .readdata + input wire avs_ctrl_write, // .write + input wire [31:0] avs_ctrl_writedata, // .writedata + output wire avs_ctrl_waitrequest, // .waitrequest + input wire [31:0] asi_raw_video_data, // raw_video.data + output wire asi_raw_video_ready, // .ready + input wire asi_raw_video_valid, // .valid + input wire aso_raw_video_ds_ready, // raw_video_ds.ready + output wire aso_raw_video_ds_valid, // .valid + output wire [31:0] aso_raw_video_ds_data, // .data + input wire aso_comp_video_ready, // comp_video.ready + output wire aso_comp_video_valid, // .valid + output wire [31:0] aso_comp_video_data, // .data + input wire [31:0] asi_ts_data, // ts.data + output wire asi_ts_ready, // .ready + input wire asi_ts_valid // .valid + ); + + // TODO: Auto-generated HDL template + + assign avs_s0_waitrequest = 1'b0; + + assign avs_s0_readdata = 32'b00000000000000000000000000000000; + + assign asi_in0_ready = 1'b0; + + assign aso_out0_valid = 1'b0; + + assign aso_out0_data = 32'b00000000000000000000000000000000; + +endmodule Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec_hw.tcl =================================================================== --- /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec_hw.tcl (revision 83) +++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec_hw.tcl (revision 83) @@ -0,0 +1,207 @@ +# TCL File Generated by Component Editor 13.1 +# Fri Feb 28 17:11:09 CET 2014 +# DO NOT MODIFY + + +# +# video_codec "video_codec" v1.0 +# 2014.02.28.17:11:09 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module video_codec +# +set_module_property DESCRIPTION "" +set_module_property NAME video_codec +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP smartEEG +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME video_codec +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL video_codec +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file video_codec.v VERILOG PATH video_codec.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl avs_ctrl_address address Input 8 +add_interface_port ctrl avs_ctrl_read read Input 1 +add_interface_port ctrl avs_ctrl_readdata readdata Output 32 +add_interface_port ctrl avs_ctrl_write write Input 1 +add_interface_port ctrl avs_ctrl_writedata writedata Input 32 +add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point raw_video +# +add_interface raw_video avalon_streaming end +set_interface_property raw_video associatedClock clock +set_interface_property raw_video associatedReset reset +set_interface_property raw_video dataBitsPerSymbol 8 +set_interface_property raw_video errorDescriptor "" +set_interface_property raw_video firstSymbolInHighOrderBits true +set_interface_property raw_video maxChannel 0 +set_interface_property raw_video readyLatency 0 +set_interface_property raw_video ENABLED true +set_interface_property raw_video EXPORT_OF "" +set_interface_property raw_video PORT_NAME_MAP "" +set_interface_property raw_video CMSIS_SVD_VARIABLES "" +set_interface_property raw_video SVD_ADDRESS_GROUP "" + +add_interface_port raw_video asi_raw_video_data data Input 32 +add_interface_port raw_video asi_raw_video_ready ready Output 1 +add_interface_port raw_video asi_raw_video_valid valid Input 1 + + +# +# connection point comp_video +# +add_interface comp_video avalon_streaming start +set_interface_property comp_video associatedClock clock +set_interface_property comp_video associatedReset reset +set_interface_property comp_video dataBitsPerSymbol 8 +set_interface_property comp_video errorDescriptor "" +set_interface_property comp_video firstSymbolInHighOrderBits true +set_interface_property comp_video maxChannel 0 +set_interface_property comp_video readyLatency 0 +set_interface_property comp_video ENABLED true +set_interface_property comp_video EXPORT_OF "" +set_interface_property comp_video PORT_NAME_MAP "" +set_interface_property comp_video CMSIS_SVD_VARIABLES "" +set_interface_property comp_video SVD_ADDRESS_GROUP "" + +add_interface_port comp_video aso_comp_video_ready ready Input 1 +add_interface_port comp_video aso_comp_video_data data Output 32 +add_interface_port comp_video aso_comp_video_valid valid Output 1 + + +# +# connection point raw_video_ds +# +add_interface raw_video_ds avalon_streaming start +set_interface_property raw_video_ds associatedClock clock +set_interface_property raw_video_ds associatedReset reset +set_interface_property raw_video_ds dataBitsPerSymbol 8 +set_interface_property raw_video_ds errorDescriptor "" +set_interface_property raw_video_ds firstSymbolInHighOrderBits true +set_interface_property raw_video_ds maxChannel 0 +set_interface_property raw_video_ds readyLatency 0 +set_interface_property raw_video_ds ENABLED true +set_interface_property raw_video_ds EXPORT_OF "" +set_interface_property raw_video_ds PORT_NAME_MAP "" +set_interface_property raw_video_ds CMSIS_SVD_VARIABLES "" +set_interface_property raw_video_ds SVD_ADDRESS_GROUP "" + +add_interface_port raw_video_ds aso_raw_video_ds_ready ready Input 1 +add_interface_port raw_video_ds aso_raw_video_ds_valid valid Output 1 +add_interface_port raw_video_ds aso_raw_video_ds_data data Output 32 + + +# +# connection point ts +# +add_interface ts avalon_streaming end +set_interface_property ts associatedClock clock +set_interface_property ts associatedReset reset +set_interface_property ts dataBitsPerSymbol 8 +set_interface_property ts errorDescriptor "" +set_interface_property ts firstSymbolInHighOrderBits true +set_interface_property ts maxChannel 0 +set_interface_property ts readyLatency 0 +set_interface_property ts ENABLED true +set_interface_property ts EXPORT_OF "" +set_interface_property ts PORT_NAME_MAP "" +set_interface_property ts CMSIS_SVD_VARIABLES "" +set_interface_property ts SVD_ADDRESS_GROUP "" + +add_interface_port ts asi_ts_data data Input 32 +add_interface_port ts asi_ts_ready ready Output 1 +add_interface_port ts asi_ts_valid valid Input 1 +