Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec_hw.tcl
===================================================================
--- /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec_hw.tcl	(revision 86)
+++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec_hw.tcl	(revision 87)
@@ -1,4 +1,4 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 16:58:45 CET 2014
+# Mon Mar 03 15:31:24 CET 2014
 # DO NOT MODIFY
 
@@ -6,5 +6,5 @@
 # 
 # audio_codec "audio_codec" v1.0
-#  2014.02.28.16:58:45
+#  2014.03.03.15:31:24
 # 
 # 
@@ -41,4 +41,9 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file audio_codec.v VERILOG PATH audio_codec.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL audio_codec
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file audio_codec.v VERILOG PATH audio_codec.v
 
 
Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec_hw.tcl
===================================================================
--- /PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec_hw.tcl	(revision 86)
+++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec_hw.tcl	(revision 87)
@@ -1,4 +1,4 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 17:02:33 CET 2014
+# Mon Mar 03 15:32:05 CET 2014
 # DO NOT MODIFY
 
@@ -6,5 +6,5 @@
 # 
 # exg_codec "exg_codec" v1.0
-#  2014.02.28.17:02:33
+#  2014.03.03.15:32:05
 # 
 # 
@@ -41,4 +41,9 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file exg_codec.v VERILOG PATH exg_codec.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL exg_codec
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file exg_codec.v VERILOG PATH exg_codec.v
 
 
Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber_hw.tcl
===================================================================
--- /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber_hw.tcl	(revision 86)
+++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber_hw.tcl	(revision 87)
@@ -1,4 +1,4 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 17:27:39 CET 2014
+# Mon Mar 03 15:33:08 CET 2014
 # DO NOT MODIFY
 
@@ -6,5 +6,5 @@
 # 
 # frame_grabber "frame_grabber" v1.0
-#  2014.02.28.17:27:39
+#  2014.03.03.15:33:08
 # 
 # 
@@ -41,4 +41,9 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL frame_grabber
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v
 
 
Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber_hw.tcl
===================================================================
--- /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber_hw.tcl	(revision 86)
+++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber_hw.tcl	(revision 87)
@@ -1,4 +1,4 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 17:57:56 CET 2014
+# Mon Mar 03 15:33:43 CET 2014
 # DO NOT MODIFY
 
@@ -6,5 +6,5 @@
 # 
 # signal_grabber "signal_grabber" v1.0
-#  2014.02.28.17:57:56
+#  2014.03.03.15:33:43
 # 
 # 
@@ -41,4 +41,9 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL signal_grabber
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v
 
 
Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger_hw.tcl
===================================================================
--- /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger_hw.tcl	(revision 86)
+++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger_hw.tcl	(revision 87)
@@ -1,4 +1,4 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 18:03:07 CET 2014
+# Mon Mar 03 15:30:43 CET 2014
 # DO NOT MODIFY
 
@@ -6,5 +6,5 @@
 # 
 # stream_merger "stream_merger" v1.0
-#  2014.02.28.18:03:07
+#  2014.03.03.15:30:43
 # 
 # 
@@ -41,4 +41,9 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file stream_merger.v VERILOG PATH stream_merger.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL stream_merger
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file stream_merger.v VERILOG PATH stream_merger.v
 
 
@@ -107,10 +112,10 @@
 set_interface_property ctrl SVD_ADDRESS_GROUP ""
 
-add_interface_port ctrl avs_s0_address address Input 8
-add_interface_port ctrl avs_s0_read read Input 1
-add_interface_port ctrl avs_s0_readdata readdata Output 32
-add_interface_port ctrl avs_s0_write write Input 1
-add_interface_port ctrl avs_s0_writedata writedata Input 32
-add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1
+add_interface_port ctrl avs_ctrl_address address Input 8
+add_interface_port ctrl avs_ctrl_read read Input 1
+add_interface_port ctrl avs_ctrl_readdata readdata Output 32
+add_interface_port ctrl avs_ctrl_write write Input 1
+add_interface_port ctrl avs_ctrl_writedata writedata Input 32
+add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
 set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
 set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro_hw.tcl
===================================================================
--- /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro_hw.tcl	(revision 86)
+++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro_hw.tcl	(revision 87)
@@ -1,4 +1,4 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 17:08:14 CET 2014
+# Mon Mar 03 15:34:33 CET 2014
 # DO NOT MODIFY
 
@@ -6,5 +6,5 @@
 # 
 # synchro "synchro" v1.0
-#  2014.02.28.17:08:14
+#  2014.03.03.15:34:33
 # 
 # 
@@ -41,4 +41,9 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file synchro.v VERILOG PATH synchro.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL synchro
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file synchro.v VERILOG PATH synchro.v
 
 
Index: /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec_hw.tcl
===================================================================
--- /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec_hw.tcl	(revision 86)
+++ /PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec_hw.tcl	(revision 87)
@@ -1,4 +1,4 @@
 # TCL File Generated by Component Editor 13.1
-# Fri Feb 28 17:11:09 CET 2014
+# Mon Mar 03 15:34:59 CET 2014
 # DO NOT MODIFY
 
@@ -6,5 +6,5 @@
 # 
 # video_codec "video_codec" v1.0
-#  2014.02.28.17:11:09
+#  2014.03.03.15:34:59
 # 
 # 
@@ -41,4 +41,9 @@
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 add_fileset_file video_codec.v VERILOG PATH video_codec.v TOP_LEVEL_FILE
+
+add_fileset SIM_VERILOG SIM_VERILOG "" ""
+set_fileset_property SIM_VERILOG TOP_LEVEL video_codec
+set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file video_codec.v VERILOG PATH video_codec.v