Ignore:
Timestamp:
Mar 3, 2014, 4:47:59 PM (10 years ago)
Author:
szahmed
Message:

Added Headline comments for Verilog files explaining their brief properties, version number etc.

File:
1 edited

Legend:

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  • PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec.v

    r84 r89  
    1 // exg_codec.v
    2 
    3 // This file was auto-generated as a prototype implementation of a module
    4 // created in component editor.  It ties off all outputs to ground and
    5 // ignores all inputs.  It needs to be edited to make it do something
    6 // useful.
    7 //
    8 // This file will not be automatically regenerated.  You should check it in
    9 // to your version control system if you want to keep it.
     1/********************************************************************
     2 *                    COPYRIGHT LIP6 2014
     3 *-----------------------------------------------------------------*/
     4/**
     5 * @file    exg_codec.v
     6 * @brief   Performs EXG data Compression/Processing
     7 *
     8 * This module perfoms recieves raw EXG data from AvalonST sink, perfoms compression/processing of the data
     9 * and sends the input raw data and compressed data to stream merger module via AvalonST sources
     10 *
     11 * @author  S. Z. Ahmed         <syed-zahid.ahmed@lip6.fr>
     12 * @author  L. Lambert          <laurent.lambert@lip6.fr>
     13 * @date    Fri. 28 Feb. 2014
     14 *
     15 * Revision History
     16 * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
     17 *
     18 *******************************************************************/
    1019
    1120`timescale 1 ps / 1 ps
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