Index: PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec.v
===================================================================
--- PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec.v	(revision 87)
+++ PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec.v	(revision 89)
@@ -1,11 +1,20 @@
-// audio_codec.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    audio_codec.v
+ * @brief   Performs Audio Compression
+ *
+ * This module perfoms audio compression of raw data received from AvalonST sink and sends
+ * the compressed audio via AvalonST source to stream merger module
+ *
+ * @author  S. Z. Ahmed 	<syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert  	<laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
Index: PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec.v
===================================================================
--- PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec.v	(revision 87)
+++ PROJECT_SMART_EEG/trunk/hw/sync_sys/exg_codec/exg_codec.v	(revision 89)
@@ -1,11 +1,20 @@
-// exg_codec.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    exg_codec.v
+ * @brief   Performs EXG data Compression/Processing
+ *
+ * This module perfoms recieves raw EXG data from AvalonST sink, perfoms compression/processing of the data
+ * and sends the input raw data and compressed data to stream merger module via AvalonST sources
+ *
+ * @author  S. Z. Ahmed 	<syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert  	<laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
Index: PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber.v
===================================================================
--- PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber.v	(revision 87)
+++ PROJECT_SMART_EEG/trunk/hw/sync_sys/frame_grabber/frame_grabber.v	(revision 89)
@@ -1,11 +1,20 @@
-// frame_grabber.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    frame_grabber.v
+ * @brief   Performs frame grabbing, Bayer->RGB conversion and sends the raw data to video codec module
+ *
+ * This module perfoms the frame grabbing of the terasic D5M camera that is connected with GPIO of DE4, it then
+ * performs Bayer->RGB conversion and sends the raw data to the video codec via AvalonST source
+ *
+ * @author  S. Z. Ahmed 	<syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert  	<laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
@@ -13,13 +22,13 @@
 		input  wire        clk,                //     clock.clk
 		input  wire        reset,              //     reset.reset
-		input  wire [7:0]  avs_s0_address,     //      ctrl.address
-		input  wire        avs_s0_read,        //          .read
-		output wire [31:0] avs_s0_readdata,    //          .readdata
-		input  wire        avs_s0_write,       //          .write
-		input  wire [31:0] avs_s0_writedata,   //          .writedata
-		output wire        avs_s0_waitrequest, //          .waitrequest
-		output wire [31:0] aso_out0_data,      // raw_video.data
-		input  wire        aso_out0_ready,     //          .ready
-		output wire        aso_out0_valid,      //          .valid
+		input  wire [7:0]  avs_ctrl_address,     //      ctrl.address
+		input  wire        avs_ctrl_read,        //          .read
+		output wire [31:0] avs_ctrl_readdata,    //          .readdata
+		input  wire        avs_ctrl_write,       //          .write
+		input  wire [31:0] avs_ctrl_writedata,   //          .writedata
+		output wire        avs_ctrl_waitrequest, //          .waitrequest
+		output wire [31:0] aso_raw_video_data,      // raw_video.data
+		input  wire        aso_raw_video_ready,     //          .ready
+		output wire        aso_raw_video_valid,      //          .valid
 		
 		input		    [11:0]		D5M_D,
@@ -37,7 +46,7 @@
 	// TODO: Auto-generated HDL template
 
-	assign avs_s0_waitrequest = 1'b0;
+	assign avs_ctrl_waitrequest = 1'b0;
 
-	assign avs_s0_readdata = 32'b00000000000000000000000000000000;
+	assign avs_ctrl_readdata = 32'b00000000000000000000000000000000;
 
 	assign aso_out0_valid = 1'b0;
Index: PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber.v
===================================================================
--- PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber.v	(revision 87)
+++ PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber/signal_grabber.v	(revision 89)
@@ -1,11 +1,20 @@
-// signal_grabber.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    signal_grabber.v
+ * @brief   Performs signal grabbing of EXG and Audio data coming from ETIS
+ *
+ * This module performs grabbing of time-stamped EXG and Audio data coming from ETIS (In initial versions create dummy/test data via internal logic of
+ * this module for validation of rest of the system). It sends the data received/Modeled from/of ETIS to Audio and EXG coders via AvalonST source
+ *
+ * @author  S. Z. Ahmed 	<syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert  	<laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
Index: PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger.v
===================================================================
--- PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger.v	(revision 87)
+++ PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger/stream_merger.v	(revision 89)
@@ -1,11 +1,24 @@
-// stream_merger.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    stream_merger.v
+ * @brief   Receives time-stamped {Downscaled RAW Video, Compressed Video, Raw EXG, Compressed EXG, Compressed Audio)
+ *          and sends them to tramission Card (exptected to be via HSMC)
+ *
+ * This module receives three components of SmartEEG data.
+ * 1- Time-stamped downscaled RAW (for live privew) and Compressed Video from the Video coder via AvalonST sinks.
+ * 2- Time stamped compressed Audio via AvalonST sink
+ * 3- Time stamped RAW and Compressed EXG data via AvalonST sinks
+ * It transmits these data channels to transmitter card (ARM-based CycloneV FPGA SocKit board connected via HSMC)
+ *
+ * @author  S. Z. Ahmed 	<syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert  	<laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
Index: PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro.v
===================================================================
--- PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro.v	(revision 87)
+++ PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro/synchro.v	(revision 89)
@@ -1,20 +1,30 @@
-// synchro.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    synchro.v
+ * @brief   Creats video trigger, time-stamp/sync clock and rest signal (for ETIS)
+ *
+ * This module generates the Video trigger signal for the Camera at the choosen fps. It also generates the time-stamp/sync clock that is
+ * used by both Acquision (ETIS) and Compression (Lip6) boards for time-stamp counters along with a start signal whic resets the time-stamp
+ * counters when the acquisition start command comes from PC (Acacia). The value of time-stamp register is transmitted to the Video coder via AvalonST source 
+ *
+ * @author  S. Z. Ahmed 	<syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert  	<laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
 module synchro (
-		input  wire [7:0]  avs_s0_address,        //           s0.address
-		input  wire        avs_s0_read,           //             .read
-		output wire [31:0] avs_s0_readdata,       //             .readdata
-		input  wire        avs_s0_write,          //             .write
-		input  wire [31:0] avs_s0_writedata,      //             .writedata
-		output wire        avs_s0_waitrequest,    //             .waitrequest
+		input  wire [7:0]  avs_ctrl_address,        //           ctrl.address
+		input  wire        avs_ctrl_read,           //             .read
+		output wire [31:0] avs_ctrl_readdata,       //             .readdata
+		input  wire        avs_ctrl_write,          //             .write
+		input  wire [31:0] avs_ctrl_writedata,      //             .writedata
+		output wire        avs_ctrl_waitrequest,    //             .waitrequest
 		input  wire        clk,                   //        clock.clk
 		input  wire        reset,                 //        reset.reset
@@ -29,7 +39,7 @@
 	// TODO: Auto-generated HDL template
 
-	assign avs_s0_waitrequest = 1'b0;
+	assign avs_ctrl_waitrequest = 1'b0;
 
-	assign avs_s0_readdata = 32'b00000000000000000000000000000000;
+	assign avs_ctrl_readdata = 32'b00000000000000000000000000000000;
 
 	assign video_trigger = 1'b0;
Index: PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec.v
===================================================================
--- PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec.v	(revision 87)
+++ PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec.v	(revision 89)
@@ -1,11 +1,20 @@
-// video_codec.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
+/********************************************************************
+ *                    COPYRIGHT LIP6 2014
+ *-----------------------------------------------------------------*/
+/** 
+ * @file    video_codec.v
+ * @brief   Performs Video Compression and Downscaled raw video bypass
+ *
+ * This module receives the RAW video data from Frame Grabber via AvalonST sink. It performs Video Compression and Downscaled RAW video bypass (for live preview),
+ * it adds time-stamp to the video frames that is received via AvalonST sink from synchro module. It transmitts the RAW and Compressed Data to stream merger via AvalonST sources
+ *
+ * @author  S. Z. Ahmed 	<syed-zahid.ahmed@lip6.fr>
+ * @author  L. Lambert  	<laurent.lambert@lip6.fr>
+ * @date    Fri. 28 Feb. 2014
+ * 
+ * Revision History
+ * @version  V1.0  Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui}
+ *
+ *******************************************************************/
 
 `timescale 1 ps / 1 ps
