Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/CORE_MPI.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/CORE_MPI.vhd	(revision 96)
+++ 	(revision )
@@ -1,997 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer:  GAMOM NGOUNOU
--- 
--- Create Date:    05:52:25 06/21/2011 
--- Design Name: 
--- Module Name:    CORE_MPI - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-Library NocLib;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity CORE_MPI is
-    Port ( 
-				clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-	         clkout : out std_logic;
-				instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           instruction_en : in  STD_LOGIC; --valide l'instruction
-			  instruction_fifo_full : out  STD_LOGIC;
-           ram_data_in : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           barrier_completed : out  STD_LOGIC;
-           packet_received : out  STD_LOGIC;
-			  packet_ack : in std_logic;
-           PushOut : out  STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution
-           ram_we : out  STD_LOGIC;
-           ram_en : out  STD_LOGIC;
-			  ram_address_rd : out  STD_LOGIC_VECTOR (15 downto 0);
-			  ram_address_wr : out  STD_LOGIC_VECTOR (15 downto 0);
-           ram_data_out : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  hold_req       : out STD_Logic;  --requete vers application
-			  hold_ack       : in  STD_Logic;  --autorisation par l'application
-           switch_port_in_cmd_en : out std_logic;
-			  switch_port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  switch_port_in_wr_en : out  STD_LOGIC;
-           switch_port_in_full : in  STD_LOGIC;
-           switch_port_in_data : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           switch_port_out_rd_en : out  STD_LOGIC;
-           switch_port_in_empty : in STD_LOGIC;
-			  switch_port_out_data_vailaible : in  STD_LOGIC
-           );
-           
-end CORE_MPI;
-
-architecture Structural of CORE_MPI is
---déclaration des types
-type Type_Noc is
-record
- port_in_cmd_en :  std_logic;
- port_out_data :   STD_LOGIC_VECTOR (Word-1 downto 0);
- port_in_wr_en :   STD_LOGIC;
- port_in_empty : STD_LOGIC;
- port_in_full :  STD_LOGIC;
- port_in_data :  STD_LOGIC_VECTOR (Word-1 downto 0);
- port_out_rd_en :  STD_LOGIC;
- port_out_data_available :  STD_LOGIC;
-end record;
--- déclaration des composants MPI
-
-COMPONENT FIFO_64_FWFT
-	PORT(
-		clk : IN std_logic;
-		din : IN std_logic_vector(Word-1 downto 0);
-		rd_en : IN std_logic;
-		srst : IN std_logic;
-		wr_en : IN std_logic;          
-		dout : OUT std_logic_vector(Word-1 downto 0);
-		empty : OUT std_logic;
-		full : OUT std_logic
-		);
-END COMPONENT;
-COMPONENT load_instr 
-    Port ( Instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Instruction_en : in  STD_LOGIC;
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           dma_rd_grant : in  STD_LOGIC;
-           dma_rd_request : out  STD_LOGIC;
-           instruction_ack : out  STD_LOGIC;
-           fifo_din : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  fifo_wr :out std_logic;
-           fifo_full : in  STD_LOGIC;
-			  copying : out std_logic;
-			  Ram_rd_en : out STD_LOGIC;
-           ram_address_rd : buffer  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           ram_data : in  STD_LOGIC_VECTOR (WORD-1 downto 0));
-end component;
-COMPONENT DMA_ARBITER
-	PORT(
-		
-		clk : IN std_logic;
-		reset : IN std_logic;
-		dma_rd_request : IN std_logic_vector(3 downto 0);
-		data_wr_in : IN std_logic_vector(Word-1 downto 0);
-		data_rd_out : out std_logic_vector(Word-1 downto 0);
-		address_rd : IN std_logic_vector(15 downto 0);
-		address_wr : IN std_logic_vector(15 downto 0);
-		
-		dma_wr_request : IN std_logic_vector(3 downto 0);          
-		address_out_rd : OUT std_logic_vector(15 downto 0);
-		address_out_wr : OUT std_logic_vector(15 downto 0);
-		ram_en : OUT std_logic;
-		ram_we : OUT std_logic;
-		hold_req       : out STD_Logic;  --requete vers application
-		hold_ack       : in  STD_Logic;  --autorisation par l'application
-		data_wr_mem  : OUT std_logic_vector(Word-1 downto 0); 
-		data_rd_mem  : IN std_logic_vector(Word-1 downto 0);
-		dma_wr_grant : OUT std_logic_vector(3 downto 0);
-		dma_rd_grant : OUT std_logic_vector(3 downto 0)
-		);
-END COMPONENT;
-
-COMPONENT EX1_FSM
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		
-		pid : in std_logic_vector (3 downto 0); --port id
-		nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc
-    instruction : in std_logic_vector(Word-1 downto 0); 
-		instruction_en : in std_logic;
-		fifo_empty : IN std_logic;
-		fifo_data_out : IN std_logic_vector(Word-1 downto 0);
-		fifo_rd_en : OUT std_logic;
-		fifo_src : IN STD_LOGIC;
-		ram_data_in : IN std_logic_vector(Word-1 downto 0);
-		ram_data_out : out std_logic_vector(Word-1 downto 0);
-		dma_rd_grant : IN std_logic;   
-		dma_wr_grant : IN std_logic;   		
-		dma_wr_request : OUT std_logic;
-		dma_rd_request : OUT std_logic;
-		ram_address : OUT std_logic_vector(15 downto 0);
-		ram_rd,ram_wr : out std_logic;
-		Snd_Data : IN Typ_PortIO(0 to 3);
-		Snd_Start : IN std_logic;
-		Snd_Ack : OUT std_logic;		
-		priority_rotation : OUT std_logic;
-		
-		switch_port_in_data : OUT std_logic_vector(Word-1 downto 0);
-		switch_port_in_wr_en : OUT std_logic;
-		switch_port_in_full : IN std_logic;
-		Result :out std_logic_vector(Word-1 downto 0);
-		Ready : out std_logic;
-		AppInitReq :out  STD_LOGIC; -- requête d'initialisation de l'application
-		AppInitAck :in  STD_LOGIC; -- Acquitement d'initialisation
-		Initialized:in   std_logic  -- état de la Lib
-		);
-	END COMPONENT;	
-	
-COMPONENT EX2_FSM
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		
-		instruction_en: in std_logic;
-		Initialized : in std_logic;
-		
-		switch_port_out_rd_en : OUT std_logic ;
-		switch_data_available : IN std_logic;
-		switch_port_out_data : IN std_logic_vector(Word-1 downto 0);
-		AppRank : in  STD_LOGIC_VECTOR;
-      AppSize : in  STD_LOGIC_VECTOR;		  
-		dma_wr_grant : IN std_logic;
-		dma_wr_request : OUT std_logic;
-		dma_rd_grant : IN std_logic;
-		dma_rd_request : OUT std_logic;
-		ram_address : OUT std_logic_vector(15 downto 0);
-		ram_rd,ram_wr : out std_logic;
-		Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
-		Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-		fifo_full : IN std_logic;
-		 Rec_Rdy : OUT std_logic;
-		 Rec_Data : buffer Typ_PortIO(0 to 3);
-		 Rec_Ack : IN std_logic;
-		fifo_data : OUT std_logic_vector(Word-1 downto 0);
-		fifo_wr_en : OUT std_logic;
-		--fifo_out : out std_logic_vector;
-		Result : out STD_LOGIC_VECTOR (Word-1 downto 0);
-		packet_received : OUT std_logic;
-		packet_ack : IN std_logic;
-		barrier_completed : OUT std_logic;
-		Ready : Out std_logic;
-		AppInitAck : in std_logic;
-		AppInitReq : out std_logic
-		);
-	END COMPONENT;
-
-
-	COMPONENT EX3_FSM
-	PORT(
-		instruction : IN std_logic_vector(Word-1 downto 0);
-		clk : IN std_logic;
-		reset : IN std_logic;     
-		Ismain :in std_logic;
-		ResOut : OUT std_logic_vector(Word-1 downto 0)
-		
-		);
-	END COMPONENT;
-	
-	COMPONENT EX4_FSM
-	PORT(
-    		  Instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO
-           Instruction_En : in  STD_LOGIC;
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           ResultOut : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Result_En : out  STD_LOGIC; 
-           Ready : out  STD_LOGIC; 
-           NocSize : out  STD_LOGIC_VECTOR;
-           AppRank : out  STD_LOGIC_VECTOR;
-           AppSize : out  STD_LOGIC_VECTOR;
-           IsMain : out  STD_LOGIC;
-           I_fifo_full :in STD_LOGIC;
-		      Snd_Ack : IN std_logic;
-		      Rec_Rdy : IN std_logic;
-		      Rec_Data : IN Typ_PortIO(0 to 3);
-		      Snd_data : OUT Typ_PortIO(0 to 3);
-		      Snd_Start : buffer std_logic;
-		      Rec_Ack : OUT std_logic; 
-		      I_fifo_wr_en: out STD_LOGIC;
-		      I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0);
-			  Initialized : out STD_LOGIC;
-			  dma_wr_request : out std_logic;
-			  dma_rd_request : out std_logic;
-			  dma_wr_grant : in std_logic;
-			  dma_rd_grant : in std_logic;
-           Ram_address : out  STD_LOGIC_VECTOR (15 downto 0); --accès au stockage
-           Ram_wr : out  STD_LOGIC; --activation de l'écriture en RAM
-           Ram_Data_in : out  STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports
-			  Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
-			  AppAck : in  STD_LOGIC;
-           AppReq : in  STD_LOGIC;
-			  PortId : out  STD_LOGIC_VECTOR(3 downto 0);
-			  port_in_cmd_en : out  STD_LOGIC;
-			  port_in_wr_en : out  STD_LOGIC;
-			  port_in_empty : in  STD_LOGIC;
-           port_in_full : in  STD_LOGIC;
-           port_in_data : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           port_out_rd_en : out  STD_LOGIC;
-           port_out_data_available : in  STD_LOGIC);
-	END COMPONENT;
-	
-	COMPONENT EX0_FSM
-	PORT(	
-			clk : in  STD_LOGIC;
-         reset : in  STD_LOGIC;
-	
-			Initialized : in  STD_LOGIC;
-         Instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			instruction_en: in STD_LOGIC;
-         
-         ClkRate : in  STD_LOGIC_VECTOR ;
-			uTimeResult : out  STD_LOGIC_VECTOR; 
-			TickResult : out STD_LOGIC_VECTOR
-			  );
-	END COMPONENT;
-
-
-COMPONENT MPI_CORE_SCHEDULER
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		priority_rotation : IN std_logic;
-		instruction_fifo_empty : IN std_logic;
-		instruction_fifo_rd_en : OUT std_logic;
-		instruction_fifo_data : IN std_logic_vector(Word-1 downto 0);
-		instruction_available : OUT std_logic;
-		
-		get_request_fifo_empty : IN std_logic;
-		get_request_fifo_rd_en : OUT std_logic;
-		get_request_fifo_data : IN std_logic_vector(Word-1 downto 0);
-		
-		fifo_rd_en : IN std_logic;          
-		fifo_empty : OUT std_logic;
-		fifo_selected : OUT std_logic;
-		
-		data_out : OUT std_logic_vector(Word-1 downto 0)
-		
-		
-		);
-	END COMPONENT;
-	
--- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic;  -- indique l'un des deux fifos d'instructions qui sont prêts
-signal fifo_instr : std_logic;  -- une instruction est prête dans les fifos d'instruction
-
-
-signal scheduler_fifo_empty : std_logic;
-signal scheduler_data_out : std_logic_vector(Word-1 downto 0);
-signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0);
-
-signal scheduler_priority_rotation : std_logic;
-signal scheduler_rd_en : std_logic;
-
-signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états
-signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0);  -- ces bus doivent être gérés en logique 3 états!
-signal dma_rd_address3 : std_logic_vector(15 downto 0);
-signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0);
-signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0);
-signal dma_wr_address : std_logic_vector(15 downto 0);
-signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0);
-signal ram_data_out_signal : std_logic_vector(Word-1 downto 0);
-signal weram,rdram,ram_wev,ram_env :std_logic:='0';
-
-signal i_fifo2_signal : std_logic_vector(Word-1 downto 0);
-signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI
-signal Res4_en:std_logic;--acquittement du réusltat du module n°4
-signal Ex4_en,Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic:='0'; -- indique la fin de l'exécution de la MAE
-signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic:='0' ; -- validation lecture des données en RAM
-signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic :='0'; -- validation écriture des données en RAM
-signal Exi_busy : std_logic:='0';
-signal Ex1_Result,Ex2_Result,Ex4_result : std_logic_vector(Word-1 downto 0);
-signal Instr_in :  STD_LOGIC_VECTOR (Word-1 downto 0);
---================interface DMA avec les modules ======================================
-signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4   : std_logic_vector(Word-1 downto 0);
-signal dma_data_out : std_logic_vector(Word-1 downto 0);
-signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0');
-signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0');
-signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1);
---
---======================================================================================
---connexion au switch
-
-signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc
-
---================================================================
---déclaration des signaux d'état du Core
-signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic;
-signal InitReq,InitReq1,InitReq2   :std_logic:='0'; -- demande d'initialisation
-signal InitAck,IAck,Ilatch : std_logic:='0';
-signal MPISize,MyRank : std_logic_vector(3 downto 0);
-signal LibState: std_logic_vector(Word-1 downto 0):=(others=>'0'); --ready,receiving,sending,spawning,rwaiting,swaiting,...
-signal NocSize :std_logic_vector(3 downto 0):=(others=>'0');
-Signal PortId : std_logic_vector(3 downto 0);
-Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz
-signal uTimeCount :std_logic_vector(31 downto 0):=(others=>'0');
-signal TickCount : std_logic_vector(31 downto 0):=(others=>'0');
-signal RankSize: std_logic_vector(Word-1 downto 0):=(others=>'0');
---========================================================
---déclaration des signaux permettant d'activer le module
-signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0);
---========================================================
---signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi
---========================================================
---connexion avec les FIFO instructions
-signal fifo1_wr : std_logic;
-signal fifo1_din : std_logic_vector (Word-1 downto 0);
-signal fifo_sel : std_logic;   --permet d'arbitrer la priorité de lecture entre les deux fifos
-signal i_fifo1_rd_en : std_logic;
-signal fifo1_full : std_logic;
-signal i_fifo1_empty : std_logic;
-signal i_fifo1_data_out : std_logic_vector(Word-1 downto 0);
-signal i_fifo2_rd_en : std_logic;
-signal i_fifo2_data_out : std_logic_vector(Word-1 downto 0);
-signal i_fifo2_data_in : std_logic_vector(Word-1 downto 0);
-signal i_fifo2_wr_en : std_logic;
-signal i_fifo2_empty : std_logic;
-signal i_fifo2_full : std_logic;
-signal Ex2_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal Ex2_i_fifo2_wr_en : std_logic:='0';
---signaux pour les données entre modules
-signal Snd_Ack :std_logic;
-signal 		Rec_Rdy : std_logic;
-signal 		Rec_Data :  Typ_PortIO(0 to 3);
-signal 		Snd_data :  Typ_PortIO(0 to 3);
-signal 		Snd_Start :  std_logic;
-signal 		Rec_Ack :  std_logic; 
---signal i_fifo2_empty : std_logic;
---signal i_fifo2_full : std_logic;
-signal Ex4_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal Ex4_i_fifo2_wr_en : std_logic:='0';
---signal i_fifo2_empty : std_logic;
---signal i_fifo2_full : std_logic;
--- signaux pour la gestion des MAE
-signal n,n_i :natural range 0 to 7:=0;
-signal St_Ex1,St_Ex2,St_Ex4:natural range 0 to 7:=0;
-signal Next_St_Ex1,Next_St_Ex2,Next_St_Ex4:natural range 0 to 7:=0;
---===========================================================
-
-begin
---switch_port_in_data_signal <= ;
---switch_port_out_data_signal <= ;
--- istanciation des composants du core MPI
-Instruction_Fifo1: FIFO_64_FWFT PORT MAP(
-		clk =>clk,
-		din =>fifo1_din,
-		rd_en => i_fifo1_rd_en,
-		srst => reset,
-		wr_en => fifo1_wr,
-		dout =>i_fifo1_data_out,
-		empty => i_fifo1_empty,
-		full => fifo1_full
-	);
-
-Instruction_Fifo2: FIFO_64_FWFT PORT MAP(
-		clk =>clk,
-		din => i_fifo2_data_in ,
-		rd_en =>i_fifo2_rd_en,
-		srst =>reset,
-		wr_en =>i_fifo2_wr_en,
-		dout =>i_fifo2_data_out,
-		empty =>i_fifo2_empty,
-		full => i_fifo2_full 
-	);
-LD_instr:load_instr PORT MAP (
-
-			  Instruction =>Instruction,
-           Instruction_en =>Instruction_en,
-           clk =>clk,
-           reset =>reset,
-           dma_rd_grant =>dma_rd_grant(3),
-           dma_rd_request =>dma_rd_request(3), 
-			  copying=> Exi_busy,
-           instruction_ack =>iack,    --indique la fin de la copie d'une instruction dans le FIFO
-           fifo_din => fifo1_din,
-			  fifo_wr =>  fifo1_wr,
-           fifo_full =>fifo1_full,
-			  Ram_rd_en=> Exi_ram_rd,
-           ram_address_rd => dma_rd_address3,
-           ram_data =>dma_data_out    --sortie DMA
-);
-
-pushout(0)<=ILatch;
-pushout(1)<=IsMain;
-pushout(2)<=SizeSet;
-pushout(3)<=Ex4_result(6); --Spawn in progress on main
-pushout(4)<=Initialized;
-pushout(5)<=Ex1_result(1); --
-pushout(6)<=LibState(3); --Spawned child
-pushout(7)<=Ex4_result(7); --Spawn complete
-MPI_CORE_EX0_FSM: EX0_FSM PORT MAP(
-		instruction => i_fifo1_data_out,
-		instruction_en=> '1',
-		uTimeResult => uTimeCount,
-		TickResult => TickCount,
-		Initialized => Initialized,  -- indique si la l'appel à init a été concluant
-		ClkRate => uClkRate,
-		clk =>clk ,
-		reset => reset 
-	);
-MPI_CORE_EX1_FSM: EX1_FSM PORT MAP(
-		clk =>clk ,
-		reset =>reset,
-		pid => MyRank,  --port Id
-		nprocs=>MPISize,      -- à revoir dans certains cas ou tous les PEs ne sont pas connectés
-		fifo_empty => scheduler_fifo_empty ,
-		fifo_data_out =>scheduler_data_out,
-		fifo_rd_en =>scheduler_rd_en,
-		fifo_src =>fifo_sel,
-		priority_rotation => scheduler_priority_rotation,
-		
-		instruction_en=>Ex_en(1),  			 --active le module
-		Instruction => Instruction,
-		switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic
-		switch_port_in_data =>Noc1.port_in_data,
-		switch_port_in_wr_en =>Noc1.Port_in_wr_en ,
-		
-		Snd_Data =>Snd_Data,
-		Snd_Start =>Snd_start,
-		Snd_Ack =>Snd_ack,				          
-		Ram_rd => ex1_ram_rd,
-		Ram_wr =>ex1_ram_wr,
-		ram_data_in =>dma_data_out,
-		Ram_data_out =>dma_data_in1,
-		ram_address=>dma_wr_address1,
-		--ram_address =>dma_rd_address2,  --la même adresse sert pour la lecture ou l'écriture
-		dma_rd_request =>dma_rd_request(1),
-		dma_wr_request =>dma_wr_request(1),
-		dma_rd_grant =>dma_rd_grant(1) ,
-		dma_wr_grant =>dma_wr_grant(1) ,
-		
-		AppInitReq => InitReq1, -- requête d'initialisation de l'application
-		AppInitAck =>Res4_En  , -- Acquitement d'initialisation
-		Initialized=>Initialized,  -- état de la Lib
-		Result => Ex1_Result,     -- le résultat de l'exécution
-		Ready=> Ex1_Rdy
-	);
-instruction_fifo_full<=fifo1_full;
-dma_rd_address1<=dma_wr_address1;  --la même adresse sert pour la lecture ou l'écriture en RAM
-Exi_sync :process(reset,clk)
-
-begin
-  if rising_edge(clk) then
-    if reset='1' then
-     St_Ex2<=0;
-    St_Ex1<=0;
-    St_Ex4<=0; 
-    Ilatch<='0';
-    n<=0;
-  else
-    St_Ex2<=Next_St_Ex2;
-    St_Ex1<=Next_St_Ex1;
-    St_Ex4<=Next_St_Ex4;
-    ILatch<=Iack;
-    n<=n_i;
-  end if;
-end if;
-End process Exi_sync;
--- détermination de l'activation des module
---scheduler_priority_rotation<=not(Ex1_rdy);
-Ex1_Act:process(ST_Ex1,Initialized,fifo_instr,n,InitReq,Ex4_rdy,Ex1_rdy,Ex2_rdy)--A qoui sert encore ce processus (26/10/12) ????
-variable c_cyl:natural range 0 to 15:=0;
-begin
-  if reset='1' then
-      Next_St_ex1<=0;
-      c_cyl:=0;
-else -- cette machie à état permet de distinguer les activations de Ex4 et Ex1
-  case St_ex1 is
-  when 0 => if InitReq='1' and Initialized='0' then
-                Next_St_ex1<=1;
-         elsif Initialized='1' then 
-            Next_St_ex1 <=2;
-        elsif fifo_instr='1' then --cas d'une instruction directe qui est présente
-            --if fifo_sel='0' then
-                      Next_St_ex1 <=2;
-            --end if;
-        end if;
-         
-  when 1 => if Ex4_Rdy='1' then
-                Next_St_ex1<=4;
-        end if;
-  when 2 => if Ex1_rdy='0' then  --ex1 est libre et actif
-                      Next_St_ex1<=3;
-               end if;
-    
-  when 3 => if Ex1_rdy='1'  and Initialized='0'then --ex1 est occupé et actif
-                Next_St_ex1<=0;
-            elsif Ex1_rdy='1'  and Initialized='1' then
-                Next_St_ex1<=2;
-            end if;
-             
-  when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau
-            --compter quelques cycles d'horloges pour attendre initreq2
-            if n=4 then
-                  Next_St_ex1<=0;
-              n_i<=0;
-            else
-              n_i<=n+1;
-            end if;
-          else
-            Next_St_ex1<=0;
-          end if;
-    
-  when others =>    
-              Next_St_ex1<=0;
-  end case;
-end if;
-end process ex1_Act;
-
-ex1_v:process(St_Ex1)
-  begin
-    case St_Ex1 is 
-  when 0 =>
-                  Ex_en(1)<='0';
-  when 1 =>
-                  Ex_en(1)<='0';
-  when 2|3 =>
-             Ex_en(1)<='1';
-  when others =>
-            Ex_en(1)<='0';
-  end case;
-  
-end process ex1_v;
-
-Ex2_nextState:Process(reset,st_Ex2, Ex4_rdy,Initialized,Ex2_Result,Ex2_rdy) --active la réception lorsqu' Put ou un Get ou un Init a été effectué
-begin
-Next_St_Ex2<=st_Ex2;
-Case st_Ex2 is
-
-when 0 =>    
-	if Initialized='1' and Ex4_rdy='1' then --- Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then
-		  Next_St_Ex2<=1; --active la réception des mesages sur le noeud.
-		
-	else
-	    Next_St_Ex2<=0;
-	end if;
-When 1 =>
-    if Ex2_rdy='0' then
-      Next_St_Ex2<=2;
-  end if;
-When 2 =>
-    if Ex2_rdy='1' then
-      Next_St_Ex2<=0;
-  end if;
-when others =>
-	 Next_St_Ex2<=0;
-	end case;
-end process;
-Ex2_val:Process(st_Ex2,Ex4_result) --
-
-begin  
-Case st_Ex2 is
-
-when 0 =>    						
-Ex_en(2)<='0';
---LibState(3)<='0';
-when 1|2 =>
-  Ex_en(2) <='1';
-when 3|4|5|6|7 =>
-  Ex_en(2)<='0';
-when others=>
-  Ex_en(2)<='0';
-end case;
-	if rising_edge(Ex4_result(1)) then
-		LibState(3)<='1'; --spawn a été détecté.
-	end if;			
-end process;
-
-Ex_en_proc:process (clk,reset)
-begin
-				if rising_edge(clk) then
-				 if reset='1' then
-					   Ex4_en<='0';
-				 else
-					
-						if Ex_en(4)='1'  then
-						  		Ex4_en<='1'; --synchro
-						else
-						    Ex4_en<='0'; --synchro
-						end if;
-					end if;
-				end if;		  
-end process;
-Ex4_Active:process (St_Ex4,initreq1,initreq2,Ex1_rdy,Initialized,Res4_en)
-begin
-				
-case St_Ex4 is
-		when		0 => 
-						if (InitReq1='1') then
-						    Next_St_Ex4<=1;
-						 elsif InitReq2='1'  then --le module 1 n'est pas actif
-						    Next_St_Ex4<=2;
-						 else
-						    Next_St_Ex4<=0;
-						end if;
-			when 1 =>
-						If Res4_en='1'  then --fin de l'exécution du module
-							Next_St_Ex4<=3;
-						end if;
-			when 2 =>
-						if Res4_en='1'  then --Ex2_result(0)='1'
-							Next_St_Ex4<=4;
-						end if;
-			when 3 =>
-					  if initreq1='0' then
-  						  Next_St_Ex4<=5;
-						end if;
-			when 4 =>
-					  if initreq2='0' then
-  						  Next_St_Ex4<=5;
-						end if;
-			when 5 =>
-						Next_St_Ex4<=0;
-			when others =>
-      			  Next_St_Ex4<=0;
-			end case;
-					
-end process Ex4_active;
-
-Ex4_active_val:process (st_Ex4)
-begin
- case St_Ex4 is
-	when 0 =>
-		AppReq<='0';
-		InitReq<='0';Ex_en(4)<='0';
-		AppAck<='0';
-	when 1 =>
-		AppReq<='1';
-		InitReq<='1'; 
-		Ex_en(4)<='1';
-		AppAck<='0';
-	when 2 =>
-		AppReq<='1';
-		InitReq<='1';
-		Ex_en(4)<='1';
-		AppAck<='0';
-	when 3 =>
-		AppReq<='0';
-		InitReq<='0';
-		Ex_en(4)<='0';
-		AppAck<='1';
-	when 4 =>
-		AppReq<='0';
-		InitReq<='0';
-		Ex_en(4)<='0';
-		AppAck<='1';
-	when 5 =>
-		AppReq<='0';
-		InitReq<='0';Ex_en(4)<='0';
-		AppAck<='1';
-	when others =>
-	  AppReq<='0';
-		InitReq<='0';
-		AppAck<='0';
-		Ex_en(4)<='0';
- end case ;
--- Appreq<=Ex_en(4);  --signal d'activation de la MAE Init
---InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation
---AppAck<=Ex1_result(0) or Ex2_result(0); -- signal init completed
-end process Ex4_active_val;
---Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ???
-Ex_en(3)<='0';
---Ex_en(4)<= '1' when InitReq='1'  else '0';
-
--- soit une requête du PE soit une requête du Core
-
-
-MPI_CORE_EX2_FSM: EX2_FSM PORT MAP(
-		
-		clk =>clk,
-		reset =>reset,
-		instruction_en=>Ex_en(2),
-		Ready =>Ex2_rdy,      				--signale que le module est disponible
-		fifo_full =>i_fifo2_full,
-		
-		fifo_wr_en => Ex2_i_fifo2_wr_en,
-		fifo_data => Ex2_i_fifo2_data_in,
-		
-		switch_port_out_rd_en => Noc2.port_out_rd_en, 
-		switch_data_available =>Noc2.port_out_data_available,
-		switch_port_out_data =>Noc2.port_out_data ,
-		
-		 Rec_Rdy => Rec_Rdy,
-		 Rec_Data =>Rec_Data,
-		 Rec_Ack =>Rec_Ack,
-													-- il manque un signal pour valider l'accès à la RAM
-		dma_wr_request =>dma_wr_request(2),
-		dma_wr_grant =>dma_wr_grant(2),
-		dma_rd_request =>dma_rd_request(2),
-		dma_rd_grant =>dma_rd_grant(2),
-		ram_address =>dma_wr_address2,
-		Ram_rd => ex2_ram_rd,
-		Ram_wr =>ex2_ram_wr,
-		Ram_data_out=> Dma_data_out,
-		Ram_data_in => Dma_data_in2,
-		packet_received =>packet_received,
-		packet_ack => packet_ack,
-		barrier_completed =>barrier_completed,
-		AppRank =>MyRank,
-      AppSize =>MPISize,
-		AppInitReq => InitReq2, -- requête d'initialisation de l'application
-		AppInitAck =>Res4_En  , -- Acquitement d'initialisation
-		Initialized=>Initialized, 
-		Result => Ex2_Result     -- le résultat de l'exécution
-	);
-Dma_rd_address2<=Dma_wr_address2;	
-ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP(
-		instruction => x"00", --pas utiliser
-		ResOut => RankSize,
-		clk =>clk ,
-		IsMain=>IsMain,
-		reset => reset 
-	);
-MPI_CORE_EX4_FSM :EX4_FSM PORT MAP (
-			  Instruction => Instr_in,  --STD_LOGIC_VECTOR (Word-1 downto 0);
-           Instruction_En =>Ex4_en,  -- ='1' lorsque ce module est sollicité
-           clk  =>clk,
-           reset =>reset,
-           ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0);
-           Result_En =>Res4_En, -- ='1' lorsque fin de l'exécution du module
-           Ready => Ex4_Rdy,
-           NocSize =>NocSize,
-           AppRank =>MyRank,
-           AppSize =>MPISize,
-           IsMain =>IsMain,
-            Rec_Rdy => Rec_Rdy,
-		        Rec_Data =>Rec_Data,
-		        Rec_Ack =>Rec_Ack,
-            Snd_Ack =>Snd_ack,
-		        Snd_data =>Snd_data,
-		        Snd_Start =>Snd_Start,
-		     
-           I_fifo_full =>i_fifo2_full,
-		
-		      I_fifo_wr_en => Ex4_i_fifo2_wr_en,
-		      I_fifo_data_in => Ex4_i_fifo2_data_in,
-			  Initialized =>Initialized,
-			  Ram_data_out => Dma_data_out,
-           Ram_address =>dma_wr_Address4, 	--accès au stockage
-           Ram_wr =>Ex4_Ram_wr, 			--activation de l'écriture en RAM
-           Ram_data_in =>Dma_data_in4,	   --données à écrire en RAM
-			  DMA_rd_Request => dma_rd_request(4),
-			  DMA_rd_grant => dma_rd_grant(4),
-			  DMA_wr_Request => dma_wr_request(4),
-			  DMA_wr_grant => dma_wr_grant(4),
-           AppAck =>AppAck,
-           AppReq =>InitReq,
-			  PortId=>PortId,
-			  port_in_cmd_en => Noc3.port_in_cmd_en,
-			  port_in_wr_en =>Noc3.port_in_wr_en,
-			  port_in_empty =>Noc3.port_in_empty,
-           port_in_full =>Noc3.port_in_full,
-           port_in_data =>Noc3.port_in_data,
-			  port_out_data =>Noc3.port_out_data,
-           port_out_rd_en =>Noc3.port_out_rd_en,
-           port_out_data_available =>Noc3.port_out_data_available
-
-
-);
---=============Mux des signaux d'accès à la RAM=========
-ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement
-Ram_en<= '1' when (rdram ='1' or weram='1')  else '0'; -- les signaux qui vont vers la RAM 
-
- --dma_data_in <=dma_data_in1 or dma_data_in2;
- --dma_data_out <=dma_data_out1 or dma_data_out2;
- mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3,
-								ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd )
-begin
-   case dma_rd_grant is
-      when "0001" => dma_rd_address <= dma_rd_address1;
-							rdram<= ex1_ram_rd;
-      when "0010" => dma_rd_address <= dma_rd_address2;
-							rdram<= ex2_ram_rd;
-      when "0100" => dma_rd_address <= dma_rd_address3;
-							rdram<= exi_ram_rd;
---      when "1000" => dma_rd_address <= <input4>;
-      when others => dma_rd_address <= (others =>'0');
-							rdram<='0';
-   end case;
-end process;
- mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4,
-                    ex1_ram_wr,ex2_ram_wr,ex4_ram_wr)
-begin
-   case dma_wr_grant is
-      
-		when "0001" => dma_wr_address <= dma_wr_address1;
-							weram<=ex1_ram_wr ;
-							Dma_data_in<=Dma_data_in1;
-		when "0010" => dma_wr_address <= dma_wr_address2;
-							weram<=ex2_ram_wr ;
-							Dma_data_in<=Dma_data_in2;
-      when "1000" => dma_wr_address <= dma_wr_address4;
-							weram<=ex4_ram_wr;
-							Dma_data_in<=Dma_data_in4;
-      when others => dma_wr_address <= (others =>'0');
-							weram<='0';
-   end case;
-end process;
---======================================================
-
---=================Mux des signaux qui vont au switch============  
- clkout<=clk;   -- permettra le lien avec le module du switch 
-
- NOC1.port_out_data<=switch_port_out_data; 
- NOC1.port_out_data_available<=switch_port_out_data_vailaible;
- NOC1.port_in_empty<=switch_port_in_empty;
- NOC1.port_in_full<=switch_port_in_full;
- 
- NOC2.port_out_data<=switch_port_out_data; 
- NOC2.port_out_data_available<=switch_port_out_data_vailaible;
- NOC2.port_in_empty<=switch_port_in_empty;
- NOC2.port_in_full<=switch_port_in_full;
- 
- NOC3.port_out_data<=switch_port_out_data; 
- NOC3.port_out_data_available<=switch_port_out_data_vailaible;
- NOC3.port_in_empty<=switch_port_in_empty;
- NOC3.port_in_full<=switch_port_in_full;
- mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2,
- ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in,ex4_i_fifo2_data_in,ex4_i_fifo2_wr_en,
- instruction,ex2_result)
-
-begin
-     case Ex_en is 
-	  
-	  when"0001" =>
-			   switch_port_in_data <=Noc1.port_in_data;
-			   switch_port_out_rd_en<=NOC2.port_out_rd_en;
-			   switch_port_in_wr_en <=NOC1.port_in_wr_en;
-			   switch_port_in_cmd_en <='0';
-	  when "0010"|"0011" =>
-				switch_port_in_data <=Noc1.port_in_data;
-				switch_port_out_rd_en<=NOC2.port_out_rd_en;
-				switch_port_in_wr_en <=NOC1.port_in_wr_en;
-				switch_port_in_cmd_en <='0';
-				 i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
-		     i_fifo2_data_in<=ex2_i_fifo2_data_in;
-	 when"1011" => --ce cas pose problème car on ne sait ce qui se passe !!!
-			  if initreq2='1' then
-			    switch_port_in_data <=Noc1.port_in_data;
-			   switch_port_out_rd_en<=NOC3.port_out_rd_en;
-			   switch_port_in_wr_en <=NOC1.port_in_wr_en;
-			    switch_port_in_cmd_en <='0';
-			    else
-			   switch_port_in_data <=Noc1.port_in_data;
-			   switch_port_out_rd_en<=NOC2.port_out_rd_en;
-			   switch_port_in_wr_en <=NOC1.port_in_wr_en;
-			   switch_port_in_cmd_en <='0';
-			   end if;
-				i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
-		     i_fifo2_data_in<=ex2_i_fifo2_data_in;
-	  when "1001"  =>   --ca où un appel à init est effectué
-				if initialized='0' then
-				switch_port_in_data <=Noc3.port_in_data;
-				switch_port_out_rd_en<=NOC3.port_out_rd_en;
-				switch_port_in_wr_en <=NOC3.port_in_wr_en;
-				switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
-      else
-        switch_port_in_data <=Noc1.port_in_data;
-			   switch_port_out_rd_en<=NOC3.port_out_rd_en;
-			   switch_port_in_wr_en <=NOC1.port_in_wr_en;
-			 end if;
-				i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
-		     i_fifo2_data_in<=ex4_i_fifo2_data_in;
-	 when "1010"   =>   --ca où un appel à init est effectué
-				--switch_port_in_data <=Noc3.port_in_data;
---				switch_port_out_rd_en<=NOC3.port_out_rd_en;
---				switch_port_in_wr_en <=NOC3.port_in_wr_en;
---				switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
-        switch_port_in_data <=Noc1.port_in_data;
-			   switch_port_out_rd_en<=NOC3.port_out_rd_en;
-			   switch_port_in_wr_en <=NOC1.port_in_wr_en;
-				i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
-		    i_fifo2_data_in<=ex4_i_fifo2_data_in;
-	  when others => --permet de gérer le cas où un spawn arrive par le réseau
-			   switch_port_in_data <=Noc3.port_in_data;
-				switch_port_out_rd_en<=NOC3.port_out_rd_en;
-				switch_port_in_wr_en <=NOC3.port_in_wr_en;
-				switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
-
-				i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
-		     i_fifo2_data_in<=ex4_i_fifo2_data_in;
-		end  case;  
-				    		Instr_in <=Instruction ;
-		if initreq2='1' and Ex_en(4)='1' then
-		    		Instr_in <=Ex2_Result ;
-		  else
-		    		Instr_in <=Instruction ;
-		  end if;
-		  i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
-		     i_fifo2_data_in<=ex2_i_fifo2_data_in;
-	end process;
-
-
---===============================================================
-MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP(
-		clk =>clk,
-		reset =>reset,
-		
-		data_wr_mem => ram_data_in, --vers RAM
-		  
-		data_rd_mem => Ram_data_out, --- Vers RAM 
-		address_rd =>dma_rd_address,
-		address_wr =>dma_wr_address,
-		address_out_rd =>ram_address_rd,
-		address_out_wr =>ram_address_wr,
-		ram_en => ram_env,  --validation lecture
-		ram_we =>ram_wev,  --validation écriture
-		hold_req=>hold_req,--demande de bus à l'application
-		hold_ack=>hold_ack, -- libération du bus RAM par l'application
-		
-		data_rd_out => Dma_data_out, --vers périphérique
-		data_wr_in =>Dma_data_in,   --vers périphérique
-		dma_wr_grant =>dma_wr_grant,
-		dma_rd_request => dma_rd_request,
-		dma_rd_grant => dma_rd_grant,
-		dma_wr_request => dma_wr_request 
-	);
-	
-
-CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction 
-														-- qui sera exécutée par la MAE EX1
-		clk => clk,
-		reset => reset,
-		priority_rotation =>scheduler_priority_rotation,
-		instruction_fifo_empty =>i_fifo1_empty,
-		get_request_fifo_empty => i_fifo2_empty,
-		instruction_fifo_rd_en =>i_fifo1_rd_en,
-		get_request_fifo_rd_en =>i_fifo2_rd_en ,
-		instruction_fifo_data =>i_fifo1_data_out,
-		get_request_fifo_data =>i_fifo2_data_out,
-		fifo_selected =>fifo_sel,
-		instruction_available => fifo_instr,
-		fifo_empty => scheduler_fifo_empty,
-		fifo_rd_en =>scheduler_rd_en,
-		data_out => scheduler_data_out
-	);
-
-end structural;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/DEMUX1.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/DEMUX1.vhd	(revision 96)
+++ 	(revision )
@@ -1,54 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    09:35:09 06/13/2011 
--- Design Name: 
--- Module Name:    DEMUX1 - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity CDEMUX1 is
-    Port ( di : in  STD_LOGIC;
-           sel : in  STD_LOGIC;
-           do1 : out  STD_LOGIC;
-           do2 : out  STD_LOGIC);
-end CDEMUX1;
-
-architecture Behavioral of CDEMUX1 is
-
-begin
-
-demux_process : process(di, sel)
-begin
-  if sel = '0' then
-     do1 <= di;
-	  do2 <= '0';
-  else
-     do2 <= di;
-	  do1 <='0';
-  end if;
-end process;
-
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/DMA_ARBITER.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/DMA_ARBITER.vhd	(revision 96)
+++ 	(revision )
@@ -1,463 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: KIEGAING EMMANUEL
--- 			 GAMOM ROLAND CHRISTIAN
--- 
--- Create Date:    04:39:43 05/21/2011 
--- Design Name: 
--- Module Name:    DMA_ARBITER - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
--- gestionnaire DMA pour le port secodaire de la RAM true dual port des mémoire 
--- privée de chaque noeud
--- Dependencies: 
--- 
--- Revision: 09/07/2012
--- Revision 1.01 - File Created
--- Revision 1.2 - 19/03/2013 
--- Correction de bugs et optimisation du nombre de cycles
---	Création d'un testbench					
--- Additional Comments: Ce module pourra être optimisé pour générer les adresses automatiquement
--- par le controleur DMA lorsqu'il est sollicité par la périphérie
---
-----------------------------------------------------------------------------------
-library IEEE;
-library NocLib;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.numeric_std.all; 
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity DMA_ARBITER is
-    Port ( dma_rd_request : in  STD_LOGIC_VEctor (3 downto 0):=(others=>'0');
-           data_wr_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           data_rd_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           address_rd : in  STD_LOGIC_VECTOR (ADRLEN-1 downto 0); --adresse pour lecture
-           address_wr : in  STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse pour écriture
-           address_out_wr : out  STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse de sortie du DMA Arbiter
-			  address_out_rd : out  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           ram_en : out  STD_LOGIC; -- 
-           ram_we : out  STD_LOGIC;
-           data_wr_mem : out  STD_LOGIC_VECTOR (Word-1 downto 0); -- donnée en sortie écriture
-           data_rd_mem : in  STD_LOGIC_VECTOR (Word-1 downto 0); -- données en sortie lecture
-           dma_wr_grant : out  STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation d'écriture
-			  hold_req       : out STD_Logic;  --requete vers application
-			  hold_ack       : in  STD_Logic;  --autorisation par l'application
-			  clk           : in std_logic;
-			  reset		    : in std_logic;
-           dma_rd_grant : out  STD_LOGIC_vector(3 downto 0):=(others=>'0');  -- autorisation de lecture
-           dma_wr_request : in  STD_LOGIC_vector(3 downto 0):=(others=>'0')); -- demande de lecture
-end DMA_ARBITER;
-
-architecture Behavioral of DMA_ARBITER is
-type fsm_states is (idle,wait_ack,arbiter_ack, writing,ReadWrite,reading);-- definition du type etat pour le codage des etats des fsm
-signal dmac_state : fsm_states;
-
-signal prio_rd,prio_wr:std_logic_vector(3 downto 0);--vecteur de bits de priorité
-signal pri_rd,pri_wr : natural range 0 to 3; -- stocke le numéro du module qui a la priorité
-signal dma_rd_logic : std_logic_vector(3 downto 0):=(others=>'0');
-signal dma_wr_logic : std_logic_vector(3 downto 0):=(others=>'0');
-signal dma_rd_latch,dma_wr_latch: std_logic_vector(3 downto 0):=(others=>'0');
-signal dma_req_wr, dma_req_rd : std_logic;
-signal last_grant_rd,last_grant_wr : STD_LOGIC_vector(3 downto 0):=(others=>'0');
-signal tmp :std_logic_vector(3 downto 0):="0000";
-
-begin
---==========================================================================
----le MUX qui contrôle les adresses est géré à l'extérieur du contrôleur DMA
-dma_sync: process (clk,data_rd_mem,data_wr_in,address_rd,address_wr)
-begin
-data_rd_out<=data_rd_mem ;
-data_wr_mem <= data_wr_in;
-address_out_rd <= address_rd;
-address_out_wr <= address_wr;
-
-end process;
---dma_rd_grant<= dma_rd_logic;
---dma_wr_grant<= dma_wr_logic;
-dma_rd_grant<= dma_rd_latch;
-dma_wr_grant<= dma_wr_latch;
---==========================================================================
-
---Déterminer si une requête HOLD doit être émise vers l'application pour la libération du 
---bus mémoire
-tmp<=(others =>'0');
-
---for  i in 0 to 3 loop 
---dma_req_wr<=dma_req_wr or dma_wr_request(i);
---loop;
-
---for  i in 0 to 3 loop
--- dma_req_rd<=dma_req_rd or dma_rd_request(i);  -- construire le signal request vers l'extérieur
---loop;
-hold_req<='1' when dma_req_rd='1' or dma_req_wr='1' else '0'; --envoyer un Hold vers l'application
-
-
--- machine à etat du DMAC
-dmac_process : process(clk,reset)
---variable tmp : natural range 0 to 15;
-variable tmp_rd,tmp_wr: std_logic_vector(3 downto 0);
-variable  req_rd,req_wr : std_logic:='0' ;
-
-begin 
-	if rising_edge(clk) then 
-	 if reset = '1' then
-				dmac_state<= idle;
-				
-				prio_rd <="0001"; -- au debut priorité lecture au premier module
-				prio_wr <="0010"; -- au debut priorité ecriture au deuxième module
-				pri_rd<=0;--index de la priorité
-				pri_wr<=1;
-				req_rd:='0';
-				req_wr:='0';
-	  else 
-				if req_wr='0'  then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture
-				case dma_wr_request is
-				when "0001" => pri_wr<=0;
-									prio_wr<="0001";
-									req_wr:='1';
-									dma_req_wr<= '1';
-									dma_wr_logic <="0001";
-				when "0010" => pri_wr<=1;
-									prio_wr<="0010";
-									req_wr:='1';
-									dma_req_wr<= '1';
-									dma_wr_logic <="0010";
-				when "0100" => pri_wr<=2;
-									prio_wr<="0100";
-									req_wr:='1';
-									dma_req_wr<= '1';
-									dma_wr_logic <="0100";
-				when "1000" => pri_wr<=3;
-									prio_wr<="1000";
-									req_wr:='1';
-									dma_req_wr<= '1';
-									dma_wr_logic <="1000";
-									
-				when others => 
-									if req_rd='1' then --demande simultané de lecture et d'écriture
-									
-										if dma_rd_request(pri_rd)='1'  then
-												pri_wr<=pri_rd;
-												req_wr:='1';
-												for i in 0 to 3 loop
-												 if i=pri_rd then
-												  prio_wr(i)<='1';
-												  dma_wr_logic(i)<='1';
-												 else
-													prio_wr(i)<='0';
-												   dma_wr_logic(i)<='0';
-												 end if;
-												end loop;
-												
-												
-										end if;
-										
-									else --on affecte l'accè à la mémoire suivant le round robbin
-										tmp_wr:= (dma_wr_request and prio_wr) ;
-										dma_wr_logic <=tmp_wr;
-										
-										req_wr:= not(All_zeros(tmp_wr)); 
-										dma_req_wr<= not(All_zeros(tmp_wr)); 
-									end if;
-									-- la priorité est circulaire et décale à chaque coup d'horloge
-									if req_wr='0' then
-										prio_wr<=rol_vec(prio_wr); 
-										if pri_wr=3 then
-											pri_wr<=0;
-											Prio_wr<="0001";
-										else
-											pri_wr<=pri_wr+1;
-										end if;
-								 end if;
-				end case;
-				else   --req_wr='1'
-				
-				 --demande simultané de lecture et d'écriture
-									
-										if dma_rd_request(pri_wr)='1'  then
-												pri_rd<=pri_wr;
-												req_rd:='1';
-												prio_rd<=prio_wr;
---												for i in 0 to 3 loop
---												 if i=pri_rd then
---												  prio_wr(i)<='1';
---												  dma_wr_logic(i)<='1';
---												 else
---													prio_wr(i)<='0';
---												   dma_wr_logic(i)<='0';
---												 end if;
---												end loop;					
-												
-										end if;
-
-				end if;
-				
-				if req_rd='0'  then --tant que le Ctrl DMA est libre alors faire bouger la priorité
-				case dma_rd_request is
-				when "0001" => pri_rd<=0;
-									prio_rd<="0001";
-									req_rd:='1';
-									dma_req_rd<= '1';
-									dma_rd_logic<="0001";
-				when "0010" => pri_rd<=1;
-									prio_rd<="0010";
-									req_rd:='1';
-									dma_req_rd<= '1';
-									dma_rd_logic<="0010";
-									
-				when "0100" => pri_rd<=2;
-									prio_rd<="0100";
-									req_rd:='1';
-									dma_req_rd<= '1';
-									dma_rd_logic<="0100";
-									
-				when "1000" => pri_rd<=3;
-									prio_rd<="1000";
-									req_rd:='1';
-									dma_req_rd<= '1';
-									dma_rd_logic<="1000";
-									
-				when others => 
-									--si une demande survient de la part d'un composant déjà acquitté alors celui-ci est prioritaire
-									if req_wr='1' then
-									
-										if dma_rd_request(pri_wr)='1'  then
-												pri_rd<=pri_wr;
-												req_rd:='1';
-												for i in 0 to 3 loop
-												 if i=pri_wr then
-												  prio_rd(i)<='1';
-												  dma_rd_logic(i)<='1';
-												 else
-													prio_rd(i)<='0';
-												   dma_rd_logic(i)<='0';
-												 end if;
-												end loop;
-												
-												
-										end if;
-										
-									else
-										tmp_rd:= (dma_rd_request and prio_rd) ; 
-										dma_rd_logic<=tmp_rd;
-										dma_req_rd<= not (All_Zeros(tmp_rd));
-										req_rd:= not (All_Zeros(tmp_rd));
-									end if;
-								-- la priorité est circulaire et décale à chaque coup d'horloge
-									if req_rd='0' then
-										prio_rd<=rol_vec(prio_rd);
-										if pri_rd =3 then
-											pri_rd<=0;
-											prio_rd<="0001";
-										else
-											
-											pri_rd<=pri_rd+1;
-										end if;
-									end if;
-				end case;
-				
-			   end if;
-	   
-		  case dmac_state is
-		   when idle => if req_rd='1' or req_wr='1' then
-									dmac_state<=wait_ack; 
-							else -- initialiser la priorité
-									
-									
-									req_rd:='0';
-									dma_req_rd<= '0';
-									
-									
-									
-									req_wr:='0';
-									dma_req_wr<= '0';
-									
-									dma_wr_logic <="0000"; --aucun accès mémoire n'est accrédité
-									dma_rd_logic <="0000";
-											
-							end if;
-							
-			when wait_ack =>  -- l'application doit autoriser l'utilisation de la RAM par le Core
-						if dma_wr_request(pri_wr) ='1' or dma_rd_request(pri_rd) ='1' then
-							if hold_ack='1' then
-								--dmac_state<=arbiter_ack;
-								if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- 
-									dmac_state <= Readwrite;
-								 elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then
-											dmac_state <= Reading;
-								elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then
-											dmac_state <= Writing;
-								else
-											dmac_state<=Idle;
-								end if;
-							end if;
-						else
-							
-							if dma_wr_request(pri_wr) ='0' then
-							req_wr:='0';-- forcer une nouvelle recherche de priorité
-							end if;
-							
-							if dma_rd_request(pri_rd) ='0' then
-								req_rd:='0';
-							end if;
-							dmac_state<=Idle;
-						end if;
-						
-				
-			when arbiter_ack => 
---							if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- 
---									dmac_state <= Readwrite;
---								 elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then
---											dmac_state <= Reading;
---								elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then
---											dmac_state <= Writing;
---								else
-											dmac_state<=Idle;
---								end if;
-								-- cet état a été combiné au précédent pour gagner un cycle
-			when Writing => if dma_wr_request(pri_wr) ='1' then
-										if hold_ack='1' then 
-										    -- on reste dans cet état
-										 if dma_rd_request(pri_rd)='1' then
-												dmac_state<=ReadWrite;
-										 else
-												req_rd:='0';
-										 end if;
-										else
-											dmac_state<=wait_ack; 
-										end if;
-								 elsif dma_rd_request(pri_rd) ='1' then
-										dmac_state <= Reading;
-										req_wr:='0';
-								 else
-										dmac_state <= idle;
-										req_wr:='0';
-								end if;
-			
-			
-			when ReadWrite => if hold_ack='1' then
-										  if dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='1' then
-												dmac_state <= ReadWrite;
-											elsif dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='0' then 
-												dmac_state <= Writing;
-												req_rd:='0';
-											elsif dma_wr_request(pri_wr)='0' and dma_rd_request(pri_rd)='1' then
-												dmac_state <= Reading;
-												req_wr:='0';
-											else
-												dmac_state <= Idle;
-												req_rd:='0';req_wr:='0';
-											end if;
-									 else 
-											if (dma_wr_request(pri_wr)='1') or (dma_rd_request(pri_rd)='1') then
-													dmac_state <= Wait_ack;
-											else
-												dmac_state <= Idle;
-											end if;
-									end if;
-			when Reading => 
-								 if dma_rd_request(pri_rd) ='1' then
-										if hold_ack='1' then 
-										    -- on reste dans cet état
-											 if dma_wr_request(pri_wr)='1' then
-												dmac_state<=ReadWrite;
-											else
-												req_wr:='0';
-											end if;
-										else
-											dmac_state<=wait_ack; 
-										end if;
-								 elsif dma_wr_request(pri_wr) ='1' then
-										dmac_state<=writing;
-										req_rd:='0';
-								 else
-										dmac_state <= idle;
-										req_rd:='0';
-								end if;
-			when others => dmac_state <= idle;
-		   end case;
-	 end if;
-	end if;
-end process;
--- action_asociées
-ol: process(dmac_state, address_rd, address_wr,pri_wr,pri_rd,prio_wr,prio_rd,dma_wr_request,dma_rd_request)
-
-begin
---tester les requêtes DMA en lecture ou en écriture
-
-case dmac_state is
-		when idle => 
-							ram_en <='0';
-							ram_we <='0';
-							dma_wr_latch <=(others=>'0');
-							dma_rd_latch <=(others=>'0');
-							--address_out_rd <= address_rd;
-							--hold_req<='0';
-		when wait_ack =>
-							ram_en <='0';
-							ram_we <='0';
-							dma_wr_latch<=(others=>'0');
-							dma_rd_latch<=(others=>'0');
-							--address_out_rd <= (others=>'Z');
-							--address_out_wr <= (others=>'Z');
-							--hold_req<='1';
-		when arbiter_ack =>  --à optimiser pour gagner un cycle
-							ram_en <='0';
-							ram_we <='0';
-							dma_wr_latch<=(others=>'0');
-							dma_rd_latch<=(others=>'0');
-							--address_out_rd <= (others=>'Z');
-							--address_out_wr <= (others=>'Z');
-		when writing => -- ecriture dans la ram
-							ram_en <='1';
-							ram_we <='1';
-							dma_wr_latch<=(others=>'0');
-							dma_wr_latch(pri_wr) <='1';
-							dma_rd_latch <=(others=>'0');
-							--address_out_rd <= (others=>'Z');
-							--address_out_wr <= address_wr;
-							--hold_req<='1';							
-							
-		when ReadWrite => -- Lecture et écriture simultannée dans la Dual Port RAM
-							ram_en <='1';
-							ram_we <='1';
-							dma_wr_latch<=(others=>'0');
-							dma_wr_latch(pri_wr) <='1';
-							dma_rd_latch<=(others=>'0');
-							dma_rd_latch(pri_rd)<='1';
-							
-							--address_out_rd <= address_rd;
-							--address_out_wr <= address_wr;
-							--hold_req<='1';							
-		when Reading => -- lecture dans la ram
-							ram_en <='1';
-							ram_we <='0';
-							dma_wr_latch<=(others=>'0');
-							dma_rd_latch<=(others=>'0');
-							dma_rd_latch(pri_rd)<='1';
-							
-							--address_out_rd <= address_rd;
-							--address_out_wr <= (others=>'Z');
-							--hold_req<='1';
-		when others => 
-						   ram_en <='0';
-							ram_we <='0';
-							dma_wr_latch <=(others=>'0');
-							dma_rd_latch <=(others=>'0');
-							--address_out_rd <= (others=>'Z');
-							--address_out_wr <= (others=>'Z');
-							--hold_req<='0';
-		end case;
-end process;
-
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX1_FSM.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX1_FSM.vhd	(revision 96)
+++ 	(revision )
@@ -1,1319 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer:GAMOM /KIEGAING
--- 
--- Create Date:    08:12:29 06/16/2011 
--- Design Name: 
--- Module Name:    EX1_FSM - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: Ce module est chargé de recevoir les instructions du programme MPI et 
--- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC
--- (GET)
---
--- Dependencies: 
---
--- Revision: 09/07/2012
--- Revision 0.03 - File updated
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
---use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library NocLib ;
-use Work.Packet_type.ALL;
-USE ieee.numeric_std.ALL;
-
-
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX1_FSM is
-    -- parametres generiques du module : 
-				
-	     
-    Port ( 
-	        --instruction_available : in  STD_LOGIC;
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-        instruction : in std_logic_vector(Word-1 downto 0);   			  
-			  instruction_en : in std_logic:='0';  -- active le module instruction
-			   pid : in std_logic_vector(3 downto 0) ; -- id du processeur
-				nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1
-			  Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
-			  Ready : out std_logic; --indique la fin de l'éxécution d'une instruction
-			  AppInitReq :out  STD_LOGIC:='0'; -- requête d'initialisation de l'application
-			  AppInitAck :in  STD_LOGIC; -- Acquitement d'initialisation
-			  Initialized:in std_logic ; -- état de la Lib
-                                 -- Accès au Fifo d'instructions
-           priority_rotation : out  STD_LOGIC:='0';
-           fifo_rd_en : out  STD_LOGIC:='0';
-			  fifo_empty : in  STD_LOGIC;
-           fifo_data_out : in  STD_LOGIC_VECTOR (7 downto 0);
-			  fifo_src :      in STD_LOGIC; --permet de désigner le fifo qui est en service
-        
-		   
-		    Snd_Data : IN Typ_PortIO(0 to 3);
-		    Snd_Start : IN std_logic;
-		    Snd_Ack : OUT std_logic;
-		     
-												-- Accès au réseau sur puce
-			  switch_port_in_full : in std_logic;
-           switch_port_in_data : out  STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
-           switch_port_in_wr_en : out  STD_LOGIC:='0';
-			                               -- Accès à la mémoire RAM du PE
-			  ram_data_in : in std_logic_vector(7 downto 0);
-			  ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0');
-			  ram_rd,ram_wr : out std_logic:='0';
-			  ram_address : out std_logic_vector(15 downto 0):=(others=>'0');
-			  
-			  dma_wr_request : OUT std_logic:='0';
-				dma_rd_request : OUT std_logic:='0';
-				dma_wr_grant : in  STD_LOGIC;
-           dma_rd_grant : in  STD_LOGIC);
-end EX1_FSM;
-
-architecture Behavioral of EX1_FSM is
-
-component proto_send is
-generic (sizemem : natural := 64);
- port (
- clk,reset : in std_logic;
- fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée
- fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
- fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie
- fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée
- fifo_in_data_out : in std_logic_vector(Word-1 downto 0);
- fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
- packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
- copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
- snd_start : in std_logic; --début de la réception
- snd_ack :in std_logic;   -- acquittement de la réception
- snd_comp : out std_logic; -- fin de la réception
- mem :in memory(0 to sizemem-1)); --données à copier vers le fifo
-
-
-end component proto_send;
--- definition du type etat pour le codage des etats des fsm
-type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses,
- decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4,
- ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5,
- ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync);
--- machine a etat du module
-signal ex1_state,Next_Ex1_state : fsm_states;
-
--- les variables utilisées dans la fsm
-signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0';
-signal mem,mem_i : memory(0 to 3);
-signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0);
-signal packet_type,packet_type_i : std_logic_vector(3 downto 0);
---signal dpid : std_logic_vector(3 downto 0);
-signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0);
-signal p_len,p_len_i: std_logic_vector(Word-1 downto 0);
-signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0);
-signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0';
---signal res_address : std_logic_vector(15 downto 0);
-signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0);
-signal n,n_i : natural range 0 to 15;
-signal len,len_i : natural range 0 to 255;
-signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0';
-signal fifo_sel:std_logic:='0';
-signal run_init,run_init_i:std_logic:='0';
-begin
--- connection des signaux avec les ports
-ram_address <= src_address;
-result<=Result1;
-sw_send: proto_send generic map (sizemem=>4)
-	port map (
-	clk=>clk,
-	reset=>reset,
- fifo_in_empty=>fifo_empty, 
- fifo_in_full=>'0',--pas utilisé
- fifo_out_empty=>'0',
- packet_len=>p_len,
- copy_mode=>fifo_copy,
- fifo_out_full => switch_port_in_full,
- fifo_in_rd_en=>fifo_rd,
- fifo_in_data_out=>fifo_data_out,
-fifo_out_wr_en =>fifo_wr,
-
- fifo_out_data_in =>noc_fifo_in,
- snd_start =>snd_start_sync,
- snd_ack =>snd_ack1,
- snd_comp=>snd_comp,
- mem =>mem
-	);
-ex1_fsm_sync:process(clk)
- 
- begin
-   if rising_edge(clk) then
-	if reset = '1' then
-	ex1_state <= fifo_select;
-	n<=0;
-	len<=0;
-	p_len<=(others=>'0');
-	snd_ack<='0';
-	src_address<=(others=>'0');
-	dest_address<=(others=>'0');
-	run_init<='0';
-	else
-	  ex1_state<=next_ex1_state;
-	  n<=n_i;
-	  len<=len_i;
-	  p_len<=p_len_i;
-	  dest_address<=dest_address_i;
-	  Packet_type<=Packet_type_i;
-	  Pid_counter<=Pid_counter_i;
-	  Data_to_send<=Data_to_send_i;
-	  Result1<=Result_i;
-	  run_init<=Run_init_i;
-	  for i in 0 to 3 loop
-		mem(i)<=mem_i(i);
-		end loop;
-	  src_address <= src_address_i;
-	  snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4
-    snd_start_sync<=snd_start1;
-	 end if;
-	end if;
- end process ex1_fsm_sync;
--- processus de transistion entre les etats 
-fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, 
- pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address,
- fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send)
-variable tempval : std_logic_vector(Word-1 downto 0);
-variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé
-begin
-     snd_ack1<='0';
-	  fifo_copy<='0';
-	  snd_start1<='0';
-	  n_i<=n; --valeur par défaut
-     Next_ex1_state <=Ex1_state;
-	  Src_address_i<=src_address;
-	  dest_address_i<=dest_address;
-	  P_len_i<=P_len;
-	  Packet_type_i<=Packet_type;
-	  Pid_counter_i<=Pid_counter;
-	  run_init_i<=Run_init;
-	  Len_i<=Len;
-	  Data_to_send_i<=Data_to_send;
-	  dma_rd<='0'; --attention ceci peut changer le code
-	  dma_wr<='0'; --il faut donc le vérifier
-	  for i in 0 to 3 loop
-		mem_i(i)<=mem(i);
-		end loop;
-		  case ex1_state is
-			 when fifo_select => if instruction_en='1' and fifo_empty  ='0' then 								
-											Next_ex1_state  <= fetch_packet_type;
-									   else
-											Next_ex1_state <= fifo_select;
-								      end if;
-										rd_ok<='0';
-										wr_ok<='0';
-										if instruction_en='1' and snd_start='1' then
-										    run_init_i<='1';
-										    Next_ex1_state<=ex1_init_run;
-										else
-										    run_init_i<='0';
-										end if;
-										--lecture du registre status de la mib MPI
-			 when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put
-										   Next_ex1_state <= read_status2;
-										  else
-											Next_ex1_state <= read_status1;
-								      end if;
-										src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
-			when read_status2 =>
-										 Next_ex1_state <= fifo_select;
-			when fetch_packet_type => rd_ok<='0';
-			             if fifo_empty ='1' then
-										Next_ex1_state <= fifo_select;
-									 else
-									   packet_type_i <= fifo_data_out(7 downto 4);
-										data_to_send_i <= fifo_data_out;
-										Next_ex1_state <= decode_packet_type;
-										rd_ok<='1';
-							      end if;
-			when decode_packet_type => rd_ok<='0';
-			                 if fifo_empty='0' then
-												 if packet_type = MPI_PUT then
-												    p_len_i <= fifo_data_out + 4; 
-													 n_i <= 0;rd_ok<='1';
-													 Next_ex1_state <= fetch_addresses;
-												  elsif packet_type = MPI_GET then
-												    len_i <= to_integer(unsigned(fifo_data_out));
-												    p_len_i <= fifo_data_out;
-													 n_i <= 0;	 rd_ok<='1';
-												    Next_ex1_state <= fetch_addresses;
-												  elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
-												    p_len_i <= "00000011"; --  = 3
-													 pid_counter_i <= "0000";
-													 rd_ok<='1';
-													 Next_ex1_state <= ex1_barrier1;
-													elsif packet_type = MPI_INIT then
-														Next_ex1_state<=ex1_init1;
-														len_i <= to_integer(unsigned(fifo_data_out));
-													   p_len_i<=fifo_data_out;
-														n_i<=0;rd_ok<='1';
-													elsif packet_type = MPI_ACK then
-												    len_i <= to_integer(unsigned(fifo_data_out));
-												    p_len_i<=fifo_data_out;
-													 n_i <= 0;	 rd_ok<='0';
-												    Next_ex1_state <= ex1_send_Ack;
-												  elsif packet_type = MPI_WIN_SYNC then
-												    len_i <= to_integer(unsigned(fifo_data_out));
-												    p_len_i<=fifo_data_out;
-													 n_i <= 0;	 rd_ok<='0';
-												    Next_ex1_state <= ex1_WSynC;
-													elsif packet_type = MPI_SPAWN then
-														Next_ex1_state<=ex1_SPAWN;
-														len_i <= to_integer(unsigned(fifo_data_out));						
-														p_len_i<=fifo_data_out;
-														onepop:='1';--il y a une donnée lue
-														src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16));
-														rd_ok<='0';
-													 else -- packet non reconnu
-													   --synthesis translate_off
-													   report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ;
-													   --synthesis translate_on
-													   if fifo_empty = '1' then
-															Next_ex1_state <= fifo_select;
-														
-														else
-														  rd_ok<='1';
-															packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet
-															data_to_send_i <= fifo_data_out;
-															Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure
-														end if;
-											     end if;												  
-							             end if;        									
-         when fetch_addresses => n_i<=n;rd_ok<='1';
-                        if fifo_empty = '0' and n = 0 then
-												  src_address_i(15 downto 8) <= fifo_data_out;
-												  n_i <= n + 1;
-												  Next_ex1_state <= fetch_addresses;
-												elsif fifo_empty = '0' and n = 1 then
-												  src_address_i(7 downto 0) <= fifo_data_out;
-												  n_i <= n + 1;
-												  Next_ex1_state <= fetch_addresses;
-												elsif fifo_empty = '0' and n = 2 then
-												  dest_address_i(15 downto 8) <= fifo_data_out;
-												  n_i <= n + 1;
-												  Next_ex1_state <= fetch_addresses;
-												elsif fifo_empty = '0' and n = 3 then
-												  dest_address_i(7 downto 0) <= fifo_data_out;
-												  n_i <= n+1;
-												 elsif n=4 then
-												   rd_ok<='0';
-												   n_i<=0;
-												  Next_ex1_state <= decode_packet_type2;
-												 elsif fifo_empty='1' then
-												   rd_ok<='0';
-													Next_ex1_state <= fetch_addresses; --attendre les données manquantes
-												 else
-													 Next_ex1_state <= fifo_select;										
-												end if;		
-			when decode_packet_type2 => if packet_type = MPI_PUT  then
-												    Next_ex1_state <= ex1_put1;
-												   elsif packet_type = MPI_GET then 
-												    Next_ex1_state <= ex1_get1;										
-								             end if;	
-												 -- execution du mpi put
-			when ex1_put1 => if dma_rd_grant = '1' then
-										  Next_ex1_state <= ex1_put2;
-										 else
-										  Next_ex1_state <= ex1_put1;
-								      end if;	
-										Wr_ok<='0';
-			when ex1_put2 =>Wr_ok<='0';
-			              if switch_port_in_full = '0' and n = 0 then
-										  --envoie du code MPI_PUT
-										  n_i<= n + 1;
-										  wr_ok<='0';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and n = 1 then
-										  data_to_send_i <= p_len;
-										  n_i<= n + 1;
-										  wr_ok<='1';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and n = 2 then
-										  data_to_send_i <= dest_address(15 downto 8);
-										  n_i<= n + 1;
-										  wr_ok<='1';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and n = 3 then
-										  data_to_send_i <= dest_address(7 downto 0);
-										  n_i<= n +1;
-										  wr_ok<='1';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and  n = 4 then
-										  p_len_i <= p_len - 4;
-										 -- Next_ex1_state <= ex1_put3;
-										  Wr_ok<='0';
-										  n_i<=n+1;
-										 elsif n=5 and dma_rd_grant='1' then 
-										   Next_ex1_state <= ex1_put3;
-										   n_i<=0;
-										   Wr_ok<='1';
-										 else
-										  Next_ex1_state <= ex1_put2;										
-								     end if;								
-			when ex1_put3 => wr_ok<='0';
-			                 if unsigned(p_len)>0  then
-			                  --if n=0 then
---												  n_i<=1; --cycle d'attente pour la RAM
---												  Wr_ok<='0';
---												elsif n=1 then
-												if switch_port_in_full = '0'  then
-													   if n=1 then --creer un délai sur ces signaux par rapport à src_adress
-													     p_len_i <= p_len - 1;
-                                Wr_Ok<='1';
-                              end if;
-                          n_i<=1;
-													src_address_i <= src_address+1;
-													Next_ex1_state <= ex1_put3;
-													
-													
-												else
-													Wr_Ok<='0';
-													src_address_i <= src_address;
-													n_i<=0;
-												end if;
-												--elsif n=2 then
---												  n_i<=0; --cycle d'attente pour la RAM
---												  Wr_ok<='0';
---												 src_address_i <= src_address ; --prochaine lecture
---												
---												end if;
-										 else
-												Wr_Ok<='0';
-											Next_ex1_state <= ex1_put4;
-										end if;	
-			when ex1_put4 =>rd_ok<='1';
-			                 wr_ok<='0';
-			                if dma_rd_grant = '1' then -- fin du mpi_put
-										   Next_ex1_state <= ex1_put5;
-										   rd_ok<='0';
-											n_i<=0;
-											data_to_send_i<="00000001";
-										  else
-											Next_ex1_state <= ex1_put4;
-								      end if;
-										
-										if fifo_src='0' then --détection Put ou Get
-										    src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-										else
-	                     src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-                    end if;
-			when ex1_put5 =>  if n >0 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-										rd_ok<='0';wr_ok<='0';
-										if n=0 then
-										  
-										  n_i<=n+1;
-										 elsif n=1 then
-												if dma_rd_grant='1' then
-												n_i<=n+1;
-												
-												end if;
-												rd_ok<='1';
-												wr_ok<='0';
-												dma_wr<='1';										
-												dma_rd<='1';
-											elsif n=2 then
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													dma_wr<='1';
-													tempval:=Ram_data_in;
-													data_to_send_i<=ram_data_in;
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-																							
-													dma_rd<='1';
-											elsif n=3 then
-											  dma_rd<='1';
-												if dma_rd_grant='1' and dma_wr_grant='1' then
-													n_i<=n+1;
-													tempval:=Ram_data_in;
-													data_to_send_i<=ram_data_in;
-													--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-													tempval(5):='1';			-- SET du bit DSENT
-													data_to_send_i(5)<='1';
-													if fifo_src='0' then -- c'est un put qui est exécuté
-														tempval(5):='1';			-- SET du bit DSENT
-														--data_to_send_i<=ram_data_in or "00100000";
-													else  -- c'est un Get qui est exécuté
-														--tempval(2):='1';  -- ne pas annuler le sending après un GET
-														--data_to_send_i<=ram_data_in or "00000100";
-													end if;
-													--data_to_send_i<=tempval; --A tester
-													rd_ok<='0';
-													wr_ok<='1';
-													dma_wr<='1';										
-													dma_rd<='1';
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												dma_rd<='0'; --libérer le bus et revenir en arrière
-												dma_wr<='0';
-												n_i<=0;
-												end if;
-											elsif n=3 then
-												if dma_wr_grant = '1' and dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-												end if;
-													rd_ok<='0';
-													wr_ok<='1';
-													dma_wr<='1';										
-													dma_rd<='1';
-											elsif n=4 then
-												if dma_wr_grant = '1' and dma_rd_grant='1' then
-													n_i<=n+1;
-																								
-													src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16));
-                          data_to_send_i<="00000001";
-												end if;
-													rd_ok<='0';
-													wr_ok<='1';	
-													dma_wr<='1';										
-													dma_rd<='1';
-											elsif n=5 then
-													if dma_wr_grant = '1'  then
-														n_i<=n+1;
-														
-																-- SET du bit DSENT
-														data_to_send_i<="00000001";
-													end if;
-														rd_ok<='0';
-														wr_ok<='1';
-														dma_wr<='1';										
-														dma_rd<='0';
-											elsif n=6 then
-														n_i<=0;
-														Next_ex1_state <= fifo_select;
-														rd_ok<='0';
-														wr_ok<='0';
-														dma_wr<='0';										
-														dma_rd<='0';
-											end if;
-										 
-			
-			when ex1_get1 => 	wr_ok<='0';
-                  			  if switch_port_in_full = '0' and n = 0 then  -- execution du mpi get
-										      --écrire l'entête de la fonction
-											   n_i<= n + 1;
-											   Wr_ok<='0';
-											   Next_ex1_state <= ex1_get1;
-			                 elsif switch_port_in_full = '0' and n = 1 then  -- execution du mpi get
-										      data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ?
-											   n_i<= n + 1;
-											   Wr_ok<='1';
-											   Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 2 then
-											   data_to_send_i <= "0000"&pid; -- Rang source
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-											   Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 3 then
-											   data_to_send_i <= p_len;
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 4 then
-											   data_to_send_i <= src_address(15 downto 8);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 5 then
-											   data_to_send_i <= src_address(7 downto 0);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 6 then
-											   data_to_send_i <= dest_address(15 downto 8);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 7 then
-											   data_to_send_i <= dest_address(7 downto 0);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 8 then
-												Next_ex1_state <= ex1_get2;
-												n_i<=0;
-												Wr_ok<='1';
-												 else
-												  Next_ex1_state <= ex1_get1;
-								      end if;	
-			when ex1_get2 => if dma_wr_grant = '1'  then
-										  Next_ex1_state <= ex1_get3;
-										  src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
-										  data_to_send_i<="00000001";
-										else
-										  	Next_ex1_state <= ex1_get2;
-										 end if;
-										dma_wr<='1';
-			when ex1_send_ack |ex1_Wsync=>	rd_ok<='0';
-			                   if n = 0 then  -- execution du mpi ack /ou Mpi_Win_sync
-										      if switch_port_in_full = '0'   then
-												
-													wr_Ok<='0'; --envoie de la première donnée(code ack)
-													n_i<= n + 1;
-													onepop:='0';
-													 
-												end if;
-											elsif  n = 1  then
-												if  fifo_empty='0' and onepop='0' then
-														data_to_send_i <=p_len ;
-														
-															rd_Ok<='1'; --passe la longueur
-															onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
-															
-												else
-															rd_Ok<='0';
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:=not onepop;
-													n_i<= n + 1;
-													wr_ok<='1';
-												elsif (switch_port_in_full = '1') then
-														wr_Ok<='0';
-													
-												end if;
-											 
-											elsif  (n= 2)  then
-												if  fifo_empty='0' and onepop='0' then
-														
-														data_to_send_i <=fifo_data_out;
-															rd_Ok<='1';
-															onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
-															
-												else
-															rd_Ok<='0';
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:=not onepop;
-													n_i<= n + 1;
-													wr_ok<='1';
-												else
-														wr_Ok<='0';
-													
-												end if;
-											elsif  (n= 3)  then
-												if  fifo_empty='0' and onepop='0' then
-														
-														data_to_send_i <=fifo_data_out;
-															rd_Ok<='1';
-															onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
-															
-												else
-															rd_Ok<='0';
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:=not onepop;
-													n_i<= n + 1;
-													wr_ok<='1';
-												
-												else
-														wr_Ok<='0';
-													
-												end if;		
-											elsif  n = 4 then
-												n_i<=0;
-												Wr_Ok<='1';
-												rd_ok<='0';--vider le tampon
-											   Next_ex1_state <= fifo_select;
-											 
-											end if;
-									
-			when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie
-			                if dma_wr_grant = '1' then -- fin du post de mpi_get
-										   
-											n_i<=n+1;
-											data_to_send_i<="00000001";
-											wr_ok<='1';
-											rd_ok<='0'; 
-											end if;
-										
-											elsif n=2 then
-											  n_i<=0;
-											  Next_ex1_state <= ex1_get4;
-										   end if;
-										src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
-			when ex1_get4 => 	wr_ok<='0';
-			                   rd_ok<='0';
-			                   dma_wr<='1';										
-                         dma_rd<='1';
-                        src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-
-			                 if n=0 then
-											                       
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-													
-											elsif n=1 then
-												src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-
-											elsif n=2 then
-												if  dma_rd_grant='1'  then
-													n_i<=n+1;
-													rd_ok<='1';
-													src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-                        else
-                          n_i<=1;
-												end if;
-
-											elsif n=3 then
-													if  dma_rd_grant='1' and dma_wr_grant='1' then
-													   n_i<=n+1;
-													   tempval:=Ram_data_in;
-														data_to_send_i<=Ram_data_in;
-													   rd_ok<='1';
-													   wr_ok<='0';
-													   dma_wr<='1';										
-													   dma_rd<='1';
-													else 
-														    dma_wr<='0';										
-														    dma_rd<='0';
-														    n_i<=n-1;
-													end if;
-													src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-												elsif n=4 then
-													if dma_wr_grant = '1' and dma_rd_grant='1' then
-													n_i<=n+1;
-													rd_ok<='0';
-													wr_ok<='1';
-													tempval(6):='1';			--SET du bit Windows Busy --car réception Get
-													tempval(1):='1';			-- SET du bit DReceiving
-													data_to_send_i(6)<='1';
-													data_to_send_i(1)<='1';
-													--data_to_send_i<=tempval;  -- à tester absolument !!!
-													else
-													rd_ok<='0';
-													wr_ok<='1';
-													n_i<=1;
-													end if;
-													dma_wr<='1';										
-													dma_rd<='1';
-												elsif n=5 then
-												  wr_ok<='1'; 
-												  if dma_wr_grant = '1' then
-												  n_i<=n+1;
-												  end if;
-												elsif n=6 then
-												  n_i<=0;
-												Next_ex1_state <= fifo_select;
-												dma_wr<='0';										
-												dma_rd<='0';
-												end if;
-			
-			when ex1_spawn => 	rd_ok<='0';
-			                  if n = 0 then  -- execution du mpi spawn
-										      if switch_port_in_full = '0'   then
-												
-													wr_Ok<='0';
-													n_i<= n + 1;
-													onepop:='0';
-													--data_to_send_i<=len;
-												end if;
-											elsif  n = 1  then
-												if  fifo_empty='0' and onepop='0' then
-														data_to_send_i <=p_len ;
-														
-															rd_Ok<='1';
-															onepop:='1'; --une donnée lue il faut arrêter de dépiler
-												
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:='0';
-													n_i<= n + 1;
-													wr_ok<='1';
-												else
-														wr_Ok<='0';
-													
-												end if;
-											 
-											elsif  (n= 2) or (n=3) then
-												if  fifo_empty='0' and onepop='0' then
-														
-														data_to_send_i <=fifo_data_out;
-															rd_Ok<='1';
-															onepop:='1'; --une donnée lue il faut arrêter de dépiler
-
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:='0';
-													n_i<= n + 1;
-													wr_ok<='1';
-												else
-														wr_Ok<='0';
-													
-												end if;	
-											elsif n=4 then
-											  n_i<=0;
-												Wr_Ok<='1';
-												rd_ok<='0';
-											   Next_ex1_state <= fifo_select;
-											end if;
-								-- execution du barrier
-			when ex1_barrier1 => if switch_port_in_full = '0' then
-												 Next_ex1_state <= ex1_barrier2;	
-											  else
-											    Next_ex1_state <= ex1_barrier1;	
-											 end if;	
-			when ex1_barrier2 => if switch_port_in_full = '0' then
-												 Next_ex1_state <= ex1_barrier3;	
-											  else
-											    Next_ex1_state <= ex1_barrier2;	
-											 end if;	
-			when ex1_barrier3 => if switch_port_in_full = '0' then
-												 Next_ex1_state <= ex1_barrier4;	
-											  else
-											    Next_ex1_state <= ex1_barrier3;	
-											 end if;	
-			when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then
-												 pid_counter_i <= pid_counter + 1;
-												 Next_ex1_state <= ex1_barrier1;	
-											  else
-											    Next_ex1_state <= fifo_select;	
-											 end if;												
-			when ex1_init1 => rd_ok<='0';
-			               if n=0 then 
-			                 n_i<=n+1;
-			                 Len_i<=len-2; --deux données a été dépilée
-			               elsif n=1 then --vider le fifo instruction
-			                  if len>0 then
-			                    if  fifo_empty='0' then
-                                 rd_ok<='1';
-                                 Len_i<=len-1;
-                              
-                            else 
-                                rd_ok<='0';
-                                Len_i<=Len;
-                            end if;
-                      else
-                          n_i<=n+1;
-                     end if;                        			                    
-                    elsif n=2 then --
-                      n_i<=0;  
-                      rd_ok<='0';
-										  Next_ex1_state<=ex1_init_run;  
-			            
-										end if;
-									
-			when ex1_init_run=> if n=0 then
-			                       if snd_start='1' then --le module ex4 veut envoyer des données
-			                           
-			                               n_i<=n+1;
-			                            
-			                            for i in 0 to 3 loop 
-			                            mem_i(i)<=snd_data(i);
-			                             end loop;
-			                            if snd_data(0)(7 downto 4)=MPI_INIT or 
-			                                 snd_data(0)(7 downto 4)=MPI_SPAWN or
-			                                 snd_data(0)(7 downto 4)=MPI_ACK then
-			                             
-			                            else
-			                              report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !";
-			                            end if;
-			                            P_len_i<=x"04";
-			                             fifo_copy<='0';
-			                             snd_ack1<='0';
-	
-			                       end if;
-			                       if AppInitAck='1' then
-			                              Next_ex1_state<=ex1_init2;
-			                       end if;
-			                     elsif n=1 then
-			                       fifo_sel<='0';--pas de rotation du fifo instruction
-			                       snd_start1<='1';
-			                       P_len_i<=x"04";
-			                       fifo_copy<='0';
-			                       snd_ack1<='0';
-			                       		
-			                       n_i<=n+1;
-			                     elsif n=2 then
-											snd_start1<='1';
-			                       if snd_comp='1' then
-			                         snd_ack1<='1';
-			                         		                        
-			                         snd_start1<='0';
-			                         n_i<=n+1;
-			                       end if;
-			                     elsif n=3 then
-			                       snd_start1<='0';
-			                       snd_ack1<='1';
-			                       fifo_sel<='0';
-			                       if snd_start='0' then --attente l'annulation de l'envoie
-      			                       n_i<=0;
-      			                       snd_ack1<='0';
-      			                       if run_init='1' then
-      			                         Next_EX1_state<=fifo_select;
-      			                         --run_init<='0';
-  			                         end if;
-			                       end if;
-			                     end if;   
-			                        
-			                     
-			when ex1_init2 => 	-- écriture dans le registre  status reg.
-										src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
-			                         if n=0 then --envoie du message Spawn Ack sur le réseau
-			                               if instruction(6)='1' then  --Spawned=1 ? 
-			                                   n_i<=1; --envoie du message Spawn à main lib
-			                                   data_to_send_i<="01010000"; --init+spawn
-			                                else 
-			                                   n_i<=4; --écrire le résultat de la fn
-			                                   data_to_send_i<="00010000"; --init seul			                                   
-			                                end if;
-	
-										        	 elsif n=1 then
-          										        	      n_i<=n+1;
-									             			mem_i(0)<=MPI_INIT & x"0"; --répondre au premier
-										            		mem_i(1)<=x"04";
-										            		mem_i(2)<=x"00";
-										            		mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au 
-			                        elsif n=2 then
-											             	snd_start1<='1';
-													           n_i<=n+1;
-													           fifo_copy<='0';
-			                        elsif n=3 then
-																fifo_copy<='0';
-																snd_start1<='1';
-												          if snd_comp='1' then
-												              snd_ack1<='1';
-												              snd_start1<='0';
-																	n_i<=n+1;
-											           	end if;
-			                        elsif n=4 then --écriture du registre status
-			                             dma_wr<='1';
-			                             wr_ok<='1';
-			                          if dma_wr_grant = '1' then -- fin du mpi_init
-			                              n_i<=n+1;
-			                           end if;
-			                         elsif n=5 then
-			                             wr_ok<='1';
-												  dma_wr<='1';
-			                          if dma_wr_grant = '1' then -- fin du mpi_init
-			                              n_i<=n+1;
-			                           end if;
-			                        elsif n=6 then
-										                Next_ex1_state <= ex1_init3;
-  										                n_i<=0;
-										                wr_ok<='0';
-								              end if;   
-			                        			                           			         	                 
-			             		
-			when ex1_init3 =>--if AppInitAck='1' then
-										 Next_ex1_state <= fifo_select;
-										 --end if;
-			when ex1_ready => Next_ex1_state <= fifo_select;
-			when others => Next_ex1_state <= fifo_select;
-		   end case;
-   
- end process;
- 
- -- sortie de la machine à etat
- ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, 
- pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok,
- fifo_rd)
- variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0');
-  begin   
--- code fonctionnel	
-	Result_i<=Result1;
-	case ex1_state is
-		when fifo_select => priority_rotation <='1';  -- on peut changer la priorité
-								  fifo_rd_en <= '0';
-								  switch_port_in_data <= (others =>'0');
-								  switch_port_in_wr_en <= '0';
-								  dma_rd_request <= '0';
-								  dma_wr_request <= '0';
-								  Ram_rd<='0';
-								  Ram_wr<='0';
-								  Ram_data_out<=(others=>'0');
-								  AppInitReq<='0';
-								  Result_i <=(others=>'0');
-								  Ready<='1';
-		when read_status1 => priority_rotation <='0';
-									fifo_rd_en <= '0';
-								  switch_port_in_data <= (others =>'0');
-								  switch_port_in_wr_en <= '0';
-								  dma_rd_request <= '1';
-								  dma_wr_request <= '0';
-								  Ram_rd<='0';
-								  Ram_wr<='0';
-								  Ram_data_out<=(others=>'0');
-								  AppInitReq<='0';
-								  Result_i <=(others=>'0');
-								  Ready<='0';
-		when read_status2 => priority_rotation <='0';
-									fifo_rd_en <= '0';
-								  switch_port_in_data <= (others =>'0');
-								  switch_port_in_wr_en <= '0';
-								  dma_rd_request <= '1';
-								  dma_wr_request <= '0';
-								  Ram_rd<='1';
-								  Ram_wr<='0';
-								  Ram_data_out<=(others=>'0');
-								  AppInitReq<='0';
-								  status_reg:=Ram_data_in;
-								  Result_i <=(others=>'0');
-								  Ready<='0';
-		when fetch_packet_type => priority_rotation <='0';
-								  fifo_rd_en <= rd_ok;
-								  switch_port_in_data <= (others =>'0');
-								  AppInitReq<='0';
-								  switch_port_in_wr_en <= '0';
-								  Ram_rd<='0';
-								  Ram_wr<='0';
-								  dma_rd_request <= '0';
-								  dma_wr_request <= '0';
-								  Ram_data_out<=(others=>'0');
-								  Result_i <=(others=>'0');
-								  Ready<='0';
-		
-		when decode_packet_type => priority_rotation <='0';
-											fifo_rd_en <= rd_ok;
-											switch_port_in_data <= Data_To_Send;
-											switch_port_in_wr_en <= '0';
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_data_out<=(others=>'0');
-											Result_i <=(others=>'0');											
-                    		Ready<='0';
-		when fetch_addresses => priority_rotation <='0';
-										fifo_rd_en <= rd_ok;
-										switch_port_in_data <= (others =>'0');
-										switch_port_in_wr_en <= '0';
-										AppInitReq<='0';
-										Ram_rd<='0';
-										Ram_wr<='0';
-										dma_rd_request <= '0';
-										dma_wr_request <= '0';
-										Ram_data_out<=(others=>'0');
-										Result_i <=(others=>'0');
-		                Ready<='0';
-		when decode_packet_type2 =>priority_rotation <='0';
-								         fifo_rd_en <= '0';
-								         switch_port_in_data <= data_to_send;
-											switch_port_in_wr_en <= '0';
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_data_out<=(others=>'0');
-											Result_i <=(others=>'0');
-											Ready<='0'; -- fin du module
-		
-		when  ex1_barrier1 => priority_rotation <='0';
-										  fifo_rd_en <= '0';
-											switch_port_in_data <= packet_type & pid_counter;
-											switch_port_in_wr_en <= not(switch_port_in_full);
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_barrier2 =>  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-											switch_port_in_data <= p_len;
-											switch_port_in_wr_en <= not(switch_port_in_full);
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_data_out<=(others=>'0');	
-											Result_i <=(others=>'0');
-											Ready<='0'; -- fin du module									  
-										  
-		when ex1_barrier3 => priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= "0000" & pid;
-								        switch_port_in_wr_en <= not(switch_port_in_full);
-								        AppInitReq<='0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_barrier4 => priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= "0000" & pid;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_get1 =>      priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <= Wr_ok;
-								        AppInitReq<='0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		when ex1_get2 =>      priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <='0';
-								        AppInitReq<='0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= dma_Wr;
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										 Ready<='0'; -- fin du module
-										  
-			when ex1_get3 =>	  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= (others=>'0');---???
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '1';
-											Ram_rd<='0';
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; -- le résultat de l'exécution 
-											Ready<='0'; -- fin du module
-											Result_i <=(2=>'1',others=>'0');--Get completed
-		when ex1_get4 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_Data_in;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= dma_rd;
-										  dma_wr_request <= dma_wr;
-											Ram_rd<=rd_ok;
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; --"00000001";
-											Result_i <=(2=>'1',others=>'0'); --get completed
-											Ready<='0'; -- fin du module
-		when ex1_put1 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '1';
-										  dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											Result_i <=(others=>'0');
-											Ready<='0'; -- fin du module
-		
-		when ex1_put2 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        AppInitReq<='0';
-								        Ram_rd<='1';
-										Ram_wr<='0';
-								        dma_rd_request <= '1';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-										  
-		when ex1_put3 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_data_in;
-								        switch_port_in_wr_en <=  wr_ok;
-								        AppInitReq<='0';
-								        dma_rd_request <= '1';
-										  dma_wr_request <= '0';
-										  Ram_rd<='1';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_put4 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_data_in;---???
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= rd_ok;
-										  dma_wr_request <= wr_ok;
-											Ram_rd<=rd_ok;
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution 
-											--result(1)<='1'; 
-											Result_i <=(1=>'1',others=>'0');--put completed
-											Ready<='0'; -- fin du module
-		when ex1_put5 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_Data_in;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= dma_rd;
-										  dma_wr_request <= dma_wr;
-											Ram_rd<=rd_ok;
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; --"00000001";
-											Result_i <=(1=>'1',others=>'0'); --put completed
-											Ready<='0'; -- fin du module
-		when ex1_init1 =>    priority_rotation <='0';
-										  if fifo_empty='0' then
-										    fifo_rd_en <= rd_ok; 
-										  else
-										    fifo_rd_en<='0';
-										  end if;
-								        switch_port_in_data <=  data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='1';
-											Result_i <=(others=>'0');
-											Ready<='0';
-			when ex1_init_run =>    priority_rotation <='0';
-										  
-										    fifo_rd_en <= fifo_rd; 
-										  
-								        switch_port_in_data <=  noc_fifo_in;
-								        switch_port_in_wr_en <= fifo_wr;
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='1';
-											Result_i <=(others=>'0');
-											Ready<='0';											     
-											
-		when ex1_init2=>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= noc_fifo_in;
-								        switch_port_in_wr_en <= fifo_wr;
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '1';
-											Ram_rd<='0';
-											Ram_wr<=wr_ok;
-											Ram_data_out<=Data_to_send; -- le résultat de l'exécution 
-											Ready<='0';								  -- dans le registre status
-											Result_i <=(others=>'0');--
-		when ex1_init3=>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_Data_in;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '1';
-											Ram_rd<='0';
-											Ram_wr<='1';
-											Ram_data_out<="00010000";
-											Ready<='0'; -- fin du module
-											Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit
-		
-		when ex1_spawn =>		  priority_rotation <='0';
-										  fifo_rd_en <= rd_ok;
-								        switch_port_in_data <= Data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0';
-		when ex1_send_ack|ex1_Wsync =>		  priority_rotation <='0';
-										  fifo_rd_en <= rd_ok;
-								        switch_port_in_data <= Data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0';
-		when ex1_ready =>
-		  	                 Ready<='1'; -- fin du module
-		  	                 priority_rotation <='0';
-											fifo_rd_en <= '0';
-											switch_port_in_data <= (others =>'0');
-											switch_port_in_wr_en <= '0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='0';
-											Ready<='0';
-		  	                 
-		when others => 	        priority_rotation <='0';
-											fifo_rd_en <= '0';
-											switch_port_in_data <= (others =>'0');
-											switch_port_in_wr_en <= '0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='0';
-											Result_i <=(others=>'0');
-											Ready<='0';
-	end case;
-	
- end process;
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX1_FSM.vhd.bak
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX1_FSM.vhd.bak	(revision 96)
+++ 	(revision )
@@ -1,1319 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer:GAMOM /KIEGAING
--- 
--- Create Date:    08:12:29 06/16/2011 
--- Design Name: 
--- Module Name:    EX1_FSM - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: Ce module est chargé de recevoir les instructions du programme MPI et 
--- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC
--- (GET)
---
--- Dependencies: 
---
--- Revision: 09/07/2012
--- Revision 0.03 - File updated
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
---use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library NocLib ;
-use Work.Packet_type.ALL;
-USE ieee.numeric_std.ALL;
-
-
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX1_FSM is
-    -- parametres generiques du module : 
-				
-	     
-    Port ( 
-	        --instruction_available : in  STD_LOGIC;
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-        instruction : in std_logic_vector(Word-1 downto 0);   			  
-			  instruction_en : in std_logic:='0';  -- active le module instruction
-			   pid : in std_logic_vector(3 downto 0) ; -- id du processeur
-				nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1
-			  Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
-			  Ready : out std_logic; --indique la fin de l'éxécution d'une instruction
-			  AppInitReq :out  STD_LOGIC:='0'; -- requête d'initialisation de l'application
-			  AppInitAck :in  STD_LOGIC; -- Acquitement d'initialisation
-			  Initialized:in std_logic ; -- état de la Lib
-                                 -- Accès au Fifo d'instructions
-           priority_rotation : out  STD_LOGIC:='0';
-           fifo_rd_en : out  STD_LOGIC:='0';
-			  fifo_empty : in  STD_LOGIC;
-           fifo_data_out : in  STD_LOGIC_VECTOR (7 downto 0);
-			  fifo_src :      in STD_LOGIC; --permet de désigner le fifo qui est en service
-        
-		   
-		    Snd_Data : IN Typ_PortIO(0 to 3);
-		    Snd_Start : IN std_logic;
-		    Snd_Ack : OUT std_logic;
-		     
-												-- Accès au réseau sur puce
-			  switch_port_in_full : in std_logic;
-           switch_port_in_data : out  STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
-           switch_port_in_wr_en : out  STD_LOGIC:='0';
-			                               -- Accès à la mémoire RAM du PE
-			  ram_data_in : in std_logic_vector(7 downto 0);
-			  ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0');
-			  ram_rd,ram_wr : out std_logic:='0';
-			  ram_address : out std_logic_vector(15 downto 0):=(others=>'0');
-			  
-			  dma_wr_request : OUT std_logic:='0';
-				dma_rd_request : OUT std_logic:='0';
-				dma_wr_grant : in  STD_LOGIC;
-           dma_rd_grant : in  STD_LOGIC);
-end EX1_FSM;
-
-architecture Behavioral of EX1_FSM is
-
-component proto_send is
-generic (sizemem : natural := 64);
- port (
- clk,reset : in std_logic;
- fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée
- fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
- fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie
- fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée
- fifo_in_data_out : in std_logic_vector(Word-1 downto 0);
- fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
- packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
- copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
- snd_start : in std_logic; --début de la réception
- snd_ack :in std_logic;   -- acquittement de la réception
- snd_comp : out std_logic; -- fin de la réception
- mem :in memory(0 to sizemem-1)); --données à copier vers le fifo
-
-
-end component proto_send;
--- definition du type etat pour le codage des etats des fsm
-type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses,
- decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4,
- ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5,
- ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync);
--- machine a etat du module
-signal ex1_state,Next_Ex1_state : fsm_states;
-
--- les variables utilisées dans la fsm
-signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0';
-signal mem,mem_i : memory(0 to 3);
-signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0);
-signal packet_type,packet_type_i : std_logic_vector(3 downto 0);
---signal dpid : std_logic_vector(3 downto 0);
-signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0);
-signal p_len,p_len_i: std_logic_vector(Word-1 downto 0);
-signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0);
-signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0';
---signal res_address : std_logic_vector(15 downto 0);
-signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0);
-signal n,n_i : natural range 0 to 15;
-signal len,len_i : natural range 0 to 255;
-signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0';
-signal fifo_sel:std_logic:='0';
-signal run_init,run_init_i:std_logic:='0';
-begin
--- connection des signaux avec les ports
-ram_address <= src_address;
-result<=Result1;
-sw_send: proto_send generic map (sizemem=>4)
-	port map (
-	clk=>clk,
-	reset=>reset,
- fifo_in_empty=>fifo_empty, 
- fifo_in_full=>'0',--pas utilisé
- fifo_out_empty=>'0',
- packet_len=>p_len,
- copy_mode=>fifo_copy,
- fifo_out_full => switch_port_in_full,
- fifo_in_rd_en=>fifo_rd,
- fifo_in_data_out=>fifo_data_out,
-fifo_out_wr_en =>fifo_wr,
-
- fifo_out_data_in =>noc_fifo_in,
- snd_start =>snd_start_sync,
- snd_ack =>snd_ack1,
- snd_comp=>snd_comp,
- mem =>mem
-	);
-ex1_fsm_sync:process(clk)
- 
- begin
-   if rising_edge(clk) then
-	if reset = '1' then
-	ex1_state <= fifo_select;
-	n<=0;
-	len<=0;
-	p_len<=(others=>'0');
-	snd_ack<='0';
-	src_address<=(others=>'0');
-	dest_address<=(others=>'0');
-	run_init<='0';
-	else
-	  ex1_state<=next_ex1_state;
-	  n<=n_i;
-	  len<=len_i;
-	  p_len<=p_len_i;
-	  dest_address<=dest_address_i;
-	  Packet_type<=Packet_type_i;
-	  Pid_counter<=Pid_counter_i;
-	  Data_to_send<=Data_to_send_i;
-	  Result1<=Result_i;
-	  run_init<=Run_init_i;
-	  for i in 0 to 3 loop
-		mem(i)<=mem_i(i);
-		end loop;
-	  src_address <= src_address_i;
-	  snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4
-    snd_start_sync<=snd_start1;
-	 end if;
-	end if;
- end process ex1_fsm_sync;
--- processus de transistion entre les etats 
-fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, 
- pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address,
- fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send)
-variable tempval : std_logic_vector(Word-1 downto 0);
-variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé
-begin
-     snd_ack1<='0';
-	  fifo_copy<='0';
-	  snd_start1<='0';
-	  n_i<=n; --valeur par défaut
-     Next_ex1_state <=Ex1_state;
-	  Src_address_i<=src_address;
-	  dest_address_i<=dest_address;
-	  P_len_i<=P_len;
-	  Packet_type_i<=Packet_type;
-	  Pid_counter_i<=Pid_counter;
-	  run_init_i<=Run_init;
-	  Len_i<=Len;
-	  Data_to_send_i<=Data_to_send;
-	  dma_rd<='0'; --attention ceci peut changer le code
-	  dma_wr<='0'; --il faut donc le vérifier
-	  for i in 0 to 3 loop
-		mem_i(i)<=mem(i);
-		end loop;
-		  case ex1_state is
-			 when fifo_select => if instruction_en='1' and fifo_empty  ='0' then 								
-											Next_ex1_state  <= fetch_packet_type;
-									   else
-											Next_ex1_state <= fifo_select;
-								      end if;
-										rd_ok<='0';
-										wr_ok<='0';
-										if instruction_en='1' and snd_start='1' then
-										    run_init_i<='1';
-										    Next_ex1_state<=ex1_init_run;
-										else
-										    run_init_i<='0';
-										end if;
-										--lecture du registre status de la mib MPI
-			 when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put
-										   Next_ex1_state <= read_status2;
-										  else
-											Next_ex1_state <= read_status1;
-								      end if;
-										src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
-			when read_status2 =>
-										 Next_ex1_state <= fifo_select;
-			when fetch_packet_type => rd_ok<='0';
-			             if fifo_empty ='1' then
-										Next_ex1_state <= fifo_select;
-									 else
-									   packet_type_i <= fifo_data_out(7 downto 4);
-										data_to_send_i <= fifo_data_out;
-										Next_ex1_state <= decode_packet_type;
-										rd_ok<='1';
-							      end if;
-			when decode_packet_type => rd_ok<='0';
-			                 if fifo_empty='0' then
-												 if packet_type = MPI_PUT then
-												    p_len_i <= fifo_data_out + 4; 
-													 n_i <= 0;rd_ok<='1';
-													 Next_ex1_state <= fetch_addresses;
-												  elsif packet_type = MPI_GET then
-												    len_i <= to_integer(unsigned(fifo_data_out));
-												    p_len_i <= fifo_data_out;
-													 n_i <= 0;	 rd_ok<='1';
-												    Next_ex1_state <= fetch_addresses;
-												  elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
-												    p_len_i <= "00000011"; --  = 3
-													 pid_counter_i <= "0000";
-													 rd_ok<='1';
-													 Next_ex1_state <= ex1_barrier1;
-													elsif packet_type = MPI_INIT then
-														Next_ex1_state<=ex1_init1;
-														len_i <= to_integer(unsigned(fifo_data_out));
-													   p_len_i<=fifo_data_out;
-														n_i<=0;rd_ok<='1';
-													elsif packet_type = MPI_ACK then
-												    len_i <= to_integer(unsigned(fifo_data_out));
-												    p_len_i<=fifo_data_out;
-													 n_i <= 0;	 rd_ok<='0';
-												    Next_ex1_state <= ex1_send_Ack;
-												  elsif packet_type = MPI_WIN_SYNC then
-												    len_i <= to_integer(unsigned(fifo_data_out));
-												    p_len_i<=fifo_data_out;
-													 n_i <= 0;	 rd_ok<='0';
-												    Next_ex1_state <= ex1_WSynC;
-													elsif packet_type = MPI_SPAWN then
-														Next_ex1_state<=ex1_SPAWN;
-														len_i <= to_integer(unsigned(fifo_data_out));						
-														p_len_i<=fifo_data_out;
-														onepop:='1';--il y a une donnée lue
-														src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16));
-														rd_ok<='0';
-													 else -- packet non reconnu
-													   --synthesis translate_off
-													   report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ;
-													   --synthesis translate_on
-													   if fifo_empty = '1' then
-															Next_ex1_state <= fifo_select;
-														
-														else
-														  rd_ok<='1';
-															packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet
-															data_to_send_i <= fifo_data_out;
-															Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure
-														end if;
-											     end if;												  
-							             end if;        									
-         when fetch_addresses => n_i<=n;rd_ok<='1';
-                        if fifo_empty = '0' and n = 0 then
-												  src_address_i(15 downto 8) <= fifo_data_out;
-												  n_i <= n + 1;
-												  Next_ex1_state <= fetch_addresses;
-												elsif fifo_empty = '0' and n = 1 then
-												  src_address_i(7 downto 0) <= fifo_data_out;
-												  n_i <= n + 1;
-												  Next_ex1_state <= fetch_addresses;
-												elsif fifo_empty = '0' and n = 2 then
-												  dest_address_i(15 downto 8) <= fifo_data_out;
-												  n_i <= n + 1;
-												  Next_ex1_state <= fetch_addresses;
-												elsif fifo_empty = '0' and n = 3 then
-												  dest_address_i(7 downto 0) <= fifo_data_out;
-												  n_i <= n+1;
-												 elsif n=4 then
-												   rd_ok<='0';
-												   n_i<=0;
-												  Next_ex1_state <= decode_packet_type2;
-												 elsif fifo_empty='1' then
-												   rd_ok<='0';
-													Next_ex1_state <= fetch_addresses; --attendre les données manquantes
-												 else
-													 Next_ex1_state <= fifo_select;										
-												end if;		
-			when decode_packet_type2 => if packet_type = MPI_PUT  then
-												    Next_ex1_state <= ex1_put1;
-												   elsif packet_type = MPI_GET then 
-												    Next_ex1_state <= ex1_get1;										
-								             end if;	
-												 -- execution du mpi put
-			when ex1_put1 => if dma_rd_grant = '1' then
-										  Next_ex1_state <= ex1_put2;
-										 else
-										  Next_ex1_state <= ex1_put1;
-								      end if;	
-										Wr_ok<='0';
-			when ex1_put2 =>Wr_ok<='0';
-			              if switch_port_in_full = '0' and n = 0 then
-										  --envoie du code MPI_PUT
-										  n_i<= n + 1;
-										  wr_ok<='0';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and n = 1 then
-										  data_to_send_i <= p_len;
-										  n_i<= n + 1;
-										  wr_ok<='1';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and n = 2 then
-										  data_to_send_i <= dest_address(15 downto 8);
-										  n_i<= n + 1;
-										  wr_ok<='1';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and n = 3 then
-										  data_to_send_i <= dest_address(7 downto 0);
-										  n_i<= n +1;
-										  wr_ok<='1';
-										  Next_ex1_state <= ex1_put2;
-										elsif switch_port_in_full = '0' and  n = 4 then
-										  p_len_i <= p_len - 4;
-										 -- Next_ex1_state <= ex1_put3;
-										  Wr_ok<='0';
-										  n_i<=n+1;
-										 elsif n=5 and dma_rd_grant='1' then 
-										   Next_ex1_state <= ex1_put3;
-										   n_i<=0;
-										   Wr_ok<='1';
-										 else
-										  Next_ex1_state <= ex1_put2;										
-								     end if;								
-			when ex1_put3 => wr_ok<='0';
-			                 if unsigned(p_len)>0  then
-			                  --if n=0 then
---												  n_i<=1; --cycle d'attente pour la RAM
---												  Wr_ok<='0';
---												elsif n=1 then
-												if switch_port_in_full = '0'  then
-													   if n=1 then --creer un délai sur ces signaux par rapport à src_adress
-													     p_len_i <= p_len - 1;
-                                Wr_Ok<='1';
-                              end if;
-                          n_i<=1;
-													src_address_i <= src_address+1;
-													Next_ex1_state <= ex1_put3;
-													
-													
-												else
-													Wr_Ok<='0';
-													src_address_i <= src_address;
-													n_i<=0;
-												end if;
-												--elsif n=2 then
---												  n_i<=0; --cycle d'attente pour la RAM
---												  Wr_ok<='0';
---												 src_address_i <= src_address ; --prochaine lecture
---												
---												end if;
-										 else
-												Wr_Ok<='0';
-											Next_ex1_state <= ex1_put4;
-										end if;	
-			when ex1_put4 =>rd_ok<='1';
-			                 wr_ok<='0';
-			                if dma_rd_grant = '1' then -- fin du mpi_put
-										   Next_ex1_state <= ex1_put5;
-										   rd_ok<='0';
-											n_i<=0;
-											data_to_send_i<="00000001";
-										  else
-											Next_ex1_state <= ex1_put4;
-								      end if;
-										
-										if fifo_src='0' then --détection Put ou Get
-										    src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-										else
-	                     src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-                    end if;
-			when ex1_put5 =>  if n >0 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-										rd_ok<='0';wr_ok<='0';
-										if n=0 then
-										  
-										  n_i<=n+1;
-										 elsif n=1 then
-												if dma_rd_grant='1' then
-												n_i<=n+1;
-												
-												end if;
-												rd_ok<='1';
-												wr_ok<='0';
-												dma_wr<='1';										
-												dma_rd<='1';
-											elsif n=2 then
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													dma_wr<='1';
-													tempval:=Ram_data_in;
-													data_to_send_i<=ram_data_in;
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-																							
-													dma_rd<='1';
-											elsif n=3 then
-											  dma_rd<='1';
-												if dma_rd_grant='1' and dma_wr_grant='1' then
-													n_i<=n+1;
-													tempval:=Ram_data_in;
-													data_to_send_i<=ram_data_in;
-													--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-													tempval(5):='1';			-- SET du bit DSENT
-													data_to_send_i(5)<='1';
-													if fifo_src='0' then -- c'est un put qui est exécuté
-														tempval(5):='1';			-- SET du bit DSENT
-														--data_to_send_i<=ram_data_in or "00100000";
-													else  -- c'est un Get qui est exécuté
-														--tempval(2):='1';  -- ne pas annuler le sending après un GET
-														--data_to_send_i<=ram_data_in or "00000100";
-													end if;
-													--data_to_send_i<=tempval; --A tester
-													rd_ok<='0';
-													wr_ok<='1';
-													dma_wr<='1';										
-													dma_rd<='1';
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												dma_rd<='0'; --libérer le bus et revenir en arrière
-												dma_wr<='0';
-												n_i<=0;
-												end if;
-											elsif n=3 then
-												if dma_wr_grant = '1' and dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-												end if;
-													rd_ok<='0';
-													wr_ok<='1';
-													dma_wr<='1';										
-													dma_rd<='1';
-											elsif n=4 then
-												if dma_wr_grant = '1' and dma_rd_grant='1' then
-													n_i<=n+1;
-																								
-													src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16));
-
-												end if;
-													rd_ok<='0';
-													wr_ok<='1';	
-													dma_wr<='1';										
-													dma_rd<='1';
-											elsif n=5 then
-													if dma_wr_grant = '1'  then
-														n_i<=n+1;
-														
-																-- SET du bit DSENT
-														data_to_send_i<="00000001";
-													end if;
-														rd_ok<='0';
-														wr_ok<='1';
-														dma_wr<='1';										
-														dma_rd<='0';
-											elsif n=6 then
-														n_i<=0;
-														Next_ex1_state <= fifo_select;
-														rd_ok<='0';
-														wr_ok<='0';
-														dma_wr<='0';										
-														dma_rd<='0';
-											end if;
-										 
-			
-			when ex1_get1 => 	wr_ok<='0';
-                  			  if switch_port_in_full = '0' and n = 0 then  -- execution du mpi get
-										      --écrire l'entête de la fonction
-											   n_i<= n + 1;
-											   Wr_ok<='0';
-											   Next_ex1_state <= ex1_get1;
-			                 elsif switch_port_in_full = '0' and n = 1 then  -- execution du mpi get
-										      data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ?
-											   n_i<= n + 1;
-											   Wr_ok<='1';
-											   Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 2 then
-											   data_to_send_i <= "0000"&pid; -- Rang source
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-											   Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 3 then
-											   data_to_send_i <= p_len;
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 4 then
-											   data_to_send_i <= src_address(15 downto 8);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 5 then
-											   data_to_send_i <= src_address(7 downto 0);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 6 then
-											   data_to_send_i <= dest_address(15 downto 8);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 7 then
-											   data_to_send_i <= dest_address(7 downto 0);
-												n_i<= n + 1;
-											   Wr_ok<='1';												
-												Next_ex1_state <= ex1_get1;
-											 elsif switch_port_in_full = '0' and n = 8 then
-												Next_ex1_state <= ex1_get2;
-												n_i<=0;
-												Wr_ok<='1';
-												 else
-												  Next_ex1_state <= ex1_get1;
-								      end if;	
-			when ex1_get2 => if dma_wr_grant = '1'  then
-										  Next_ex1_state <= ex1_get3;
-										  src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
-										  data_to_send_i<="00000001";
-										else
-										  	Next_ex1_state <= ex1_get2;
-										 end if;
-										dma_wr<='1';
-			when ex1_send_ack |ex1_Wsync=>	rd_ok<='0';
-			                   if n = 0 then  -- execution du mpi ack /ou Mpi_Win_sync
-										      if switch_port_in_full = '0'   then
-												
-													wr_Ok<='0'; --envoie de la première donnée(code ack)
-													n_i<= n + 1;
-													onepop:='0';
-													 
-												end if;
-											elsif  n = 1  then
-												if  fifo_empty='0' and onepop='0' then
-														data_to_send_i <=p_len ;
-														
-															rd_Ok<='1'; --passe la longueur
-															onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
-															
-												else
-															rd_Ok<='0';
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:=not onepop;
-													n_i<= n + 1;
-													wr_ok<='1';
-												elsif (switch_port_in_full = '1') then
-														wr_Ok<='0';
-													
-												end if;
-											 
-											elsif  (n= 2)  then
-												if  fifo_empty='0' and onepop='0' then
-														
-														data_to_send_i <=fifo_data_out;
-															rd_Ok<='1';
-															onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
-															
-												else
-															rd_Ok<='0';
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:=not onepop;
-													n_i<= n + 1;
-													wr_ok<='1';
-												else
-														wr_Ok<='0';
-													
-												end if;
-											elsif  (n= 3)  then
-												if  fifo_empty='0' and onepop='0' then
-														
-														data_to_send_i <=fifo_data_out;
-															rd_Ok<='1';
-															onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
-															
-												else
-															rd_Ok<='0';
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:=not onepop;
-													n_i<= n + 1;
-													wr_ok<='1';
-												
-												else
-														wr_Ok<='0';
-													
-												end if;		
-											elsif  n = 4 then
-												n_i<=0;
-												Wr_Ok<='1';
-												rd_ok<='0';--vider le tampon
-											   Next_ex1_state <= fifo_select;
-											 
-											end if;
-									
-			when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie
-			                if dma_wr_grant = '1' then -- fin du post de mpi_get
-										   
-											n_i<=n+1;
-											data_to_send_i<="00000001";
-											wr_ok<='1';
-											rd_ok<='0'; 
-											end if;
-										
-											elsif n=2 then
-											  n_i<=0;
-											  Next_ex1_state <= ex1_get4;
-										   end if;
-										src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
-			when ex1_get4 => 	wr_ok<='0';
-			                   rd_ok<='0';
-			                   dma_wr<='1';										
-                         dma_rd<='1';
-                        src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-
-			                 if n=0 then
-											                       
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-													
-											elsif n=1 then
-												src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-
-											elsif n=2 then
-												if  dma_rd_grant='1'  then
-													n_i<=n+1;
-													rd_ok<='1';
-													src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-                        else
-                          n_i<=1;
-												end if;
-
-											elsif n=3 then
-													if  dma_rd_grant='1' and dma_wr_grant='1' then
-													   n_i<=n+1;
-													   tempval:=Ram_data_in;
-														data_to_send_i<=Ram_data_in;
-													   rd_ok<='1';
-													   wr_ok<='0';
-													   dma_wr<='1';										
-													   dma_rd<='1';
-													else 
-														    dma_wr<='0';										
-														    dma_rd<='0';
-														    n_i<=n-1;
-													end if;
-													src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-												elsif n=4 then
-													if dma_wr_grant = '1' and dma_rd_grant='1' then
-													n_i<=n+1;
-													rd_ok<='0';
-													wr_ok<='1';
-													tempval(6):='1';			--SET du bit Windows Busy --car réception Get
-													tempval(1):='1';			-- SET du bit DReceiving
-													data_to_send_i(6)<='1';
-													data_to_send_i(1)<='1';
-													--data_to_send_i<=tempval;  -- à tester absolument !!!
-													else
-													rd_ok<='0';
-													wr_ok<='1';
-													n_i<=1;
-													end if;
-													dma_wr<='1';										
-													dma_rd<='1';
-												elsif n=5 then
-												  wr_ok<='1'; 
-												  if dma_wr_grant = '1' then
-												  n_i<=n+1;
-												  end if;
-												elsif n=6 then
-												  n_i<=0;
-												Next_ex1_state <= fifo_select;
-												dma_wr<='0';										
-												dma_rd<='0';
-												end if;
-			
-			when ex1_spawn => 	rd_ok<='0';
-			                  if n = 0 then  -- execution du mpi spawn
-										      if switch_port_in_full = '0'   then
-												
-													wr_Ok<='0';
-													n_i<= n + 1;
-													onepop:='0';
-													--data_to_send_i<=len;
-												end if;
-											elsif  n = 1  then
-												if  fifo_empty='0' and onepop='0' then
-														data_to_send_i <=p_len ;
-														
-															rd_Ok<='1';
-															onepop:='1'; --une donnée lue il faut arrêter de dépiler
-												
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:='0';
-													n_i<= n + 1;
-													wr_ok<='1';
-												else
-														wr_Ok<='0';
-													
-												end if;
-											 
-											elsif  (n= 2) or (n=3) then
-												if  fifo_empty='0' and onepop='0' then
-														
-														data_to_send_i <=fifo_data_out;
-															rd_Ok<='1';
-															onepop:='1'; --une donnée lue il faut arrêter de dépiler
-
-												end if;
-
-											  if (switch_port_in_full = '0') and onepop='1'   then	 										wr_ok<='1';
-													onepop:='0';
-													n_i<= n + 1;
-													wr_ok<='1';
-												else
-														wr_Ok<='0';
-													
-												end if;	
-											elsif n=4 then
-											  n_i<=0;
-												Wr_Ok<='1';
-												rd_ok<='0';
-											   Next_ex1_state <= fifo_select;
-											end if;
-								-- execution du barrier
-			when ex1_barrier1 => if switch_port_in_full = '0' then
-												 Next_ex1_state <= ex1_barrier2;	
-											  else
-											    Next_ex1_state <= ex1_barrier1;	
-											 end if;	
-			when ex1_barrier2 => if switch_port_in_full = '0' then
-												 Next_ex1_state <= ex1_barrier3;	
-											  else
-											    Next_ex1_state <= ex1_barrier2;	
-											 end if;	
-			when ex1_barrier3 => if switch_port_in_full = '0' then
-												 Next_ex1_state <= ex1_barrier4;	
-											  else
-											    Next_ex1_state <= ex1_barrier3;	
-											 end if;	
-			when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then
-												 pid_counter_i <= pid_counter + 1;
-												 Next_ex1_state <= ex1_barrier1;	
-											  else
-											    Next_ex1_state <= fifo_select;	
-											 end if;												
-			when ex1_init1 => rd_ok<='0';
-			               if n=0 then 
-			                 n_i<=n+1;
-			                 Len_i<=len-2; --deux données a été dépilée
-			               elsif n=1 then --vider le fifo instruction
-			                  if len>0 then
-			                    if  fifo_empty='0' then
-                                 rd_ok<='1';
-                                 Len_i<=len-1;
-                              
-                            else 
-                                rd_ok<='0';
-                                Len_i<=Len;
-                            end if;
-                      else
-                          n_i<=n+1;
-                     end if;                        			                    
-                    elsif n=2 then --
-                      n_i<=0;  
-                      rd_ok<='0';
-										  Next_ex1_state<=ex1_init_run;  
-			            
-										end if;
-									
-			when ex1_init_run=> if n=0 then
-			                       if snd_start='1' then --le module ex4 veut envoyer des données
-			                           
-			                               n_i<=n+1;
-			                            
-			                            for i in 0 to 3 loop 
-			                            mem_i(i)<=snd_data(i);
-			                             end loop;
-			                            if snd_data(0)(7 downto 4)=MPI_INIT or 
-			                                 snd_data(0)(7 downto 4)=MPI_SPAWN or
-			                                 snd_data(0)(7 downto 4)=MPI_ACK then
-			                             
-			                            else
-			                              report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !";
-			                            end if;
-			                            P_len_i<=x"04";
-			                             fifo_copy<='0';
-			                             snd_ack1<='0';
-	
-			                       end if;
-			                       if AppInitAck='1' then
-			                              Next_ex1_state<=ex1_init2;
-			                       end if;
-			                     elsif n=1 then
-			                       fifo_sel<='0';--pas de rotation du fifo instruction
-			                       snd_start1<='1';
-			                       P_len_i<=x"04";
-			                       fifo_copy<='0';
-			                       snd_ack1<='0';
-			                       		
-			                       n_i<=n+1;
-			                     elsif n=2 then
-											snd_start1<='1';
-			                       if snd_comp='1' then
-			                         snd_ack1<='1';
-			                         		                        
-			                         snd_start1<='0';
-			                         n_i<=n+1;
-			                       end if;
-			                     elsif n=3 then
-			                       snd_start1<='0';
-			                       snd_ack1<='1';
-			                       fifo_sel<='0';
-			                       if snd_start='0' then --attente l'annulation de l'envoie
-      			                       n_i<=0;
-      			                       snd_ack1<='0';
-      			                       if run_init='1' then
-      			                         Next_EX1_state<=fifo_select;
-      			                         --run_init<='0';
-  			                         end if;
-			                       end if;
-			                     end if;   
-			                        
-			                     
-			when ex1_init2 => 	-- écriture dans le registre  status reg.
-										src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
-			                         if n=0 then --envoie du message Spawn Ack sur le réseau
-			                               if instruction(6)='1' then  --Spawned=1 ? 
-			                                   n_i<=1; --envoie du message Spawn à main lib
-			                                   data_to_send_i<="01010000"; --init+spawn
-			                                else 
-			                                   n_i<=4; --écrire le résultat de la fn
-			                                   data_to_send_i<="00010000"; --init seul			                                   
-			                                end if;
-	
-										        	 elsif n=1 then
-          										        	      n_i<=n+1;
-									             			mem_i(0)<=MPI_INIT & x"0"; --répondre au premier
-										            		mem_i(1)<=x"04";
-										            		mem_i(2)<=x"00";
-										            		mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au 
-			                        elsif n=2 then
-											             	snd_start1<='1';
-													           n_i<=n+1;
-													           fifo_copy<='0';
-			                        elsif n=3 then
-																fifo_copy<='0';
-																snd_start1<='1';
-												          if snd_comp='1' then
-												              snd_ack1<='1';
-												              snd_start1<='0';
-																	n_i<=n+1;
-											           	end if;
-			                        elsif n=4 then --écriture du registre status
-			                             dma_wr<='1';
-			                             wr_ok<='1';
-			                          if dma_wr_grant = '1' then -- fin du mpi_init
-			                              n_i<=n+1;
-			                           end if;
-			                         elsif n=5 then
-			                             wr_ok<='1';
-												  dma_wr<='1';
-			                          if dma_wr_grant = '1' then -- fin du mpi_init
-			                              n_i<=n+1;
-			                           end if;
-			                        elsif n=6 then
-										                Next_ex1_state <= ex1_init3;
-  										                n_i<=0;
-										                wr_ok<='0';
-								              end if;   
-			                        			                           			         	                 
-			             		
-			when ex1_init3 =>--if AppInitAck='1' then
-										 Next_ex1_state <= fifo_select;
-										 --end if;
-			when ex1_ready => Next_ex1_state <= fifo_select;
-			when others => Next_ex1_state <= fifo_select;
-		   end case;
-   
- end process;
- 
- -- sortie de la machine à etat
- ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, 
- pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok,
- fifo_rd)
- variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0');
-  begin   
--- code fonctionnel	
-	Result_i<=Result1;
-	case ex1_state is
-		when fifo_select => priority_rotation <='1';  -- on peut changer la priorité
-								  fifo_rd_en <= '0';
-								  switch_port_in_data <= (others =>'0');
-								  switch_port_in_wr_en <= '0';
-								  dma_rd_request <= '0';
-								  dma_wr_request <= '0';
-								  Ram_rd<='0';
-								  Ram_wr<='0';
-								  Ram_data_out<=(others=>'0');
-								  AppInitReq<='0';
-								  Result_i <=(others=>'0');
-								  Ready<='1';
-		when read_status1 => priority_rotation <='0';
-									fifo_rd_en <= '0';
-								  switch_port_in_data <= (others =>'0');
-								  switch_port_in_wr_en <= '0';
-								  dma_rd_request <= '1';
-								  dma_wr_request <= '0';
-								  Ram_rd<='0';
-								  Ram_wr<='0';
-								  Ram_data_out<=(others=>'0');
-								  AppInitReq<='0';
-								  Result_i <=(others=>'0');
-								  Ready<='0';
-		when read_status2 => priority_rotation <='0';
-									fifo_rd_en <= '0';
-								  switch_port_in_data <= (others =>'0');
-								  switch_port_in_wr_en <= '0';
-								  dma_rd_request <= '1';
-								  dma_wr_request <= '0';
-								  Ram_rd<='1';
-								  Ram_wr<='0';
-								  Ram_data_out<=(others=>'0');
-								  AppInitReq<='0';
-								  status_reg:=Ram_data_in;
-								  Result_i <=(others=>'0');
-								  Ready<='0';
-		when fetch_packet_type => priority_rotation <='0';
-								  fifo_rd_en <= rd_ok;
-								  switch_port_in_data <= (others =>'0');
-								  AppInitReq<='0';
-								  switch_port_in_wr_en <= '0';
-								  Ram_rd<='0';
-								  Ram_wr<='0';
-								  dma_rd_request <= '0';
-								  dma_wr_request <= '0';
-								  Ram_data_out<=(others=>'0');
-								  Result_i <=(others=>'0');
-								  Ready<='0';
-		
-		when decode_packet_type => priority_rotation <='0';
-											fifo_rd_en <= rd_ok;
-											switch_port_in_data <= Data_To_Send;
-											switch_port_in_wr_en <= '0';
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_data_out<=(others=>'0');
-											Result_i <=(others=>'0');											
-                    		Ready<='0';
-		when fetch_addresses => priority_rotation <='0';
-										fifo_rd_en <= rd_ok;
-										switch_port_in_data <= (others =>'0');
-										switch_port_in_wr_en <= '0';
-										AppInitReq<='0';
-										Ram_rd<='0';
-										Ram_wr<='0';
-										dma_rd_request <= '0';
-										dma_wr_request <= '0';
-										Ram_data_out<=(others=>'0');
-										Result_i <=(others=>'0');
-		                Ready<='0';
-		when decode_packet_type2 =>priority_rotation <='0';
-								         fifo_rd_en <= '0';
-								         switch_port_in_data <= data_to_send;
-											switch_port_in_wr_en <= '0';
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_data_out<=(others=>'0');
-											Result_i <=(others=>'0');
-											Ready<='0'; -- fin du module
-		
-		when  ex1_barrier1 => priority_rotation <='0';
-										  fifo_rd_en <= '0';
-											switch_port_in_data <= packet_type & pid_counter;
-											switch_port_in_wr_en <= not(switch_port_in_full);
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_barrier2 =>  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-											switch_port_in_data <= p_len;
-											switch_port_in_wr_en <= not(switch_port_in_full);
-											AppInitReq<='0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_data_out<=(others=>'0');	
-											Result_i <=(others=>'0');
-											Ready<='0'; -- fin du module									  
-										  
-		when ex1_barrier3 => priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= "0000" & pid;
-								        switch_port_in_wr_en <= not(switch_port_in_full);
-								        AppInitReq<='0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_barrier4 => priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= "0000" & pid;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_get1 =>      priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <= Wr_ok;
-								        AppInitReq<='0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		when ex1_get2 =>      priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <='0';
-								        AppInitReq<='0';
-								        Ram_rd<='0';
-										Ram_wr<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= dma_Wr;
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										 Ready<='0'; -- fin du module
-										  
-			when ex1_get3 =>	  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= (others=>'0');---???
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '1';
-											Ram_rd<='0';
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; -- le résultat de l'exécution 
-											Ready<='0'; -- fin du module
-											Result_i <=(2=>'1',others=>'0');--Get completed
-		when ex1_get4 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_Data_in;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= dma_rd;
-										  dma_wr_request <= dma_wr;
-											Ram_rd<=rd_ok;
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; --"00000001";
-											Result_i <=(2=>'1',others=>'0'); --get completed
-											Ready<='0'; -- fin du module
-		when ex1_put1 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '1';
-										  dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											Result_i <=(others=>'0');
-											Ready<='0'; -- fin du module
-		
-		when ex1_put2 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        AppInitReq<='0';
-								        Ram_rd<='1';
-										Ram_wr<='0';
-								        dma_rd_request <= '1';
-										  dma_wr_request <= '0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-										  
-		when ex1_put3 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_data_in;
-								        switch_port_in_wr_en <=  wr_ok;
-								        AppInitReq<='0';
-								        dma_rd_request <= '1';
-										  dma_wr_request <= '0';
-										  Ram_rd<='1';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0'; -- fin du module
-		
-		when ex1_put4 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_data_in;---???
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= rd_ok;
-										  dma_wr_request <= wr_ok;
-											Ram_rd<=rd_ok;
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution 
-											--result(1)<='1'; 
-											Result_i <=(1=>'1',others=>'0');--put completed
-											Ready<='0'; -- fin du module
-		when ex1_put5 =>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_Data_in;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= dma_rd;
-										  dma_wr_request <= dma_wr;
-											Ram_rd<=rd_ok;
-											Ram_wr<=wr_ok;
-											Ram_data_out<=data_to_send; --"00000001";
-											Result_i <=(1=>'1',others=>'0'); --put completed
-											Ready<='0'; -- fin du module
-		when ex1_init1 =>    priority_rotation <='0';
-										  if fifo_empty='0' then
-										    fifo_rd_en <= rd_ok; 
-										  else
-										    fifo_rd_en<='0';
-										  end if;
-								        switch_port_in_data <=  data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='1';
-											Result_i <=(others=>'0');
-											Ready<='0';
-			when ex1_init_run =>    priority_rotation <='0';
-										  
-										    fifo_rd_en <= fifo_rd; 
-										  
-								        switch_port_in_data <=  noc_fifo_in;
-								        switch_port_in_wr_en <= fifo_wr;
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='1';
-											Result_i <=(others=>'0');
-											Ready<='0';											     
-											
-		when ex1_init2=>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= noc_fifo_in;
-								        switch_port_in_wr_en <= fifo_wr;
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '1';
-											Ram_rd<='0';
-											Ram_wr<=wr_ok;
-											Ram_data_out<=Data_to_send; -- le résultat de l'exécution 
-											Ready<='0';								  -- dans le registre status
-											Result_i <=(others=>'0');--
-		when ex1_init3=>		  priority_rotation <='0';
-										  fifo_rd_en <= '0';
-								        switch_port_in_data <= ram_Data_in;
-								        switch_port_in_wr_en <= '0';
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '1';
-											Ram_rd<='0';
-											Ram_wr<='1';
-											Ram_data_out<="00010000";
-											Ready<='0'; -- fin du module
-											Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit
-		
-		when ex1_spawn =>		  priority_rotation <='0';
-										  fifo_rd_en <= rd_ok;
-								        switch_port_in_data <= Data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0';
-		when ex1_send_ack|ex1_Wsync =>		  priority_rotation <='0';
-										  fifo_rd_en <= rd_ok;
-								        switch_port_in_data <= Data_to_send;
-								        switch_port_in_wr_en <= wr_ok;
-								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_out<=(others=>'0');
-										  Result_i <=(others=>'0');
-										  Ready<='0';
-		when ex1_ready =>
-		  	                 Ready<='1'; -- fin du module
-		  	                 priority_rotation <='0';
-											fifo_rd_en <= '0';
-											switch_port_in_data <= (others =>'0');
-											switch_port_in_wr_en <= '0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='0';
-											Ready<='0';
-		  	                 
-		when others => 	        priority_rotation <='0';
-											fifo_rd_en <= '0';
-											switch_port_in_data <= (others =>'0');
-											switch_port_in_wr_en <= '0';
-											dma_rd_request <= '0';
-											dma_wr_request <= '0';
-											Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_out<=(others=>'0');
-											AppInitReq<='0';
-											Result_i <=(others=>'0');
-											Ready<='0';
-	end case;
-	
- end process;
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX2_FSM.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX2_FSM.vhd	(revision 96)
+++ 	(revision )
@@ -1,1722 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: GRIIA - ETIS  -  LIP6
--- Engineer: GAMOM, KIEGAING
--- 
--- Create Date:    01:02:10 06/17/2011 
--- Design Name: 
--- Module Name:    EX2_FSM - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
--- machine a etat qui execute la reception des packet dans le core mpi
--- Dependencies: 
---ss
--- Revision: 26/01/2012
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-library NocLib ;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.Numeric_std.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use Work.Packet_type.ALL;
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX2_FSM is
-
-   generic (
-				 pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
-				 nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
-			 );
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-
-           Instruction_en : in std_logic;
-			  
-			dma_wr_grant : in  STD_LOGIC;
-			dma_wr_request : out  STD_LOGIC;
-			dma_rd_grant : in  STD_LOGIC;
-			dma_rd_request : out  STD_LOGIC;
-			ram_rd : out std_logic;
-			ram_wr : out std_logic;
-			ram_address : out std_logic_vector(ADRLEN-1 downto 0);
-			Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-			Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
-			  
-			fifo_data : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-			fifo_wr_en : out  STD_LOGIC;
-			fifo_full : in  STD_LOGIC;
-			  Rec_Rdy : OUT std_logic;
-		    Rec_Data : buffer Typ_PortIO(0 to 3);
-		    Rec_Ack : IN std_logic;   
-			AppRank : in  STD_LOGIC_VECTOR(3 downto 0);
-			AppSize : in  STD_LOGIC_VECTOR(3 downto 0);
-           packet_received : out  STD_LOGIC;
-           packet_ack : in  STD_LOGIC;
-           barrier_completed : out  STD_LOGIC;
-			  Ready : Out std_logic;
-			  AppInitReq :out  STD_LOGIC; -- requête d'initialisation de l'application
-			  AppInitAck :in  STD_LOGIC; -- Acquitement d'initialisation
-			  Initialized:in std_logic ; -- état de la Lib
-			  Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
-           switch_data_available : in  STD_LOGIC;			  
-           switch_port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           switch_port_out_rd_en : out  STD_LOGIC
-			  
-			  
-			  
-			  );
-end EX2_FSM;
-
-architecture Behavioral of EX2_FSM is
---module pour la lecture des données sur le réseau
-CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu
-component Proto_receiv is
- generic (sizemem : natural := 64);
- port (
- clk,reset : in std_logic;
- fifo_empty,fifo_full : in std_logic;
- rcv_start : in std_logic; --début de la réception
- rcv_ack :in std_logic;   -- acquittement de la réception
- rcv_comp : out std_logic; -- fin de la réception
-  pop : out std_logic:='0';
- fifo_out : in std_logic_vector(Word-1 downto 0);
- mem :out memory(0 to sizemem-1));
-end component Proto_receiv;
-
-COMPONENT SetBit
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		BitMask : IN std_logic_vector(7 downto 0);
-		BitVal : IN std_logic;
-		start : in std_logic;
-		whole : in std_logic;
-		done :  out std_logic;
-		dma_wr_grant : IN std_logic;
-		dma_rd_grant : IN std_logic;
-		Ram_data_in : out std_logic_vector(7 downto 0);          
-		dma_wr_request : OUT std_logic;
-		dma_rd_request : OUT std_logic;
-		ram_rd : OUT std_logic;
-		ram_wr : OUT std_logic;
-		ram_address : IN std_logic_vector(15 downto 0);
-		Ram_data_out : in std_logic_vector(7 downto 0)
-		);
-		End component SetBit;
---constante
-constant Max_stack : integer:=7;--Le nombre de GET qui peuvent être empilés
--- définition du type etat de la machine à etat
-type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, 
-fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4,
-ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3,
- Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,
-  ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy);
-type fsm_ack is(ack0,ack_readwait,ack_checkwait,ack1,ack2,ack3,ack4,ack5,ack6);
-type mem32 is array (natural range <>) of std_logic_vector (31 downto 0);
-signal Next_Ex2_state,ex2_state :fsm_states;
-signal ack_state,next_ack_state : fsm_ack;
---
-signal mode_get,match_get:std_logic:='0';
-signal mode_get_i,match_get_i:std_logic:='0';
--- machine a etat du module
-signal packet_type, packet_type_i : std_logic_vector(3 downto 0);
-signal P_len_i,P_len : std_logic_vector(Word-1 downto 0);
-signal barrier_counter,barrier_counter_i : std_logic_vector(3 downto 0);
-signal pading_data,data_to_ram,Data_to_ram_i :  std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal n,n_i : natural range 0 to 15;
-signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0');
-signal data_to_write_fifo,data_to_write_fifo_i :  std_logic_vector(Word-1 downto 0);
---*******************************************
---signaux pour la fonction SetBit
-signal		sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
-signal		sb_BitVal,sb_start,sb_done : std_logic:='0';
-signal  sb_whole : std_logic:='0'; --écrire le mot entier
-signal		sb_Ram_data_in : std_logic_vector(7 downto 0);          
-signal		sb_dma_wr_request :  std_logic;
-signal		sb_dma_rd_request :  std_logic;
-signal		sb_ram_rd : std_logic;
-signal		sb_ram_wr : std_logic;
-signal		sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
-signal		sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
--- deuxième module pour set busy bit
-signal Set_Wbusy : std_logic:='0'; --choix du Mux
-signal	GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl
-
---*********************************************
-signal Ex2_on : std_logic:='0';
-signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
-signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement
-signal  dest_ack,dest_ack_i:std_logic_vector(3 downto 0) :=(others=>'0');
-signal  to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal Result_i,result1 :  STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0');
---signaux pour l'untilisation du composant de réception 
-signal rfifo_empty,rfifo_full:std_logic;
-signal rcv_start,rcv_comp,rcv_ack:std_logic;
-signal rpop:std_logic;
-signal initreq,initreq_i:std_logic:='0'; --Requete d'initialisation
---signal mem:memory(0 to Msize-1));
---jusqu'à 16 Get peuvent être attendus!
-signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés
-signal WStart,WPost,WBUSY, WBUSY_i,RGET,RGET_i: std_logic:='0'; --
-signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(Max_Stack downto 0):=(others=>'0');
-signal Waited_Get,Waited_Get_i : mem32(0 to Max_stack);
-Signal Rec_Data_i : Typ_PortIO(0 to 3);
-signal Get_Instr,Get_instr_i,Put_instr,Put_instr_i :memory(0 to 8);
-signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0');
-signal P_G,P_G_i: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get
-signal Ptr_Get,Ptr_Get_i : natural range 0 to Max_stack:=0;
-signal Received_get,Received_get_i : std_logic_vector(Max_stack downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu
-begin
-
-ram_address <= ack_address when instr_ack='1' else dest_address;
---fifo_data <= data_to_write_fifo;
-Result<=Result1;
-p_instr_fifo:process(ack_state,data_to_write_fifo_i,wr_ack,to_fifo_ack,instr_ack)
-begin
-  if instr_ack='1' then
-    fifo_data<=to_fifo_ack;
-else
-  fifo_data<=data_to_write_fifo_i;
-end if;
-end process p_instr_fifo;
-
-
-
-R0:proto_receiv generic map (sizemem =>4)
-	port map (
-	clk=>clk,
-	reset=>reset,
-	rcv_start=>rcv_start,
-	rcv_comp=>rcv_comp,
-	rcv_ack=>rcv_ack,
-	fifo_empty=>rfifo_empty,
-	fifo_full=>rfifo_full,
-	fifo_out=>switch_port_out_data,
-	pop=>rpop,
-	mem=>open
-	
-	);
---envoie de l'acquittement
-setbit1:SetBit
-	PORT MAP (
-		clk =>clk,
-		reset =>reset,
-		BitMask =>sb_bitMask,
-		BitVal =>sb_bitval,
-		dma_wr_grant =>dma_wr_grant,
-		dma_rd_grant =>dma_rd_grant,
-		Ram_data_in => sb_Ram_data_in,         
-		dma_wr_request =>sb_dma_wr_request,
-		dma_rd_request =>sb_dma_rd_request,
-		ram_rd =>sb_ram_rd,
-		ram_wr =>sb_ram_wr,
-		ram_address =>dest_address,
-		Ram_data_out =>sb_ram_data_out,
-		Start =>sb_start,
-		whole=>sb_whole,
-		done =>sb_done
-		);
-
--- processus de transistion entre les etats 
-ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized,
- switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len,
- sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter,
- dest_ack,rec_wpost,Gcomp,rec_data,mode_get,match_get,Instr_ack,result1,data_to_write_fifo)
-variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
-variable tempval : std_logic_vector(Word-1 downto 0);
-variable n_e,i:natural range 0 to 15 :=0;
-
---=================================================================-
-procedure read_nocdat_fsm(sdata_avail: std_logic;
-signal rd,wr:out std_logic;
-signal Plen_i : in std_logic_vector(Word-1 downto 0);
-signal Plen_o : out std_logic_vector(Word-1 downto 0);
-variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is
---lit la suite des données qui sont dans le NoC et identifie le paramètre important
-begin
-if n_e<3 then 
-			                 wr<='0';
-											if sdata_avail='1' then
-												n:=n_e+1;
-												rd<='1';
-												plen_o <=plen_i-1;
-											else
-												rd<='0';
-											end if;
-											--result_i<=(others=>'0');
-										elsif n_e=3 then
-											if sdata_avail='1' then
-												n:=n_e+1;
-												rd<='0';
-												--P_len <=P_len_i -1;
-												--data_to_ram<=sportdout;
-												--Result_i<=sport_out_data;
-											else
-												rd<='0';	
-											end if;
-										end if;
-end procedure;
-
-begin
- 
-	Next_Ex2_state <= Ex2_state;
-	Ex2_on<='0';
-	sb_whole<='0';
-	sb_start<='0'; --valeur par défaut
-	sb_bitmask<=x"FF";
-	sb_bitval<='1';
-	dma_rd<='0';
-	dma_wr<='0';
-	rd_ok<='0';
-	wr_ok<='0';
-	barrier_counter_i <= barrier_counter;
-  GPost_Set_i<=GPost_Set;
-  Rec_WPost_i<=Rec_WPost;
-  GPost_i<=GPost;
-  P_G_i<=P_G;
-  RGET_i<=RGET;
-  WBUSY_i<=WBUSY;
-  Result_i<=Result1;
-  Ptr_get_i<=Ptr_get;
-  mode_get_i<=mode_get;
-  data_to_write_fifo_i<=data_to_write_fifo;
-  match_get_i<=match_get;
-  GComp_i<=GComp;
-  Instr_ack_i<=Instr_ack;
-  received_get_i<=received_get;
-  mode_get_i<=mode_get;
-  InitReq_i<=InitReq;
-  match_get_i<=match_get;
-  Data_to_ram_i<=Data_to_ram;
-  dest_address_i<=dest_address;
-   for i in 0 to Max_stack loop 
-  Waited_get_i(i)<=Waited_get(i);
-  end loop;
- For i in 0 to 7 loop
-			Get_Instr_i(i)<=Get_instr(i);
-	  end loop;
-		Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
-		  n_i<=n; --valeur par défaut de n_i
-		  P_len_i<=P_len;
-		  for i in 0 to 3 loop 
-	  Rec_Data_i(i)<=Rec_Data(i);
-		Packet_type_i<=Packet_type;
-		dest_ack_i<=dest_ack;
-	  end loop;
-		  case ex2_state is
-		   when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then
-        		        Next_Ex2_state  <= fetch_packet_type;
-                    		     end if;
-                    		     rd_ok<='0';wr_ok<='0';
-			 when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1'  then 	--and initialized ='1'						
-											      Next_Ex2_state  <= decode_packet_type;
-											      packet_type_i<=switch_port_out_data(7 downto 4);
-											      Dest_ack_i<=switch_port_out_data(3 downto 0);
-											      Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue !
-											      rd_ok<='1';
-									         else
-											      --Next_Ex2_state <= Ex2_Ready;
-											      rd_ok<='0';
-								           end if;
-								           n_i<=0;
-			when decode_packet_type => rd_ok<='0';
-			                 if switch_data_available ='0' then
-													Next_Ex2_state <= decode_packet_type;
-												else
-												    rd_ok<='1';
-												    Rec_Data_i(1)<=switch_port_out_data-2;
-													 if packet_type = MPI_PUT then
-													    P_len_i <= switch_port_out_data - 2;
-														  n_i<=0;
-														  
-														 Next_Ex2_state <= decode_packet_type2;
-													  elsif packet_type = MPI_GET then
-													    P_len_i <=switch_port_out_data-2;
-														 Next_Ex2_state <= decode_packet_type2;
-													  elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
-													    P_len_i <= switch_port_out_data;
-														 n_i<=0;
-														 Next_Ex2_state <= ex2_barrier1;
-													  elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
-													   n_i<=0;
-													   wr_ok<='0';
-													   --rd_ok<='1';
-														P_len_i <= switch_port_out_data-2;
-														Rec_Data_i(1)<=switch_port_out_data;
-														Next_Ex2_state <= ex2_init1;
-														 elsif packet_type = MPI_ACK then
-													   n_i<=0;
-													   wr_ok<='0';
-													   rd_ok<='0';
-														P_len_i <= switch_port_out_data-2;
-														Next_Ex2_state <= ex2_ack1;
-														elsif packet_type = MPI_WIN_SYNC then
-													   n_i<=0;
-													   wr_ok<='0';
-													   rd_ok<='0';
-														P_len_i <= switch_port_out_data-2;
-														Next_Ex2_state <= ex2_Wsync;
-													  elsif packet_type = MPI_SPAWN  then
-													    Next_Ex2_state <= ex2_spawn1;
-													    wr_ok<='0';
-													   rd_ok<='0';
-													  else
-														  Next_Ex2_state <= decode_packet_type;
-														  rd_ok<='0';
-													 end if;
-												end if;
-			when decode_packet_type2 => if packet_type = MPI_PUT then
-													Next_Ex2_state <= fetch_addresses;
-												  else
-												 	Next_Ex2_state <= ex2_get1;							  
-							               end if;        									
-         when fetch_addresses => if  n=0 then
-                               if switch_data_available = '1'  then
-												            dest_address_i(15 downto 8) <= switch_port_out_data;
-												            Rec_data_i(2)<=switch_port_out_data;												             
-												              n_i <= n + 1;
-												                  rd_ok<='1';
-												        else
-												                  rd_ok<='0';												        												             
-												        end if;												      
-												       elsif n=1 then 
-												            if switch_data_available = '1'  then
-												              dest_address_i(Word-1 downto 0) <= switch_port_out_data;
-												                Rec_data_i(3)<=switch_port_out_data;
-												                P_len_i <= P_len - 2;	
-												                Next_Ex2_state <= ex2_put1;
-												                n_i<=0;
-												                rd_ok<='1';
-												                else
-												                  rd_ok<='0';
-												                    Next_Ex2_state <= fetch_addresses;
-								                        end if;	
-								               end if;	
- when ex2_ack1 =>  rd_ok<='0';
-                  if n<2 then --réception de l'acquittement.
-                    n_e:=n;
-                	   read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n);
-                	   n_i<=n_e;
-              	   elsif n=2  then
-              	     	if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												
-												data_to_ram_i<=switch_port_out_data;
-												Result_i<=switch_port_out_data;	
-											end if;
-              	     
-              elsif n=3 then
-              	     n_i<=n+1;P_G_i<=0;
-                    if data_to_ram(7 downto 4)=MPI_PUT then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16));
-														wr_ok<='1';
-														P_G_i<=1; --put ou get
-														P_len_i<=x"06"; --longueur de l'entête à parcourir
-												elsif	data_to_ram(7 downto 4)=MPI_GET then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														P_G_i<=2; --put get
-														P_len_i<=x"06";--taille de l'instruction en mémoire
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16));
-												elsif data_to_ram(7 downto 4)=MPI_SPAWN then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16));
-												elsif data_to_ram(7 downto 4)=MPI_INIT then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16));		
-														wr_ok<='1'; --
-														-- 
-												else 
-														Result_i<="00000000";
-														wr_ok<='0'; --
-														n_i<=n; --code inconnu !
-												end if;
-										elsif n=4 then
-										  if P_G=1 or P_G=2 then
-										    Next_ex2_state<=ex2_ack2;
-										   else
-										      Next_ex2_state<=ex2_ack3;
-										   end if;
-										   n_i<=0;
-										end if;
-          								               		
-            when Ex2_ack2 =>if unsigned(p_len)>0 then
-                        If Dma_rd_grant='1' then
-			                  if n=0  then
-												  n_i<=n+1; --cycle d'attente pour la RAM
-												elsif n=1 then 
-												  dest_address_i <= dest_address+1; 
-												  n_i<=2;
-												elsif n>=2 then
-											
-													    --creer un délai sur ces signaux par rapport à src_adress
-													     
-                          n_i<=n+1;
-                          rd_ok<='1';
---                          if n>1 then
-													dest_address_i <= dest_address+1; 
-													p_len_i <= p_len - 1;
-													--end if;
-													Get_Instr_i(n-2)<=Ram_data_out; --deux cycles de retard
-													Next_ex2_state <= ex2_ack2;
-												end if;	
-												end if;
-												dma_rd<='1';
-												rd_ok<='1';	
-												else
-												  if P_G=1 then
-												    dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16));
-												  else
-												    dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16));
-													Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id
-													Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur
-													Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas
-													Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut
-													RGET_i<='1';									
-													
-													Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter
-													end if;
-													Next_ex2_state <= ex2_ack3;
-													n_i<=0; --suite du process ack
-													rd_ok<='0';
-													dma_rd<='0';
-												end if;
-   
-when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction
-            	     sb_start<='1';
-            	     sb_bitMask<=x"20";--cinquième bit à un
-            	     sb_bitval<='1';
-            	     sb_whole<='0';--Modifier un seul bit !
-            	     if sb_done='1' then
-            	       n_i<=1;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-            	       dest_address_i<=dest_address+1;
-        	       end if;
-	       
-	       elsif n=1 then
-	                sb_start<='1';
-            	     sb_bitMask<=Rec_Data(2);
-            	     sb_bitval<='1';
-            	     sb_whole<='1'; 
-            	     if sb_done='1' then
-            	       n_i<=n+1;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-            	       sb_whole<='0';
-        	       end if;
-
-	        elsif n=2 then
-	             Next_Ex2_state<=Ex2_Ready;
-	             n_i<=0;
-            end if;
-            
-    when ex2_Wsync =>  rd_ok<='0';
-                  if n<2 then --réception de la synchronisation.
-                    n_e:=n;
-                	   read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n);
-                	   n_i<=n_e;
-              	   elsif n=2  then
-              	     	if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												
-												data_to_ram_i<=switch_port_out_data;
-												Result_i<=switch_port_out_data;	
-											end if;
-              	     
-              elsif n=3 then
-              	     n_i<=n+1;P_G_i<=0;
-                    if data_to_ram(7 downto 4)=SYNC_WSTART then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
-														wr_ok<='1';
-														P_G_i<=1; --put ou get
-														P_len_i<=x"06"; --longueur de l'entête à parcourir
-												elsif	data_to_ram(7 downto 4)=SYNC_WPOST then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														P_G_i<=2; --put get
-														P_len_i<=x"06";--taille de l'instruction en mémoire
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
-												elsif data_to_ram(7 downto 4)=SYNC_WWAIT then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16));
-												elsif data_to_ram(7 downto 4)=SYNC_WCOMP then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));		
-														wr_ok<='1'; --
-														Next_Ex2_State<=Ex2_WCOMP;
-														n_i<=0;
-												else 
-														Result_i<="00000000";
-														wr_ok<='0'; --
-														n_i<=n; --code inconnu !
-												end if;
-										
-										end if;  
-          when Ex2_Wcomp => dma_rd<='1';
-                        rd_ok<='1';	
-                        
-			                  if n=0  then
-												  n_i<=n+1; --cycle d'attente pour la RAM
-												  i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-													 GComp_i(i)<='1';
-												elsif n=1 then 
-												  dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));
-												  If Dma_rd_grant='1' then
-												  n_i<=2;
-												  end if;
-												elsif n=2 then
-											      If Dma_rd_grant='1' then
-													    --creer un délai sur ces signaux par rapport à dest_adress							     
-                                n_i<=n+1;
-                                rd_ok<='1';
-													       dest_address_i <= dest_address+1; 
-													       GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard
-													       
-													 else
-													   n_i<=1;
-													  end if;
-													elsif n=3 then
-													  If Dma_rd_grant='1' then
-													  --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed
-													 n_i<=n+1;
-													 rd_ok<='1';
-													 dma_rd<='1';
-													 end if;
-													elsif n=4 then
-													  --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed
-
-													 rd_ok<='1';
-													 dma_rd<='1';	
-													 n_i<=n+1;	
-													 elsif n=5 then		
-													 rd_ok<='0';
-													 dma_rd<='0';										 
-													n_i<=0;
-													If GPost=GComp then --le même nombre de post que de COmpleted ?
-													GPost_Set_i<='1';
-													end if;
-
-													Next_ex2_state <= ex2_set_busy;
-												end if;	
-												
-												          
-			when ex2_init1 => if n<2 then 	-- execution du mpi Init
-			                 wr_ok<='0';
-											if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												P_len_i <=P_len-1;
-												Rec_Data_i(n+2)<=switch_port_out_data;
-												data_to_ram_i<=switch_port_out_data;
-												Result_i<=switch_port_out_data;
-											else
-												rd_ok<='0';
-												n_i<=n;
-											end if;
-											result_i<=(others=>'0');
-										elsif n=2 then
-												n_i<=n+1;
-												rd_ok<='0';
-
-										elsif n=3 then 
-										  rd_ok<='0'; -- normalement plus rien à lire
-										  n_i<=n+1;
-											if Initialized='1' then
-												if data_to_ram(7 downto 4)=INIT_SEEKMAIN then
-														Result_i<=data_to_ram;
-														InitReq_i<='1'; --permet d'activer Init de Ex_4
-												elsif	data_to_ram(7 downto 4)=INIT_STAT then
-														Result_i<=data_to_ram;
-														InitReq_i<='1'; --permet d'activer Init de Ex_4
-												elsif data_to_ram(7 downto 4)=INIT_REGISTER then
-														Result_i<=data_to_ram;
-														InitReq_i<='0'; --permet d'activer Init de Ex_4
-														report "Mise à jour des données d'initialisation";
-														Next_Ex2_state<=ex2_ready;
-														n_i<=0;
-												elsif data_to_ram(7 downto 4)=INIT_SPAWN then
-														Result_i<=data_to_ram;
-														InitReq_i<='1'; --permet d'activer Init de Ex_4
-														-- il faut mettre à jour l'état de Spawn
-												else 
-														Result_i<="00000000";
-														InitReq_i<='0'; --permet d'activer Init de Ex_4
-												end if;
-											end if;
-											elsif n=4 then 
-										    n_i<=n+1;
-										  elsif n=5 then
-												if p_len=0 then 
-													Next_Ex2_state<=ex2_init2;
-													rd_ok<='0';
-												else
-													p_len_i <=p_len -1;
-													rd_ok<='1'; --vider le tampon de lecture pour ce paquet !
-												end if;
-											
-										end if;
-			when ex2_init2=>  if n=5 then 
-			                         if AppInitAck='1' then
-											             n_i<=n+1;
-											             InitReq_i<='0';
-											             Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init
-											         end if;
-											     elsif n=6 then 
-											         	Next_Ex2_state<=Ex2_Ready;
-												        n_i<=0;
-												        InitReq_i<='0';
-											     end if;
-										
-			when ex2_put1 => rd_ok<='0'; --ne  pas autoriser la lecture du switch
-			                 wr_ok<='0';
-			                 dma_rd<='1';
-			                 if n=0 then
-		                if RGET='1' then
-									Lp:	  for i in 1 to Max_stack loop  -- to Ptr_get normalement
-										  if i<=Ptr_Get then
-										  if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and
-										    waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and
-										    waited_get(i-1)(23 downto 16)=rec_data(2) and
-											   waited_get(i-1)(31 downto 24)=rec_data(3) then
-                          if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then
-		
-             													match_get_i<='1';
-                          end if;
-                        else
-                      
-										      end if;
-										 end if;
-										exit Lp when i= Ptr_get;
-										end loop Lp;
-										end if;
-											
-			                   n_i<=1;
-			                 elsif n=1 then
-			                   if match_get='1' then 
-			                     n_i<=3; --ne pas envoyer ack dans ce cas
-			                     report "GET Détecté ACK pas envoyé dans Ex2 du HCL n°" & image(pid);
-			                     else
-			                       n_i<=2;
-			                    end if;
-			                 elsif n=2 then
-			                   	 instr_ack_i<='1'; --activer  l'envoie de l'accusé de réception
-			                   	 data_to_write_fifo_i<=to_fifo_ack;
-			                   	 wr_ok<=wr_ack;
-			                   	 if sent_ack='1' then
-			                   	   n_i<=3;
-			                   	   instr_ack_i<='0';
-			                   	   dma_wr<='1';
-			                   	  end if;
-			                   	  
-			                   	elsif n=3 then
-			                   	  dma_wr<='1';
-			                   	if dma_wr_grant = '1' then
-  										          Next_Ex2_state <= ex2_put2;
-  										          data_to_ram_i<=switch_port_out_data;
-  										          rd_ok<='0';
-  										          n_i<=0;
-  										          delai:=0;
-										  	   else
-										          Next_Ex2_state <= ex2_put1;
-								          end if;
-								          end if;	
-			when ex2_put2 =>	rd_ok<='0';
-			                 n_i<=1;
-			                 i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-			                 --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-			               if unsigned( P_len) > 0  then 
-												
-											if switch_data_available = '1' and delai=0  then
-													   delai:=1; --une donné lue
-														 P_len_i <= P_len - 1;
-														 Next_Ex2_state <= ex2_put2;
-														 rd_ok<='1';
-														 data_to_ram_i<=switch_port_out_data;
-											end if;
-											if  dma_wr_grant='1' and delai=1 then
-											 -- if n=1 then
-													  wr_ok<='1';
-													  dest_address_i <= dest_address + 1;
-													  delai:=0;--une donnée écrite
-											--	else
-											--	    dest_address_i <= dest_address ;
-											--	end if;
-														--if delai=1 then 
-														--data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
-														--end if;
-														 
-												else
-												  dest_address_i<=dest_address;
-												  wr_ok<='0';
-												  n_i<=0;
-												end if;
-											
-													Next_Ex2_state <= ex2_put2;
-										
-										else 
-										  rd_ok<='0';
-										  
-
-											if dma_wr_grant='1' and n=1 then 
-
-												 Next_Ex2_state <= ex2_put3;
-												Wr_ok<='0';
-												 n_i<=0;
-											 end if;
-									    end if;
-									 
-			when ex2_put3 =>			if dma_rd_grant='1' then 
-													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-													Next_Ex2_state <= ex2_put4;
-													n_i<=0;
-													rd_ok<='1';
-													wr_ok<='0';
-												end if;
-			
-			when ex2_put4 => if  n>0 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-										if n=0 then
-										  if RGET='1' then
-									L1:	  for i in 1 to Max_stack loop  -- to Ptr_get normalement
-										  if i<=Ptr_Get then
-										  if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and
-										    waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and
-										    waited_get(i-1)(23 downto 16)=rec_data(2) and
-											   waited_get(i-1)(31 downto 24)=rec_data(3) then
-                          if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then
-                          received_get_i(i-1)<='1';
-             													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-             													mode_get_i<='1';
-             													match_get_i<='1';
-                          end if;
-                        else
-                      
-										      end if;
-										 end if;
-										exit L1 when i= Ptr_get;
-										end loop L1;
-										end if;
-											
-											n_i<=n+1;
-											rd_ok<='1';
-											wr_ok<='0';
-											
-											elsif n=1 then
-											 if match_get='0' then
-											   i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-											  Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-                      end if;
-												if dma_rd_grant='1' then 
-												if RGET='1' then --si on est en mode attente d'un Get
-												RGET_i<='0';  --Supposons tous les Gets reçus !
-                        test_wcomp:for i in 1 to Max_stack loop --Tous les Get reçus ?
-                          if Ptr_get>=i then
-                          if received_get(i-1)='0' then
-                            RGET_i<='1';    --Non !
-                        end if;
-                      end if;
-								exit test_wcomp when i=Ptr_get;
-                        end loop test_wcomp;
-                       
-                      end if;
-													n_i<=n+1;
-													rd_ok<='1';
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												end if;
-											elsif n=2 then
-												if dma_rd_grant='1' and dma_wr_grant='1' then 
-													n_i<=n+1;
-													tempval:=Ram_data_out;
-													tempval(4):='1';			--SET du bit DReceived
-												  if Mode_Get='1' then                    --si get ack est détecté
-													   tempval(6):=RGET;  -- Bit 6  Busy=0 si dernier get reçu !!
-													   mode_get_i<='1';
-													end if;
-													data_to_ram_i<=tempval;
-													rd_ok<='0';
-													wr_ok<='1';
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												n_i<=0;
-												end if;
-											elsif n=3 then
-												if dma_wr_grant='1' then
-													rd_ok<='0';
-													wr_ok<='1';
-													n_i<=n+1;
-												end if;
-											elsif n=4 then
-												if dma_wr_grant='1' then
-													rd_ok<='0';
-													wr_ok<='1';
-													
-													n_i<=5;
-												end if;
-										 elsif n=5 then
-										     Next_Ex2_state <= ex2_set_busy;
-										     n_i<=0;
-										     rd_ok<='0';
-													wr_ok<='0';
-													mode_get_i<='0';
-													match_get_i<='0';
-											end if;
-											
-										 
-								  
-									--	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
-			when ex2_put5 => 
-										   Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put
-										
-			when ex2_spawn1 => 
-											
-											if n<2 then
-											 n_e:=n;
-											read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n);	
-											n_i<=n_e;
-											Rec_Data_i(2)<=Switch_port_out_data;
-											elsif n=2 then
-											    Rec_Data_i(3)<=Switch_port_out_data;
-													Result_i<=Switch_port_out_data;
-													Data_to_ram_i<=Switch_port_out_data;
-													n_i<=n+1;
-													rd_ok<='1';
-											elsif n=3 then
-												if data_to_ram(7 downto 4)=SPAWN_LOAD then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --permet d'activer Init de Ex_4
-												elsif	data_to_ram(7 downto 4)=SPAWN_COMP then
-														Result_i<=data_to_ram;
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-
-												elsif	data_to_ram(7 downto 4)=SPAWN_ERR then
-														Result_i<=data_to_ram;
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-												else
-														Result_i<=(others=>'0');
-													
-												end if;
-												n_i<=n+1;
-												rd_ok<='0';
-											elsif n=4 then	
-											     wr_ok<='1';
-														if AppInitAck='1' then
-															wr_ok<='0';
-															rd_ok<='0';
-															n_i<=n+1;
-														end if;
-											elsif n=5 then
-															wr_ok<='0';
-															rd_ok<='0';
-															n_i<=0;
-												Next_Ex2_state <=Ex2_Ready;
-											end if;
-			when Ex2_Spawn2=> 
-			               Next_Ex2_state <=Ex2_Ready;
-			when ex2_get1 =>  rd_ok<='0'; --ne  pas autoriser la lecture du switch
-			                 --ack_state<=next_ack_state; --MAE d'envoie de AR
-			                 dma_rd<='1';
-			                 if n=0 then
-			                   	 instr_ack_i<='1'; --activer  l'envoie de l'accusé de réception
-			                   	 data_to_write_fifo_i<=to_fifo_ack;
-			                   	 wr_ok<=wr_ack;
-			                   	if sent_ack='1' then
-			                   	   n_i<=1;
-			                   	   instr_ack_i<='0';
-			                   	   wr_ok<='0';
-			                   	   --if switch_data_available='1' then
-			                   	   rd_ok<='0';--
-			                   	   --P_len<=P_len-1;
-			                   	   --end if;
-			                   	  end if;
-			                   	  
-			                   	elsif n=1 then
-			                   	if   switch_data_available='1' then
-			                   	if fifo_full = '0' then  -- conversion du get en put en empilement dans le fifo
-										    	     data_to_write_fifo_i <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put						       	 
-											         wr_ok<='1';
-											         rd_ok<='1'; --autoriser la lecture du crossbar
-											         P_len_i<=P_len-1;
-											         n_i<=n+1;
-											     else
-											       Wr_ok<='0';
-											       Rd_ok<='0';
-								        	  end if;	
-								        	  else
-								        	    Wr_ok<='0';
-								        	    rd_ok<='0';
-								        	  end if;
-								        	 elsif n=2 then
-								        	  if   switch_data_available='1' then
-								        	   if fifo_full = '0' then  -- conversion du get en put en empilement dans le fifo
-										    	     --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put						       	 
-											       	--P_len_i <= P_len-1;--le nombre d'octet qui restent à copier
-											       	 Next_Ex2_state <= ex2_get2;
-											         wr_ok<='0';
-											         rd_ok<='0'; --autoriser la lecture du crossbar
-											         n_i<=0;
-											       else
-											         rd_ok<='0';
-											         wr_ok<='0';
-											      end if;
-											     else
-											         rd_ok<='0';
-											         wr_ok<='0';
-								        	  end if;	
-								      end if;
-			when ex2_get2 => if P_len>0 then 
-			                 if fifo_full = '0' and switch_data_available ='1' then
-  										        data_to_write_fifo_i <= switch_port_out_data;--la longueur initiale du GET
-  											     p_len_i <= P_len - 1;
-  										        Next_Ex2_state <= ex2_get2;
-  											     wr_ok<='1';
-  											     Rd_ok<='1';
-										    elsE
-										         
-											         wr_ok<='0';
-											         Rd_ok<='0';
-											 END IF;
-										  else
-										  if n=0 then
-										   if fifo_full='0' then
-											 wr_ok<='0';--une impulsion en plus
-											 n_i<=n+1;
-											 Next_Ex2_state <= ex2_get2;
-											 else
-											  wr_ok<='0';
-											end if;
-											
-											else
-											  Next_Ex2_state <= ex2_get3;
-											  n_i<=0;
-											  wr_ok<='0';
-											 end if;
-											rd_ok<='0';
-								    end if;
-								    i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-			               Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-
-								    --préparer en avance l'adresse de lecture/écriture
-								    dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-		   when ex2_get3 => wr_ok<='0';
-		                    if dma_rd_grant='1' then -- fin du mpi_get
-										   Next_Ex2_state <= ex2_get4;
-											n_i<=0;
-											--activer le bit sending du registre de transfert
-										  else
-											Next_Ex2_state <= ex2_get3;
-								      end if;
-											
-										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-			when ex2_get4 => if n <4 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-											if n=0 then
-												if dma_rd_grant='1' then
-												n_i<=n+1;
-												
-												end if;
-												rd_ok<='1';
-												wr_ok<='0';
-											elsif n=1 then
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-												  data_to_ram_i<=Ram_data_out;
-											elsif n=2 then
-													if dma_rd_grant='1' and dma_wr_grant='1' then
-														n_i<=n+1;
-														tempval:=Ram_data_out;
-														--tempval(2):='1';  	--mise à 1 du Bit DSending
-														--tempval(5):='0'; 		--Mise à 0 du Bit Sent
-														data_to_ram_i(2)<='1';  	--mise à 1 du Bit DSending
-														data_to_ram_i(5)<='0'; 		--Mise à 0 du Bit Sent
-
-														data_to_ram_i<=tempval;
-														rd_ok<='1';
-														wr_ok<='0';
-													else
-													rd_ok<='1';
-													wr_ok<='0';
-													n_i<=0;
-												end if;
-											
-											  
-											elsif n=3 then
-												if dma_wr_grant = '1' then
-												n_i<=n+1;
-												rd_ok<='0';
-												wr_ok<='1';
-												end if;
-											elsif n=4 then
-											  if dma_wr_grant = '1' then
-													n_i<=0;
-													Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get
-											  else
-													rd_ok<='0';
-													wr_ok<='1';
-													--n<=n-1;
-											 end if;
-											end if;
-										   
-										 
-										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-					when ex2_Set_Busy => if n=0 then --set busy bit of the instruction
-            	             dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-                          n_i<=1;
-                              if Gpost_Set='1' then
-                                if  (rec_wpost=gpost) and RGET='0' then
-                                    Wbusy_i<='0';
-                                    Gpost_Set_i<='0';
-                                    GComp_i<=(others=>'0');
-                                    rec_wpost_i<=(others=>'0');--reset des messages reçu
-                                else
-                                    Wbusy_i<='1';
-                                end if;
-                            else
-                                
-                                n_i<=2;
-                              end if;
-                              if RGET='1' then 
-                                  WBusy_i<='1';
-                             end if;
-          	     elsif n=1 then
-            	     sb_start<='1';
-            	     sb_bitMask<=x"40";--6e bit à 1
-            	     sb_bitval<=WBusy;
-            	     if sb_done='1' then
-            	       n_i<=2;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-        	       end if;
-	       elsif n=2 then
-	             Next_Ex2_state<=Ex2_Ready;
-	             n_i<=0;
-            end if;
-								-- execution du barrier
-			when ex2_barrier1 => if switch_data_available = '1' then
-												 pading_data <= switch_port_out_data;
-												 Next_Ex2_state <= ex2_barrier2;
-											  else
-											    Next_Ex2_state <= ex2_barrier1;	
-											 end if;	
-			when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then
-												 barrier_counter_i <= barrier_counter + 1;
-												 Next_Ex2_state <= ex2_barrier4;	
-											  else
-											    Next_Ex2_state <= ex2_barrier3;	
-											 end if;	
-			when ex2_barrier3 => if n < 10 then
-												 n_i<= n + 1;
-												 Next_Ex2_state <= ex2_barrier3;	
-											  else
-											    Next_Ex2_state <= Ex2_Ready;	
-											 end if;	
-			when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED 
-												 data_to_write_fifo_i <= MPI_BARRIER_COMPLETED & "0000";
-												 Next_Ex2_state <= ex2_barrier5;	
-											  else
-											    Next_Ex2_state <= Ex2_Ready;	
-											 end if;	
-			when ex2_barrier5 => if fifo_full = '0' then  -- taille du packet MPI_BARRIER_COMPLETED
-												 data_to_write_fifo_i <= "00000011";
-												 Next_Ex2_state <= ex2_barrier6;	
-											  else
-											    Next_Ex2_state <= ex2_barrier5;	
-											 end if;		
-			when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
-												 data_to_write_fifo_i <= "00000000";
-												 Next_Ex2_state <= ex2_barrier7;	
-											  else
-											    Next_Ex2_state <= ex2_barrier6;	
-											 end if;				
-			when ex2_barrier7 => if fifo_full = '0' then
-												 barrier_counter_i <= "0000";
-												 Next_Ex2_state <= Ex2_Ready;	
-											  else
-											    Next_Ex2_state <= ex2_barrier7;	
-											 end if;				
-			
-			when others => Next_Ex2_state <= Ex2_Ready;
-		   end case;
-        
- end process;
- 
- -- sortie de la machine à etat
---
- ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr,
- switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request,
- appInitAck,n,InitReq)
-  variable transact : std_logic_vector(Word-1 downto 0);
-  begin   
--- code fonctionnel	
-	sb_ram_data_out<=Ram_data_out; --presque toujours cette valeur
-	case Ex2_state is
-		when  Ex2_Ready => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='1';
-										  AppInitReq<='0';
-		when  fetch_packet_type => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='0';
-										  AppInitReq<='0';
-										  
-								  
-		when decode_packet_type => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when decode_packet_type2 => fifo_wr_en <= '0';
-										    switch_port_out_rd_en <= '0';
-										    packet_received <= '0'; 
-										    dma_wr_request <= '0';
-										    dma_rd_request <= '0';
-										    Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										    barrier_completed <= '0';
-										    AppInitReq<='0';	
-											Ready<='0';
-		when fetch_addresses =>  fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		when ex2_ack1 |ex2_Wsync =>		  
-										Ready<='0';
-										switch_port_out_rd_en<=rd_ok;
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;
-				when ex2_ack2|Ex2_WCOMP =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= dma_rd;
-										dma_wr_request <= '0';
-										Ram_rd<=rd_ok;
-										Ram_wr<='0';
-										Ram_data_in<=(others=>'0');
-			when ex2_ack3 =>		  
-										Ready<='0';
-										switch_port_out_rd_en<=rd_ok;
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;							
-		when ex2_put1 =>  fifo_wr_en <= wr_ok;
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= dma_wr;
-										  dma_rd_request <= dma_rd;
-										  Ram_rd<='1';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when  ex2_put2 =>   Ready<='0';
-										fifo_wr_en <= '0';
-										switch_port_out_rd_en <=rd_ok;
-									   
-										if rd_ok = '1' then
-										
-										 Ram_data_in<=switch_port_out_data;
-										else
-											Ram_data_in<=data_to_ram;
-										end if;
-										Ram_wr<=wr_ok;
-										Ram_rd<='0';
-										packet_received <= '0';
-										dma_rd_request <= '0'; 
-										dma_wr_request <= '1';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-		when  ex2_put3 => 	 Ready<='0';
-										fifo_wr_en <= '0';
-									   switch_port_out_rd_en <='0';	
-										--ne pas corrompre le contenu de la RAM
-										--Ram_data_in<=data_to_ram; 					
-										Ram_wr<='0';
-										Ram_rd<='1';
-										packet_received <= '0';
-										dma_rd_request <= '1'; 
-										dma_wr_request <= '0';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-										Ram_data_in<=(others=>'0');
-		
-		when ex2_put4 =>    fifo_wr_en <= '0';
-										Ready<='0';
-										switch_port_out_rd_en <= '0';
-										 packet_received <= '1'; 
-										 dma_rd_request <= dma_rd;
-										 dma_wr_request <=dma_wr;
-										 Ram_wr<=wr_ok;
-										 Ram_rd<=rd_ok;
-										 AppInitReq<='0';	 
-										 barrier_completed <= '0';	
-										 Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution 
-											
-		when ex2_put5 =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								        packet_received <= '1';
-								        AppInitReq<='0';
-								        barrier_completed <= '0';
-								        dma_rd_request <= dma_rd;
-										dma_wr_request <= dma_wr;
-										Ram_rd<=rd_ok;
-										Ram_wr<=wr_ok;
-										Ram_data_in<=data_to_ram;
-										--Result <=(1=>'1',others=>'0'); --put completed								  
-		
-		when ex2_get1=>   fifo_wr_en <= wr_ok;
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= dma_rd;
-										  Ram_rd<='1';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when ex2_get2 =>	     										    
-											 switch_port_out_rd_en <=rd_ok;
-										  fifo_wr_en <= Wr_ok;
-										  Ready<='0';
-										  packet_received <= '0';
-										  dma_rd_request <= '0'; 
-										  dma_wr_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0'; 
-										  AppInitReq<='0';	
-										    
-		when ex2_get3 =>      		fifo_wr_en <= '0';
-										Ready<='0';
-										switch_port_out_rd_en <= '0';
-										 packet_received <= '1'; 
-										 dma_rd_request <= '1';
-										 dma_wr_request <='0';
-										 Ram_wr<='0';
-										 Ram_rd<='1';
-										  AppInitReq<='0';	
-										  barrier_completed <= '0';
-										Ram_data_in<=(others=>'0');
-										 --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
-											
-		when ex2_get4 =>		  
-										Ready<='0';
-										barrier_completed <= '0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								        packet_received <= '1';
-								        AppInitReq<='0';
-								        dma_rd_request <= dma_rd;
-										dma_wr_request <= dma_wr;
-										Ram_rd<=rd_ok;
-										Ram_wr<=wr_ok;
-										Ram_data_in<=data_to_ram; --activer le bit DSending
-		
-		
-		when ex2_barrier1 =>  fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= switch_data_available;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0'; 
-											Ready<='0';
-										  AppInitReq<='0';	
-										  
-		when ex2_barrier2 =>  fifo_wr_en <= '0';
-										Ready<='0';
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';    
-										  AppInitReq<='0';	
-										  
-		when ex2_barrier3 =>	fifo_wr_en <= '0';
-										  switch_port_out_rd_en <='0';
-										  Ready<='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '1';	 
-											AppInitReq<='0';	
-		
-		when ex2_barrier4 =>   fifo_wr_en <= '0';
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  
-										  
-		when ex2_barrier5 =>  fifo_wr_en <= not(fifo_full);
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';										  
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  
-		when ex2_barrier6 =>  fifo_wr_en <= not(fifo_full);										 
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';
-										  Ready<='0';		 	
-		
-		when ex2_barrier7 =>  fifo_wr_en <= not(fifo_full); 
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  	
-     when ex2_spawn1 =>				fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <= rd_ok;--switch_data_available;
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-										   Ready<='0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<=wr_ok;
-	when  ex2_Spawn2 =>   Ready<='0';
-										fifo_wr_en <= '0';
-										switch_port_out_rd_en <='0';
-									   									
-											Ram_data_in<=data_to_ram;
-										
-										Ram_wr<=wr_ok;
-										Ram_rd<='0';
-										packet_received <= '0';
-										dma_rd_request <= '0'; 
-										dma_wr_request <= '1';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-	  when ex2_init1 =>    	fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <= rd_ok;--switch_data_available;
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-										   Ready<='0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<=InitReq;
-											
-		
-		when ex2_init2 =>    	fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <='0';
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<= not(AppInitAck);
-											Ready<='0';
-
-            
-		when ex2_Set_Busy =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;				
-		when others => 			 Ready<='1';   -- le module est à nouveau libre
-									fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='1';
-										  AppInitReq<='0';
-	end case;
-	
- end process;
- 
- ex2_fsm_sync:process(clk,reset)
- 
- begin
-   
-	if reset = '1' then
-	ex2_state <= Ex2_Ready;
-	ack_state<=ack0; --MAE d'envoie de AR
-	n<=0;
-	P_len<=(others=>'0');
-	GPost<=(others =>'0');
-	else
-	if rising_edge(clk) then
-	  ex2_state<=next_ex2_state;
-	  ack_state<=next_ack_state; --MAE d'envoie de AR
-	  n<=n_i;
-	  P_len<=P_len_i;
-	  Packet_type<=packet_type_i;
-	  P_G<=P_G_i;
-	  Result1<=Result_i; --juste une copie
-	  dest_address <= dest_address_i;
-	  data_to_write_fifo<=data_to_write_fifo_i;
-	  WBUSY<=WBUSY_i;
-	  RGET<=RGET_i;
-	  InitReq<=InitReq_i;
-	  mode_get<=mode_get_i;
-	  match_get<=match_get_i;
-	  Sent_ack<=sent_ack_i;
-	  Instr_ack<=Instr_ack_i;
-	  Ptr_Get<=Ptr_Get_i;
-	  Rec_Wpost<=Rec_WPost_i;
-	  dest_ack<=dest_ack_i;
-	  barrier_counter<=barrier_counter_i;
-	  GPost<=GPost_i;
-	  GComp<=GComp_i;
-	  Received_get<=Received_get_i;
-	  GPost_set<=GPost_Set_i;
-	  data_to_ram<=data_to_ram_i;
-	  For i in 0 to Max_stack loop
-	     Waited_get(i)<=Waited_get_i(i);
-	  end loop;
-	  For i in 0 to 7 loop
-			Get_Instr(i)<=Get_instr_i(i);
-	  end loop;
-	  for i in 0 to 3 loop 
-	  Rec_Data(i)<=Rec_Data_i(i); 
-	  end loop;
-	 end if;
-	end if;
- end process ex2_fsm_sync;
-snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,apprank,Packet_type,ram_data_out,dma_rd_grant)
---ce processus est chargé d'emettre  l'accusé de réception pour chaque instruction reçu
-begin	
---  if rising_edge(clk) then
-    Sent_ack_i<='0'; --pas besoin de le mémoriser
-	 wr_ack<='0'; --valeur par défaut
-	 ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen));
-    if  reset='1' then
-        next_ack_state<=ack0;
-		  to_fifo_ack<=(others=>'1');
-  else
-    next_ack_state<=ack_state;
-	
-	case ack_state is 
-	when ack0 =>to_fifo_ack<=(others=>'0'); 
-	               Wr_ack<='0';
-	               if instr_ack='1' then 
-	               next_ack_state<=ack_readwait;
-	               to_fifo_ack <= MPI_ACK & Dest_ack;
-	               wr_ack<='0';
-	             end if;
-	             
-	             sent_ack_i<='0';
-	when ack_readwait =>	to_fifo_ack <= MPI_ACK & Dest_ack;
-	  ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen));
- --vérifier WinPost attend bien une action de cette source
-	 if dma_rd_grant='1' then 
-	    next_ack_state<=ack_checkwait;
-	 end if;  
-	when ack_checkwait =>	to_fifo_ack <= MPI_ACK & Dest_ack;
-	ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen));
-	if dma_rd_grant='1' and ram_data_out(conv_integer(dest_ack))='1' then
-	 next_ack_state<=ack1;
-	elsif dma_rd_grant='0' then
-	next_ack_state<=ack_readwait;
-	else
-	  next_ack_state<=ack6; --pas d'acknowledge à envoyer
-	  assert true report "Packet non attendu de cette source !"
-	  severity failure;
-	end if;           
-	when ack1 =>  if fifo_full = '0' then  -- conversion envoie lack à l'emetteur  
-	       	           -- en empilement dans le fifo
-										    to_fifo_ack <= MPI_ACK & Dest_ack;
-											  next_ack_state <= ack2;
-											  wr_ack<='1';
-								else
-								        wr_ack<='0';
-								 end if;	
-								      sent_ack_i<='0';
-										to_fifo_ack <= MPI_ACK & Dest_ack;
-	when ack2 =>     if fifo_full = '0' then
-										   to_fifo_ack <= "00000100";--la longueur
-											
-										   next_ack_state <= ack3;
-											wr_ack<='1';
-										else --
-										  next_ack_state <= ack2;
-											wr_ack<='0';
-										 
-								    end if;
-									 to_fifo_ack <= "00000100";
-								    sent_ack_i<='0';
-	when ack3 =>     if fifo_full = '0' then
-	                     to_fifo_ack <= "00000000";--
-										   next_ack_state <= ack4;
-											wr_ack<='1';
-										else --
-										  next_ack_state <= ack3;
-											wr_ack<='0';
-										 
-								    end if;	
-									 to_fifo_ack <= "00000000";
-								    sent_ack_i<='0';
-	when ack4 =>     if fifo_full = '0' then
-											to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur
-										  next_ack_state <= ack5;
-											wr_ack<='1';
-											sent_ack_i<='0';
-										else --
-										  next_ack_state <= ack4;
-											wr_ack<='0';
-										 sent_ack_i<='0';
-								    end if;	
-									 to_fifo_ack <=packet_type & apprank ;
-			when ack5 => if Instr_ack='0' then --dernier pulse
-			           				next_ack_state <= ack0;
-			           			else
-			           			  next_ack_state <= ack6;
-			           		 end if;
-			           		 wr_ack<='0';
-										sent_ack_i<='1';
-										to_fifo_ack<=(others=>'1');
-			when ack6 => if Instr_ack='0' then
-			           				next_ack_state <= ack0;
-			           				
-			           		 end if;
-			           		 wr_ack<='0';
-								 sent_ack_i<='1';
-								 to_fifo_ack<=(others=>'1');
-end case;
-end if;
---end if;
-end process;	
-
-	    
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX2_FSM.vhd.bak
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX2_FSM.vhd.bak	(revision 96)
+++ 	(revision )
@@ -1,1722 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: GRIIA - ETIS  -  LIP6
--- Engineer: GAMOM, KIEGAING
--- 
--- Create Date:    01:02:10 06/17/2011 
--- Design Name: 
--- Module Name:    EX2_FSM - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
--- machine a etat qui execute la reception des packet dans le core mpi
--- Dependencies: 
---ss
--- Revision: 26/01/2012
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-library NocLib ;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.Numeric_std.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use Work.Packet_type.ALL;
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX2_FSM is
-
-   generic (
-				 pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
-				 nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
-			 );
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-
-           Instruction_en : in std_logic;
-			  
-			dma_wr_grant : in  STD_LOGIC;
-			dma_wr_request : out  STD_LOGIC;
-			dma_rd_grant : in  STD_LOGIC;
-			dma_rd_request : out  STD_LOGIC;
-			ram_rd : out std_logic;
-			ram_wr : out std_logic;
-			ram_address : out std_logic_vector(ADRLEN-1 downto 0);
-			Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-			Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
-			  
-			fifo_data : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-			fifo_wr_en : out  STD_LOGIC;
-			fifo_full : in  STD_LOGIC;
-			  Rec_Rdy : OUT std_logic;
-		    Rec_Data : buffer Typ_PortIO(0 to 3);
-		    Rec_Ack : IN std_logic;   
-			AppRank : in  STD_LOGIC_VECTOR(3 downto 0);
-			AppSize : in  STD_LOGIC_VECTOR(3 downto 0);
-           packet_received : out  STD_LOGIC;
-           packet_ack : in  STD_LOGIC;
-           barrier_completed : out  STD_LOGIC;
-			  Ready : Out std_logic;
-			  AppInitReq :out  STD_LOGIC; -- requête d'initialisation de l'application
-			  AppInitAck :in  STD_LOGIC; -- Acquitement d'initialisation
-			  Initialized:in std_logic ; -- état de la Lib
-			  Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
-           switch_data_available : in  STD_LOGIC;			  
-           switch_port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           switch_port_out_rd_en : out  STD_LOGIC
-			  
-			  
-			  
-			  );
-end EX2_FSM;
-
-architecture Behavioral of EX2_FSM is
---module pour la lecture des données sur le réseau
-CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu
-component Proto_receiv is
- generic (sizemem : natural := 64);
- port (
- clk,reset : in std_logic;
- fifo_empty,fifo_full : in std_logic;
- rcv_start : in std_logic; --début de la réception
- rcv_ack :in std_logic;   -- acquittement de la réception
- rcv_comp : out std_logic; -- fin de la réception
-  pop : out std_logic:='0';
- fifo_out : in std_logic_vector(Word-1 downto 0);
- mem :out memory(0 to sizemem-1));
-end component Proto_receiv;
-
-COMPONENT SetBit
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		BitMask : IN std_logic_vector(7 downto 0);
-		BitVal : IN std_logic;
-		start : in std_logic;
-		whole : in std_logic;
-		done :  out std_logic;
-		dma_wr_grant : IN std_logic;
-		dma_rd_grant : IN std_logic;
-		Ram_data_in : out std_logic_vector(7 downto 0);          
-		dma_wr_request : OUT std_logic;
-		dma_rd_request : OUT std_logic;
-		ram_rd : OUT std_logic;
-		ram_wr : OUT std_logic;
-		ram_address : IN std_logic_vector(15 downto 0);
-		Ram_data_out : in std_logic_vector(7 downto 0)
-		);
-		End component SetBit;
---constante
-constant Max_stack : integer:=7;--Le nombre de GET qui peuvent être empilés
--- définition du type etat de la machine à etat
-type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, 
-fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4,
-ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3,
- Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,
-  ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy);
-type fsm_ack is(ack0,ack_readwait,ack_checkwait,ack1,ack2,ack3,ack4,ack5,ack6);
-type mem32 is array (natural range <>) of std_logic_vector (31 downto 0);
-signal Next_Ex2_state,ex2_state :fsm_states;
-signal ack_state,next_ack_state : fsm_ack;
---
-signal mode_get,match_get:std_logic:='0';
-signal mode_get_i,match_get_i:std_logic:='0';
--- machine a etat du module
-signal packet_type, packet_type_i : std_logic_vector(3 downto 0);
-signal P_len_i,P_len : std_logic_vector(Word-1 downto 0);
-signal barrier_counter,barrier_counter_i : std_logic_vector(3 downto 0);
-signal pading_data,data_to_ram,Data_to_ram_i :  std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal n,n_i : natural range 0 to 15;
-signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0');
-signal data_to_write_fifo,data_to_write_fifo_i :  std_logic_vector(Word-1 downto 0);
---*******************************************
---signaux pour la fonction SetBit
-signal		sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
-signal		sb_BitVal,sb_start,sb_done : std_logic:='0';
-signal  sb_whole : std_logic:='0'; --écrire le mot entier
-signal		sb_Ram_data_in : std_logic_vector(7 downto 0);          
-signal		sb_dma_wr_request :  std_logic;
-signal		sb_dma_rd_request :  std_logic;
-signal		sb_ram_rd : std_logic;
-signal		sb_ram_wr : std_logic;
-signal		sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
-signal		sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
--- deuxième module pour set busy bit
-signal Set_Wbusy : std_logic:='0'; --choix du Mux
-signal	GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl
-
---*********************************************
-signal Ex2_on : std_logic:='0';
-signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
-signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement
-signal  dest_ack,dest_ack_i:std_logic_vector(3 downto 0) :=(others=>'0');
-signal  to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal Result_i,result1 :  STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0');
---signaux pour l'untilisation du composant de réception 
-signal rfifo_empty,rfifo_full:std_logic;
-signal rcv_start,rcv_comp,rcv_ack:std_logic;
-signal rpop:std_logic;
-signal initreq,initreq_i:std_logic:='0'; --Requete d'initialisation
---signal mem:memory(0 to Msize-1));
---jusqu'à 16 Get peuvent être attendus!
-signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés
-signal WStart,WPost,WBUSY, WBUSY_i,RGET,RGET_i: std_logic:='0'; --
-signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(Max_Stack downto 0):=(others=>'0');
-signal Waited_Get,Waited_Get_i : mem32(0 to Max_stack);
-Signal Rec_Data_i : Typ_PortIO(0 to 3);
-signal Get_Instr,Get_instr_i,Put_instr,Put_instr_i :memory(0 to 8);
-signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0');
-signal P_G,P_G_i: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get
-signal Ptr_Get,Ptr_Get_i : natural range 0 to Max_stack:=0;
-signal Received_get,Received_get_i : std_logic_vector(Max_stack downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu
-begin
-
-ram_address <= ack_address when instr_ack='1' else dest_address;
---fifo_data <= data_to_write_fifo;
-Result<=Result1;
-p_instr_fifo:process(ack_state,data_to_write_fifo_i,wr_ack,to_fifo_ack,instr_ack)
-begin
-  if instr_ack='1' then
-    fifo_data<=to_fifo_ack;
-else
-  fifo_data<=data_to_write_fifo_i;
-end if;
-end process p_instr_fifo;
-
-
-
-R0:proto_receiv generic map (sizemem =>4)
-	port map (
-	clk=>clk,
-	reset=>reset,
-	rcv_start=>rcv_start,
-	rcv_comp=>rcv_comp,
-	rcv_ack=>rcv_ack,
-	fifo_empty=>rfifo_empty,
-	fifo_full=>rfifo_full,
-	fifo_out=>switch_port_out_data,
-	pop=>rpop,
-	mem=>open
-	
-	);
---envoie de l'acquittement
-setbit1:SetBit
-	PORT MAP (
-		clk =>clk,
-		reset =>reset,
-		BitMask =>sb_bitMask,
-		BitVal =>sb_bitval,
-		dma_wr_grant =>dma_wr_grant,
-		dma_rd_grant =>dma_rd_grant,
-		Ram_data_in => sb_Ram_data_in,         
-		dma_wr_request =>sb_dma_wr_request,
-		dma_rd_request =>sb_dma_rd_request,
-		ram_rd =>sb_ram_rd,
-		ram_wr =>sb_ram_wr,
-		ram_address =>dest_address,
-		Ram_data_out =>sb_ram_data_out,
-		Start =>sb_start,
-		whole=>sb_whole,
-		done =>sb_done
-		);
-
--- processus de transistion entre les etats 
-ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized,
- switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len,
- sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter,
- dest_ack,rec_wpost,Gcomp,rec_data,mode_get,match_get,Instr_ack,result1,data_to_write_fifo)
-variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
-variable tempval : std_logic_vector(Word-1 downto 0);
-variable n_e,i:natural range 0 to 15 :=0;
-
---=================================================================-
-procedure read_nocdat_fsm(sdata_avail: std_logic;
-signal rd,wr:out std_logic;
-signal Plen_i : in std_logic_vector(Word-1 downto 0);
-signal Plen_o : out std_logic_vector(Word-1 downto 0);
-variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is
---lit la suite des données qui sont dans le NoC et identifie le paramètre important
-begin
-if n_e<3 then 
-			                 wr<='0';
-											if sdata_avail='1' then
-												n:=n_e+1;
-												rd<='1';
-												plen_o <=plen_i-1;
-											else
-												rd<='0';
-											end if;
-											--result_i<=(others=>'0');
-										elsif n_e=3 then
-											if sdata_avail='1' then
-												n:=n_e+1;
-												rd<='0';
-												--P_len <=P_len_i -1;
-												--data_to_ram<=sportdout;
-												--Result_i<=sport_out_data;
-											else
-												rd<='0';	
-											end if;
-										end if;
-end procedure;
-
-begin
- 
-	Next_Ex2_state <= Ex2_state;
-	Ex2_on<='0';
-	sb_whole<='0';
-	sb_start<='0'; --valeur par défaut
-	sb_bitmask<=x"FF";
-	sb_bitval<='1';
-	dma_rd<='0';
-	dma_wr<='0';
-	rd_ok<='0';
-	wr_ok<='0';
-	barrier_counter_i <= barrier_counter;
-  GPost_Set_i<=GPost_Set;
-  Rec_WPost_i<=Rec_WPost;
-  GPost_i<=GPost;
-  P_G_i<=P_G;
-  RGET_i<=RGET;
-  WBUSY_i<=WBUSY;
-  Result_i<=Result1;
-  Ptr_get_i<=Ptr_get;
-  mode_get_i<=mode_get;
-  data_to_write_fifo_i<=data_to_write_fifo;
-  match_get_i<=match_get;
-  GComp_i<=GComp;
-  Instr_ack_i<=Instr_ack;
-  received_get_i<=received_get;
-  mode_get_i<=mode_get;
-  InitReq_i<=InitReq;
-  match_get_i<=match_get;
-  Data_to_ram_i<=Data_to_ram;
-  dest_address_i<=dest_address;
-   for i in 0 to Max_stack loop 
-  Waited_get_i(i)<=Waited_get(i);
-  end loop;
- For i in 0 to 7 loop
-			Get_Instr_i(i)<=Get_instr(i);
-	  end loop;
-		Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
-		  n_i<=n; --valeur par défaut de n_i
-		  P_len_i<=P_len;
-		  for i in 0 to 3 loop 
-	  Rec_Data_i(i)<=Rec_Data(i);
-		Packet_type_i<=Packet_type;
-		dest_ack_i<=dest_ack;
-	  end loop;
-		  case ex2_state is
-		   when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then
-        		        Next_Ex2_state  <= fetch_packet_type;
-                    		     end if;
-                    		     rd_ok<='0';wr_ok<='0';
-			 when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1'  then 	--and initialized ='1'						
-											      Next_Ex2_state  <= decode_packet_type;
-											      packet_type_i<=switch_port_out_data(7 downto 4);
-											      Dest_ack_i<=switch_port_out_data(3 downto 0);
-											      Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue !
-											      rd_ok<='1';
-									         else
-											      --Next_Ex2_state <= Ex2_Ready;
-											      rd_ok<='0';
-								           end if;
-								           n_i<=0;
-			when decode_packet_type => rd_ok<='0';
-			                 if switch_data_available ='0' then
-													Next_Ex2_state <= decode_packet_type;
-												else
-												    rd_ok<='1';
-												    Rec_Data_i(1)<=switch_port_out_data-2;
-													 if packet_type = MPI_PUT then
-													    P_len_i <= switch_port_out_data - 2;
-														  n_i<=0;
-														  
-														 Next_Ex2_state <= decode_packet_type2;
-													  elsif packet_type = MPI_GET then
-													    P_len_i <=switch_port_out_data-2;
-														 Next_Ex2_state <= decode_packet_type2;
-													  elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
-													    P_len_i <= switch_port_out_data;
-														 n_i<=0;
-														 Next_Ex2_state <= ex2_barrier1;
-													  elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
-													   n_i<=0;
-													   wr_ok<='0';
-													   --rd_ok<='1';
-														P_len_i <= switch_port_out_data-2;
-														Rec_Data_i(1)<=switch_port_out_data;
-														Next_Ex2_state <= ex2_init1;
-														 elsif packet_type = MPI_ACK then
-													   n_i<=0;
-													   wr_ok<='0';
-													   rd_ok<='0';
-														P_len_i <= switch_port_out_data-2;
-														Next_Ex2_state <= ex2_ack1;
-														elsif packet_type = MPI_WIN_SYNC then
-													   n_i<=0;
-													   wr_ok<='0';
-													   rd_ok<='0';
-														P_len_i <= switch_port_out_data-2;
-														Next_Ex2_state <= ex2_Wsync;
-													  elsif packet_type = MPI_SPAWN  then
-													    Next_Ex2_state <= ex2_spawn1;
-													    wr_ok<='0';
-													   rd_ok<='0';
-													  else
-														  Next_Ex2_state <= decode_packet_type;
-														  rd_ok<='0';
-													 end if;
-												end if;
-			when decode_packet_type2 => if packet_type = MPI_PUT then
-													Next_Ex2_state <= fetch_addresses;
-												  else
-												 	Next_Ex2_state <= ex2_get1;							  
-							               end if;        									
-         when fetch_addresses => if  n=0 then
-                               if switch_data_available = '1'  then
-												            dest_address_i(15 downto 8) <= switch_port_out_data;
-												            Rec_data_i(2)<=switch_port_out_data;												             
-												              n_i <= n + 1;
-												                  rd_ok<='1';
-												        else
-												                  rd_ok<='0';												        												             
-												        end if;												      
-												       elsif n=1 then 
-												            if switch_data_available = '1'  then
-												              dest_address_i(Word-1 downto 0) <= switch_port_out_data;
-												                Rec_data_i(3)<=switch_port_out_data;
-												                P_len_i <= P_len - 2;	
-												                Next_Ex2_state <= ex2_put1;
-												                n_i<=0;
-												                rd_ok<='1';
-												                else
-												                  rd_ok<='0';
-												                    Next_Ex2_state <= fetch_addresses;
-								                        end if;	
-								               end if;	
- when ex2_ack1 =>  rd_ok<='0';
-                  if n<2 then --réception de l'acquittement.
-                    n_e:=n;
-                	   read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n);
-                	   n_i<=n_e;
-              	   elsif n=2  then
-              	     	if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												
-												data_to_ram_i<=switch_port_out_data;
-												Result_i<=switch_port_out_data;	
-											end if;
-              	     
-              elsif n=3 then
-              	     n_i<=n+1;P_G_i<=0;
-                    if data_to_ram(7 downto 4)=MPI_PUT then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16));
-														wr_ok<='1';
-														P_G_i<=1; --put ou get
-														P_len_i<=x"06"; --longueur de l'entête à parcourir
-												elsif	data_to_ram(7 downto 4)=MPI_GET then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														P_G_i<=2; --put get
-														P_len_i<=x"06";--taille de l'instruction en mémoire
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16));
-												elsif data_to_ram(7 downto 4)=MPI_SPAWN then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16));
-												elsif data_to_ram(7 downto 4)=MPI_INIT then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16));		
-														wr_ok<='1'; --
-														-- 
-												else 
-														Result_i<="00000000";
-														wr_ok<='0'; --
-														n_i<=n; --code inconnu !
-												end if;
-										elsif n=4 then
-										  if P_G=1 or P_G=2 then
-										    Next_ex2_state<=ex2_ack2;
-										   else
-										      Next_ex2_state<=ex2_ack3;
-										   end if;
-										   n_i<=0;
-										end if;
-          								               		
-            when Ex2_ack2 =>if unsigned(p_len)>0 then
-                        If Dma_rd_grant='1' then
-			                  if n=0  then
-												  n_i<=n+1; --cycle d'attente pour la RAM
-												elsif n=1 then 
-												  dest_address_i <= dest_address+1; 
-												  n_i<=2;
-												elsif n>=2 then
-											
-													    --creer un délai sur ces signaux par rapport à src_adress
-													     
-                          n_i<=n+1;
-                          rd_ok<='1';
---                          if n>1 then
-													dest_address_i <= dest_address+1; 
-													p_len_i <= p_len - 1;
-													--end if;
-													Get_Instr_i(n-2)<=Ram_data_out; --deux cycles de retard
-													Next_ex2_state <= ex2_ack2;
-												end if;	
-												end if;
-												dma_rd<='1';
-												rd_ok<='1';	
-												else
-												  if P_G=1 then
-												    dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16));
-												  else
-												    dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16));
-													Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id
-													Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur
-													Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas
-													Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut
-													RGET_i<='1';									
-													
-													Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter
-													end if;
-													Next_ex2_state <= ex2_ack3;
-													n_i<=0; --suite du process ack
-													rd_ok<='0';
-													dma_rd<='0';
-												end if;
-   
-when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction
-            	     sb_start<='1';
-            	     sb_bitMask<=x"20";--cinquième bit à un
-            	     sb_bitval<='1';
-            	     sb_whole<='0';--Modifier un seul bit !
-            	     if sb_done='1' then
-            	       n_i<=1;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-            	       dest_address_i<=dest_address+1;
-        	       end if;
-	       
-	       elsif n=1 then
-	                sb_start<='1';
-            	     sb_bitMask<=Rec_Data(2);
-            	     sb_bitval<='1';
-            	     sb_whole<='1'; 
-            	     if sb_done='1' then
-            	       n_i<=n+1;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-            	       sb_whole<='0';
-        	       end if;
-
-	        elsif n=2 then
-	             Next_Ex2_state<=Ex2_Ready;
-	             n_i<=0;
-            end if;
-            
-    when ex2_Wsync =>  rd_ok<='0';
-                  if n<2 then --réception de la synchronisation.
-                    n_e:=n;
-                	   read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n);
-                	   n_i<=n_e;
-              	   elsif n=2  then
-              	     	if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												
-												data_to_ram_i<=switch_port_out_data;
-												Result_i<=switch_port_out_data;	
-											end if;
-              	     
-              elsif n=3 then
-              	     n_i<=n+1;P_G_i<=0;
-                    if data_to_ram(7 downto 4)=SYNC_WSTART then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
-														wr_ok<='1';
-														P_G_i<=1; --put ou get
-														P_len_i<=x"06"; --longueur de l'entête à parcourir
-												elsif	data_to_ram(7 downto 4)=SYNC_WPOST then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														P_G_i<=2; --put get
-														P_len_i<=x"06";--taille de l'instruction en mémoire
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
-												elsif data_to_ram(7 downto 4)=SYNC_WWAIT then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16));
-												elsif data_to_ram(7 downto 4)=SYNC_WCOMP then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));		
-														wr_ok<='1'; --
-														Next_Ex2_State<=Ex2_WCOMP;
-														n_i<=0;
-												else 
-														Result_i<="00000000";
-														wr_ok<='0'; --
-														n_i<=n; --code inconnu !
-												end if;
-										
-										end if;  
-          when Ex2_Wcomp => dma_rd<='1';
-                        rd_ok<='1';	
-                        
-			                  if n=0  then
-												  n_i<=n+1; --cycle d'attente pour la RAM
-												  i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-													 GComp_i(i)<='1';
-												elsif n=1 then 
-												  dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));
-												  If Dma_rd_grant='1' then
-												  n_i<=2;
-												  end if;
-												elsif n=2 then
-											      If Dma_rd_grant='1' then
-													    --creer un délai sur ces signaux par rapport à dest_adress							     
-                                n_i<=n+1;
-                                rd_ok<='1';
-													       dest_address_i <= dest_address+1; 
-													       GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard
-													       
-													 else
-													   n_i<=1;
-													  end if;
-													elsif n=3 then
-													  If Dma_rd_grant='1' then
-													  --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed
-													 n_i<=n+1;
-													 rd_ok<='1';
-													 dma_rd<='1';
-													 end if;
-													elsif n=4 then
-													  --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed
-
-													 rd_ok<='1';
-													 dma_rd<='1';	
-													 n_i<=n+1;	
-													 elsif n=5 then		
-													 rd_ok<='0';
-													 dma_rd<='0';										 
-													n_i<=0;
-													If GPost=GComp then --le même nombre de post que de COmpleted ?
-													GPost_Set_i<='1';
-													end if;
-
-													Next_ex2_state <= ex2_set_busy;
-												end if;	
-												
-												          
-			when ex2_init1 => if n<2 then 	-- execution du mpi Init
-			                 wr_ok<='0';
-											if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												P_len_i <=P_len-1;
-												Rec_Data_i(n+2)<=switch_port_out_data;
-												data_to_ram_i<=switch_port_out_data;
-												Result_i<=switch_port_out_data;
-											else
-												rd_ok<='0';
-												n_i<=n;
-											end if;
-											result_i<=(others=>'0');
-										elsif n=2 then
-												n_i<=n+1;
-												rd_ok<='0';
-
-										elsif n=3 then 
-										  rd_ok<='0'; -- normalement plus rien à lire
-										  n_i<=n+1;
-											if Initialized='1' then
-												if data_to_ram(7 downto 4)=INIT_SEEKMAIN then
-														Result_i<=data_to_ram;
-														InitReq_i<='1'; --permet d'activer Init de Ex_4
-												elsif	data_to_ram(7 downto 4)=INIT_STAT then
-														Result_i<=data_to_ram;
-														InitReq_i<='1'; --permet d'activer Init de Ex_4
-												elsif data_to_ram(7 downto 4)=INIT_REGISTER then
-														Result_i<=data_to_ram;
-														InitReq_i<='0'; --permet d'activer Init de Ex_4
-														report "Mise à jour des données d'initialisation";
-														Next_Ex2_state<=ex2_ready;
-														n_i<=0;
-												elsif data_to_ram(7 downto 4)=INIT_SPAWN then
-														Result_i<=data_to_ram;
-														InitReq_i<='1'; --permet d'activer Init de Ex_4
-														-- il faut mettre à jour l'état de Spawn
-												else 
-														Result_i<="00000000";
-														InitReq_i<='0'; --permet d'activer Init de Ex_4
-												end if;
-											end if;
-											elsif n=4 then 
-										    n_i<=n+1;
-										  elsif n=5 then
-												if p_len=0 then 
-													Next_Ex2_state<=ex2_init2;
-													rd_ok<='0';
-												else
-													p_len_i <=p_len -1;
-													rd_ok<='1'; --vider le tampon de lecture pour ce paquet !
-												end if;
-											
-										end if;
-			when ex2_init2=>  if n=5 then 
-			                         if AppInitAck='1' then
-											             n_i<=n+1;
-											             InitReq_i<='0';
-											             Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init
-											         end if;
-											     elsif n=6 then 
-											         	Next_Ex2_state<=Ex2_Ready;
-												        n_i<=0;
-												        InitReq_i<='0';
-											     end if;
-										
-			when ex2_put1 => rd_ok<='0'; --ne  pas autoriser la lecture du switch
-			                 wr_ok<='0';
-			                 dma_rd<='1';
-			                 if n=0 then
-		                if RGET='1' then
-									Lp:	  for i in 1 to Max_stack loop  -- to Ptr_get normalement
-										  if i<=Ptr_Get then
-										  if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and
-										    waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and
-										    waited_get(i-1)(23 downto 16)=rec_data(2) and
-											   waited_get(i-1)(31 downto 24)=rec_data(3) then
-                          if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then
-		
-             													match_get_i<='1';
-                          end if;
-                        else
-                      
-										      end if;
-										 end if;
-										exit Lp when i= Ptr_get;
-										end loop Lp;
-										end if;
-											
-			                   n_i<=1;
-			                 elsif n=1 then
-			                   if match_get='1' then 
-			                     n_i<=3; --ne pas envoyer ack dans ce cas
-			                     report "GET Détecté ACK pas envoyé dans Ex2 du HCL n°" & image(pid);
-			                     else
-			                       n_i<=2;
-			                    end if;
-			                 elsif n=2 then
-			                   	 instr_ack_i<='1'; --activer  l'envoie de l'accusé de réception
-			                   	 data_to_write_fifo_i<=to_fifo_ack;
-			                   	 wr_ok<=wr_ack;
-			                   	 if sent_ack='1' then
-			                   	   n_i<=2;
-			                   	   instr_ack_i<='0';
-			                   	   dma_wr<='1';
-			                   	  end if;
-			                   	  
-			                   	elsif n=3 then
-			                   	  dma_wr<='1';
-			                   	if dma_wr_grant = '1' then
-  										          Next_Ex2_state <= ex2_put2;
-  										          data_to_ram_i<=switch_port_out_data;
-  										          rd_ok<='0';
-  										          n_i<=0;
-  										          delai:=0;
-										  	   else
-										          Next_Ex2_state <= ex2_put1;
-								          end if;
-								          end if;	
-			when ex2_put2 =>	rd_ok<='0';
-			                 n_i<=1;
-			                 i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-			                 --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-			               if unsigned( P_len) > 0  then 
-												
-											if switch_data_available = '1' and delai=0  then
-													   delai:=1; --une donné lue
-														 P_len_i <= P_len - 1;
-														 Next_Ex2_state <= ex2_put2;
-														 rd_ok<='1';
-														 data_to_ram_i<=switch_port_out_data;
-											end if;
-											if  dma_wr_grant='1' and delai=1 then
-											 -- if n=1 then
-													  wr_ok<='1';
-													  dest_address_i <= dest_address + 1;
-													  delai:=0;--une donnée écrite
-											--	else
-											--	    dest_address_i <= dest_address ;
-											--	end if;
-														--if delai=1 then 
-														--data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
-														--end if;
-														 
-												else
-												  dest_address_i<=dest_address;
-												  wr_ok<='0';
-												  n_i<=0;
-												end if;
-											
-													Next_Ex2_state <= ex2_put2;
-										
-										else 
-										  rd_ok<='0';
-										  
-
-											if dma_wr_grant='1' and n=1 then 
-
-												 Next_Ex2_state <= ex2_put3;
-												Wr_ok<='0';
-												 n_i<=0;
-											 end if;
-									    end if;
-									 
-			when ex2_put3 =>			if dma_rd_grant='1' then 
-													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-													Next_Ex2_state <= ex2_put4;
-													n_i<=0;
-													rd_ok<='1';
-													wr_ok<='0';
-												end if;
-			
-			when ex2_put4 => if  n>0 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-										if n=0 then
-										  if RGET='1' then
-									L1:	  for i in 1 to Max_stack loop  -- to Ptr_get normalement
-										  if i<=Ptr_Get then
-										  if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and
-										    waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and
-										    waited_get(i-1)(23 downto 16)=rec_data(2) and
-											   waited_get(i-1)(31 downto 24)=rec_data(3) then
-                          if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then
-                          received_get_i(i-1)<='1';
-             													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-             													mode_get_i<='1';
-             													match_get_i<='1';
-                          end if;
-                        else
-                      
-										      end if;
-										 end if;
-										exit L1 when i= Ptr_get;
-										end loop L1;
-										end if;
-											
-											n_i<=n+1;
-											rd_ok<='1';
-											wr_ok<='0';
-											
-											elsif n=1 then
-											 if match_get='0' then
-											   i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-											  Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-                      end if;
-												if dma_rd_grant='1' then 
-												if RGET='1' then --si on est en mode attente d'un Get
-												RGET_i<='0';  --Supposons tous les Gets reçus !
-                        test_wcomp:for i in 1 to Max_stack loop --Tous les Get reçus ?
-                          if Ptr_get>=i then
-                          if received_get(i-1)='0' then
-                            RGET_i<='1';    --Non !
-                        end if;
-                      end if;
-								exit test_wcomp when i=Ptr_get;
-                        end loop test_wcomp;
-                       
-                      end if;
-													n_i<=n+1;
-													rd_ok<='1';
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												end if;
-											elsif n=2 then
-												if dma_rd_grant='1' and dma_wr_grant='1' then 
-													n_i<=n+1;
-													tempval:=Ram_data_out;
-													tempval(4):='1';			--SET du bit DReceived
-												  if Mode_Get='1' then                    --si get ack est détecté
-													   tempval(6):=RGET;  -- Bit 6  Busy=0 si dernier get reçu !!
-													   mode_get_i<='1';
-													end if;
-													data_to_ram_i<=tempval;
-													rd_ok<='0';
-													wr_ok<='1';
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												n_i<=0;
-												end if;
-											elsif n=3 then
-												if dma_wr_grant='1' then
-													rd_ok<='0';
-													wr_ok<='1';
-													n_i<=n+1;
-												end if;
-											elsif n=4 then
-												if dma_wr_grant='1' then
-													rd_ok<='0';
-													wr_ok<='1';
-													
-													n_i<=5;
-												end if;
-										 elsif n=5 then
-										     Next_Ex2_state <= ex2_set_busy;
-										     n_i<=0;
-										     rd_ok<='0';
-													wr_ok<='0';
-													mode_get_i<='0';
-													match_get_i<='0';
-											end if;
-											
-										 
-								  
-									--	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
-			when ex2_put5 => 
-										   Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put
-										
-			when ex2_spawn1 => 
-											
-											if n<2 then
-											 n_e:=n;
-											read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n);	
-											n_i<=n_e;
-											Rec_Data_i(2)<=Switch_port_out_data;
-											elsif n=2 then
-											    Rec_Data_i(3)<=Switch_port_out_data;
-													Result_i<=Switch_port_out_data;
-													Data_to_ram_i<=Switch_port_out_data;
-													n_i<=n+1;
-													rd_ok<='1';
-											elsif n=3 then
-												if data_to_ram(7 downto 4)=SPAWN_LOAD then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --permet d'activer Init de Ex_4
-												elsif	data_to_ram(7 downto 4)=SPAWN_COMP then
-														Result_i<=data_to_ram;
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-
-												elsif	data_to_ram(7 downto 4)=SPAWN_ERR then
-														Result_i<=data_to_ram;
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-												else
-														Result_i<=(others=>'0');
-													
-												end if;
-												n_i<=n+1;
-												rd_ok<='0';
-											elsif n=4 then	
-											     wr_ok<='1';
-														if AppInitAck='1' then
-															wr_ok<='0';
-															rd_ok<='0';
-															n_i<=n+1;
-														end if;
-											elsif n=5 then
-															wr_ok<='0';
-															rd_ok<='0';
-															n_i<=0;
-												Next_Ex2_state <=Ex2_Ready;
-											end if;
-			when Ex2_Spawn2=> 
-			               Next_Ex2_state <=Ex2_Ready;
-			when ex2_get1 =>  rd_ok<='0'; --ne  pas autoriser la lecture du switch
-			                 --ack_state<=next_ack_state; --MAE d'envoie de AR
-			                 dma_rd<='1';
-			                 if n=0 then
-			                   	 instr_ack_i<='1'; --activer  l'envoie de l'accusé de réception
-			                   	 data_to_write_fifo_i<=to_fifo_ack;
-			                   	 wr_ok<=wr_ack;
-			                   	if sent_ack='1' then
-			                   	   n_i<=1;
-			                   	   instr_ack_i<='0';
-			                   	   wr_ok<='0';
-			                   	   --if switch_data_available='1' then
-			                   	   rd_ok<='0';--
-			                   	   --P_len<=P_len-1;
-			                   	   --end if;
-			                   	  end if;
-			                   	  
-			                   	elsif n=1 then
-			                   	if   switch_data_available='1' then
-			                   	if fifo_full = '0' then  -- conversion du get en put en empilement dans le fifo
-										    	     data_to_write_fifo_i <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put						       	 
-											         wr_ok<='1';
-											         rd_ok<='1'; --autoriser la lecture du crossbar
-											         P_len_i<=P_len-1;
-											         n_i<=n+1;
-											     else
-											       Wr_ok<='0';
-											       Rd_ok<='0';
-								        	  end if;	
-								        	  else
-								        	    Wr_ok<='0';
-								        	    rd_ok<='0';
-								        	  end if;
-								        	 elsif n=2 then
-								        	  if   switch_data_available='1' then
-								        	   if fifo_full = '0' then  -- conversion du get en put en empilement dans le fifo
-										    	     --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put						       	 
-											       	--P_len_i <= P_len-1;--le nombre d'octet qui restent à copier
-											       	 Next_Ex2_state <= ex2_get2;
-											         wr_ok<='0';
-											         rd_ok<='0'; --autoriser la lecture du crossbar
-											         n_i<=0;
-											       else
-											         rd_ok<='0';
-											         wr_ok<='0';
-											      end if;
-											     else
-											         rd_ok<='0';
-											         wr_ok<='0';
-								        	  end if;	
-								      end if;
-			when ex2_get2 => if P_len>0 then 
-			                 if fifo_full = '0' and switch_data_available ='1' then
-  										        data_to_write_fifo_i <= switch_port_out_data;--la longueur initiale du GET
-  											     p_len_i <= P_len - 1;
-  										        Next_Ex2_state <= ex2_get2;
-  											     wr_ok<='1';
-  											     Rd_ok<='1';
-										    elsE
-										         
-											         wr_ok<='0';
-											         Rd_ok<='0';
-											 END IF;
-										  else
-										  if n=0 then
-										   if fifo_full='0' then
-											 wr_ok<='0';--une impulsion en plus
-											 n_i<=n+1;
-											 Next_Ex2_state <= ex2_get2;
-											 else
-											  wr_ok<='0';
-											end if;
-											
-											else
-											  Next_Ex2_state <= ex2_get3;
-											  n_i<=0;
-											  wr_ok<='0';
-											 end if;
-											rd_ok<='0';
-								    end if;
-								    i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-			               Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-
-								    --préparer en avance l'adresse de lecture/écriture
-								    dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-		   when ex2_get3 => wr_ok<='0';
-		                    if dma_rd_grant='1' then -- fin du mpi_get
-										   Next_Ex2_state <= ex2_get4;
-											n_i<=0;
-											--activer le bit sending du registre de transfert
-										  else
-											Next_Ex2_state <= ex2_get3;
-								      end if;
-											
-										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-			when ex2_get4 => if n <4 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-											if n=0 then
-												if dma_rd_grant='1' then
-												n_i<=n+1;
-												
-												end if;
-												rd_ok<='1';
-												wr_ok<='0';
-											elsif n=1 then
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-												  data_to_ram_i<=Ram_data_out;
-											elsif n=2 then
-													if dma_rd_grant='1' and dma_wr_grant='1' then
-														n_i<=n+1;
-														tempval:=Ram_data_out;
-														--tempval(2):='1';  	--mise à 1 du Bit DSending
-														--tempval(5):='0'; 		--Mise à 0 du Bit Sent
-														data_to_ram_i(2)<='1';  	--mise à 1 du Bit DSending
-														data_to_ram_i(5)<='0'; 		--Mise à 0 du Bit Sent
-
-														data_to_ram_i<=tempval;
-														rd_ok<='1';
-														wr_ok<='0';
-													else
-													rd_ok<='1';
-													wr_ok<='0';
-													n_i<=0;
-												end if;
-											
-											  
-											elsif n=3 then
-												if dma_wr_grant = '1' then
-												n_i<=n+1;
-												rd_ok<='0';
-												wr_ok<='1';
-												end if;
-											elsif n=4 then
-											  if dma_wr_grant = '1' then
-													n_i<=0;
-													Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get
-											  else
-													rd_ok<='0';
-													wr_ok<='1';
-													--n<=n-1;
-											 end if;
-											end if;
-										   
-										 
-										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-					when ex2_Set_Busy => if n=0 then --set busy bit of the instruction
-            	             dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-                          n_i<=1;
-                              if Gpost_Set='1' then
-                                if  (rec_wpost=gpost) and RGET='0' then
-                                    Wbusy_i<='0';
-                                    Gpost_Set_i<='0';
-                                    GComp_i<=(others=>'0');
-                                    rec_wpost_i<=(others=>'0');--reset des messages reçu
-                                else
-                                    Wbusy_i<='1';
-                                end if;
-                            else
-                                
-                                n_i<=2;
-                              end if;
-                              if RGET='1' then 
-                                  WBusy_i<='1';
-                             end if;
-          	     elsif n=1 then
-            	     sb_start<='1';
-            	     sb_bitMask<=x"40";--6e bit à 1
-            	     sb_bitval<=WBusy;
-            	     if sb_done='1' then
-            	       n_i<=2;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-        	       end if;
-	       elsif n=2 then
-	             Next_Ex2_state<=Ex2_Ready;
-	             n_i<=0;
-            end if;
-								-- execution du barrier
-			when ex2_barrier1 => if switch_data_available = '1' then
-												 pading_data <= switch_port_out_data;
-												 Next_Ex2_state <= ex2_barrier2;
-											  else
-											    Next_Ex2_state <= ex2_barrier1;	
-											 end if;	
-			when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then
-												 barrier_counter_i <= barrier_counter + 1;
-												 Next_Ex2_state <= ex2_barrier4;	
-											  else
-											    Next_Ex2_state <= ex2_barrier3;	
-											 end if;	
-			when ex2_barrier3 => if n < 10 then
-												 n_i<= n + 1;
-												 Next_Ex2_state <= ex2_barrier3;	
-											  else
-											    Next_Ex2_state <= Ex2_Ready;	
-											 end if;	
-			when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED 
-												 data_to_write_fifo_i <= MPI_BARRIER_COMPLETED & "0000";
-												 Next_Ex2_state <= ex2_barrier5;	
-											  else
-											    Next_Ex2_state <= Ex2_Ready;	
-											 end if;	
-			when ex2_barrier5 => if fifo_full = '0' then  -- taille du packet MPI_BARRIER_COMPLETED
-												 data_to_write_fifo_i <= "00000011";
-												 Next_Ex2_state <= ex2_barrier6;	
-											  else
-											    Next_Ex2_state <= ex2_barrier5;	
-											 end if;		
-			when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
-												 data_to_write_fifo_i <= "00000000";
-												 Next_Ex2_state <= ex2_barrier7;	
-											  else
-											    Next_Ex2_state <= ex2_barrier6;	
-											 end if;				
-			when ex2_barrier7 => if fifo_full = '0' then
-												 barrier_counter_i <= "0000";
-												 Next_Ex2_state <= Ex2_Ready;	
-											  else
-											    Next_Ex2_state <= ex2_barrier7;	
-											 end if;				
-			
-			when others => Next_Ex2_state <= Ex2_Ready;
-		   end case;
-        
- end process;
- 
- -- sortie de la machine à etat
---
- ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr,
- switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request,
- appInitAck,n,InitReq)
-  variable transact : std_logic_vector(Word-1 downto 0);
-  begin   
--- code fonctionnel	
-	sb_ram_data_out<=Ram_data_out; --presque toujours cette valeur
-	case Ex2_state is
-		when  Ex2_Ready => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='1';
-										  AppInitReq<='0';
-		when  fetch_packet_type => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='0';
-										  AppInitReq<='0';
-										  
-								  
-		when decode_packet_type => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when decode_packet_type2 => fifo_wr_en <= '0';
-										    switch_port_out_rd_en <= '0';
-										    packet_received <= '0'; 
-										    dma_wr_request <= '0';
-										    dma_rd_request <= '0';
-										    Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										    barrier_completed <= '0';
-										    AppInitReq<='0';	
-											Ready<='0';
-		when fetch_addresses =>  fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		when ex2_ack1 |ex2_Wsync =>		  
-										Ready<='0';
-										switch_port_out_rd_en<=rd_ok;
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;
-				when ex2_ack2|Ex2_WCOMP =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= dma_rd;
-										dma_wr_request <= '0';
-										Ram_rd<=rd_ok;
-										Ram_wr<='0';
-										Ram_data_in<=(others=>'0');
-			when ex2_ack3 =>		  
-										Ready<='0';
-										switch_port_out_rd_en<=rd_ok;
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;							
-		when ex2_put1 =>  fifo_wr_en <= wr_ok;
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= dma_wr;
-										  dma_rd_request <= dma_rd;
-										  Ram_rd<='1';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when  ex2_put2 =>   Ready<='0';
-										fifo_wr_en <= '0';
-										switch_port_out_rd_en <=rd_ok;
-									   
-										if rd_ok = '1' then
-										
-										 Ram_data_in<=switch_port_out_data;
-										else
-											Ram_data_in<=data_to_ram;
-										end if;
-										Ram_wr<=wr_ok;
-										Ram_rd<='0';
-										packet_received <= '0';
-										dma_rd_request <= '0'; 
-										dma_wr_request <= '1';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-		when  ex2_put3 => 	 Ready<='0';
-										fifo_wr_en <= '0';
-									   switch_port_out_rd_en <='0';	
-										--ne pas corrompre le contenu de la RAM
-										--Ram_data_in<=data_to_ram; 					
-										Ram_wr<='0';
-										Ram_rd<='1';
-										packet_received <= '0';
-										dma_rd_request <= '1'; 
-										dma_wr_request <= '0';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-										Ram_data_in<=(others=>'0');
-		
-		when ex2_put4 =>    fifo_wr_en <= '0';
-										Ready<='0';
-										switch_port_out_rd_en <= '0';
-										 packet_received <= '1'; 
-										 dma_rd_request <= dma_rd;
-										 dma_wr_request <=dma_wr;
-										 Ram_wr<=wr_ok;
-										 Ram_rd<=rd_ok;
-										 AppInitReq<='0';	 
-										 barrier_completed <= '0';	
-										 Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution 
-											
-		when ex2_put5 =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								        packet_received <= '1';
-								        AppInitReq<='0';
-								        barrier_completed <= '0';
-								        dma_rd_request <= dma_rd;
-										dma_wr_request <= dma_wr;
-										Ram_rd<=rd_ok;
-										Ram_wr<=wr_ok;
-										Ram_data_in<=data_to_ram;
-										--Result <=(1=>'1',others=>'0'); --put completed								  
-		
-		when ex2_get1=>   fifo_wr_en <= wr_ok;
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= dma_rd;
-										  Ram_rd<='1';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when ex2_get2 =>	     										    
-											 switch_port_out_rd_en <=rd_ok;
-										  fifo_wr_en <= Wr_ok;
-										  Ready<='0';
-										  packet_received <= '0';
-										  dma_rd_request <= '0'; 
-										  dma_wr_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0'; 
-										  AppInitReq<='0';	
-										    
-		when ex2_get3 =>      		fifo_wr_en <= '0';
-										Ready<='0';
-										switch_port_out_rd_en <= '0';
-										 packet_received <= '1'; 
-										 dma_rd_request <= '1';
-										 dma_wr_request <='0';
-										 Ram_wr<='0';
-										 Ram_rd<='1';
-										  AppInitReq<='0';	
-										  barrier_completed <= '0';
-										Ram_data_in<=(others=>'0');
-										 --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
-											
-		when ex2_get4 =>		  
-										Ready<='0';
-										barrier_completed <= '0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								        packet_received <= '1';
-								        AppInitReq<='0';
-								        dma_rd_request <= dma_rd;
-										dma_wr_request <= dma_wr;
-										Ram_rd<=rd_ok;
-										Ram_wr<=wr_ok;
-										Ram_data_in<=data_to_ram; --activer le bit DSending
-		
-		
-		when ex2_barrier1 =>  fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= switch_data_available;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0'; 
-											Ready<='0';
-										  AppInitReq<='0';	
-										  
-		when ex2_barrier2 =>  fifo_wr_en <= '0';
-										Ready<='0';
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';    
-										  AppInitReq<='0';	
-										  
-		when ex2_barrier3 =>	fifo_wr_en <= '0';
-										  switch_port_out_rd_en <='0';
-										  Ready<='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '1';	 
-											AppInitReq<='0';	
-		
-		when ex2_barrier4 =>   fifo_wr_en <= '0';
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  
-										  
-		when ex2_barrier5 =>  fifo_wr_en <= not(fifo_full);
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';										  
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  
-		when ex2_barrier6 =>  fifo_wr_en <= not(fifo_full);										 
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';
-										  Ready<='0';		 	
-		
-		when ex2_barrier7 =>  fifo_wr_en <= not(fifo_full); 
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  	
-     when ex2_spawn1 =>				fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <= rd_ok;--switch_data_available;
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-										   Ready<='0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<=wr_ok;
-	when  ex2_Spawn2 =>   Ready<='0';
-										fifo_wr_en <= '0';
-										switch_port_out_rd_en <='0';
-									   									
-											Ram_data_in<=data_to_ram;
-										
-										Ram_wr<=wr_ok;
-										Ram_rd<='0';
-										packet_received <= '0';
-										dma_rd_request <= '0'; 
-										dma_wr_request <= '1';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-	  when ex2_init1 =>    	fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <= rd_ok;--switch_data_available;
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-										   Ready<='0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<=InitReq;
-											
-		
-		when ex2_init2 =>    	fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <='0';
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<= not(AppInitAck);
-											Ready<='0';
-
-            
-		when ex2_Set_Busy =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;				
-		when others => 			 Ready<='1';   -- le module est à nouveau libre
-									fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='1';
-										  AppInitReq<='0';
-	end case;
-	
- end process;
- 
- ex2_fsm_sync:process(clk,reset)
- 
- begin
-   
-	if reset = '1' then
-	ex2_state <= Ex2_Ready;
-	ack_state<=ack0; --MAE d'envoie de AR
-	n<=0;
-	P_len<=(others=>'0');
-	GPost<=(others =>'0');
-	else
-	if rising_edge(clk) then
-	  ex2_state<=next_ex2_state;
-	  ack_state<=next_ack_state; --MAE d'envoie de AR
-	  n<=n_i;
-	  P_len<=P_len_i;
-	  Packet_type<=packet_type_i;
-	  P_G<=P_G_i;
-	  Result1<=Result_i; --juste une copie
-	  dest_address <= dest_address_i;
-	  data_to_write_fifo<=data_to_write_fifo_i;
-	  WBUSY<=WBUSY_i;
-	  RGET<=RGET_i;
-	  InitReq<=InitReq_i;
-	  mode_get<=mode_get_i;
-	  match_get<=match_get_i;
-	  Sent_ack<=sent_ack_i;
-	  Instr_ack<=Instr_ack_i;
-	  Ptr_Get<=Ptr_Get_i;
-	  Rec_Wpost<=Rec_WPost_i;
-	  dest_ack<=dest_ack_i;
-	  barrier_counter<=barrier_counter_i;
-	  GPost<=GPost_i;
-	  GComp<=GComp_i;
-	  Received_get<=Received_get_i;
-	  GPost_set<=GPost_Set_i;
-	  data_to_ram<=data_to_ram_i;
-	  For i in 0 to Max_stack loop
-	     Waited_get(i)<=Waited_get_i(i);
-	  end loop;
-	  For i in 0 to 7 loop
-			Get_Instr(i)<=Get_instr_i(i);
-	  end loop;
-	  for i in 0 to 3 loop 
-	  Rec_Data(i)<=Rec_Data_i(i); 
-	  end loop;
-	 end if;
-	end if;
- end process ex2_fsm_sync;
-snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,apprank,Packet_type,ram_data_out,dma_rd_grant)
---ce processus est chargé d'emettre  l'accusé de réception pour chaque instruction reçu
-begin	
---  if rising_edge(clk) then
-    Sent_ack_i<='0'; --pas besoin de le mémoriser
-	 wr_ack<='0'; --valeur par défaut
-	 ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen));
-    if  reset='1' then
-        next_ack_state<=ack0;
-		  to_fifo_ack<=(others=>'1');
-  else
-    next_ack_state<=ack_state;
-	
-	case ack_state is 
-	when ack0 =>to_fifo_ack<=(others=>'0'); 
-	               Wr_ack<='0';
-	               if instr_ack='1' then 
-	               next_ack_state<=ack_readwait;
-	               to_fifo_ack <= MPI_ACK & Dest_ack;
-	               wr_ack<='0';
-	             end if;
-	             
-	             sent_ack_i<='0';
-	when ack_readwait =>	to_fifo_ack <= MPI_ACK & Dest_ack;
-	  ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen));
- --vérifier WinPost attend bien une action de cette source
-	 if dma_rd_grant='1' then 
-	    next_ack_state<=ack_checkwait;
-	 end if;  
-	when ack_checkwait =>	to_fifo_ack <= MPI_ACK & Dest_ack;
-	ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen));
-	if dma_rd_grant='1' and ram_data_out(conv_integer(dest_ack))='1' then
-	 next_ack_state<=ack1;
-	elsif dma_rd_grant='0' then
-	next_ack_state<=ack_readwait;
-	else
-	  next_ack_state<=ack6; --pas d'acknowledge à envoyer
-	  assert true report "Packet non attendu de cette source !"
-	  severity failure;
-	end if;           
-	when ack1 =>  if fifo_full = '0' then  -- conversion envoie lack à l'emetteur  
-	       	           -- en empilement dans le fifo
-										    to_fifo_ack <= MPI_ACK & Dest_ack;
-											  next_ack_state <= ack2;
-											  wr_ack<='1';
-								else
-								        wr_ack<='0';
-								 end if;	
-								      sent_ack_i<='0';
-										to_fifo_ack <= MPI_ACK & Dest_ack;
-	when ack2 =>     if fifo_full = '0' then
-										   to_fifo_ack <= "00000100";--la longueur
-											
-										   next_ack_state <= ack3;
-											wr_ack<='1';
-										else --
-										  next_ack_state <= ack2;
-											wr_ack<='0';
-										 
-								    end if;
-									 to_fifo_ack <= "00000100";
-								    sent_ack_i<='0';
-	when ack3 =>     if fifo_full = '0' then
-	                     to_fifo_ack <= "00000000";--
-										   next_ack_state <= ack4;
-											wr_ack<='1';
-										else --
-										  next_ack_state <= ack3;
-											wr_ack<='0';
-										 
-								    end if;	
-									 to_fifo_ack <= "00000000";
-								    sent_ack_i<='0';
-	when ack4 =>     if fifo_full = '0' then
-											to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur
-										  next_ack_state <= ack5;
-											wr_ack<='1';
-											sent_ack_i<='0';
-										else --
-										  next_ack_state <= ack4;
-											wr_ack<='0';
-										 sent_ack_i<='0';
-								    end if;	
-									 to_fifo_ack <=packet_type & apprank ;
-			when ack5 => if Instr_ack='0' then --dernier pulse
-			           				next_ack_state <= ack0;
-			           			else
-			           			  next_ack_state <= ack6;
-			           		 end if;
-			           		 wr_ack<='0';
-										sent_ack_i<='1';
-										to_fifo_ack<=(others=>'1');
-			when ack6 => if Instr_ack='0' then
-			           				next_ack_state <= ack0;
-			           				
-			           		 end if;
-			           		 wr_ack<='0';
-								 sent_ack_i<='1';
-								 to_fifo_ack<=(others=>'1');
-end case;
-end if;
---end if;
-end process;	
-
-	    
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX2_FSM_1.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX2_FSM_1.vhd	(revision 96)
+++ 	(revision )
@@ -1,1604 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: GRIIA - ETIS  -  LIP6
--- Engineer: GAMOM, KIEGAING
--- 
--- Create Date:    01:02:10 06/17/2011 
--- Design Name: 
--- Module Name:    EX2_FSM - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
--- machine a etat qui execute la reception des packet dans le core mpi
--- Dependencies: 
---ss
--- Revision: 26/01/2012
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-library NocLib ;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.Numeric_std.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use Work.Packet_type.ALL;
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX2_FSM is
-
-   generic (
-				 pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
-				 nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
-			 );
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-
-           Instruction_en : in std_logic;
-			  
-			dma_wr_grant : in  STD_LOGIC;
-			dma_wr_request : out  STD_LOGIC;
-			dma_rd_grant : in  STD_LOGIC;
-			dma_rd_request : out  STD_LOGIC;
-			ram_rd : out std_logic;
-			ram_wr : out std_logic;
-			ram_address : out std_logic_vector(ADRLEN-1 downto 0);
-			Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-			Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
-			  
-			fifo_data : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-			fifo_wr_en : out  STD_LOGIC;
-			fifo_full : in  STD_LOGIC;
-			  Rec_Rdy : OUT std_logic;
-		    Rec_Data : buffer Typ_PortIO(0 to 3);
-		    Rec_Ack : IN std_logic;   
-			AppRank : in  STD_LOGIC_VECTOR(3 downto 0);
-			AppSize : in  STD_LOGIC_VECTOR(3 downto 0);
-           packet_received : out  STD_LOGIC;
-           packet_ack : in  STD_LOGIC;
-           barrier_completed : out  STD_LOGIC;
-			  Ready : Out std_logic;
-			  AppInitReq :out  STD_LOGIC; -- requête d'initialisation de l'application
-			  AppInitAck :in  STD_LOGIC; -- Acquitement d'initialisation
-			  Initialized:in std_logic ; -- état de la Lib
-			  Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
-           switch_data_available : in  STD_LOGIC;			  
-           switch_port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           switch_port_out_rd_en : out  STD_LOGIC
-			  
-			  
-			  
-			  );
-end EX2_FSM;
-
-architecture Behavioral of EX2_FSM is
---module pour la lecture des données sur le réseau
-CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu
-component Proto_receiv is
- generic (sizemem : natural := 64);
- port (
- clk,reset : in std_logic;
- fifo_empty,fifo_full : in std_logic;
- rcv_start : in std_logic; --début de la réception
- rcv_ack :in std_logic;   -- acquittement de la réception
- rcv_comp : out std_logic; -- fin de la réception
-  pop : out std_logic:='0';
- fifo_out : in std_logic_vector(Word-1 downto 0);
- mem :out memory(0 to sizemem-1));
-end component Proto_receiv;
-
-COMPONENT SetBit
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		BitMask : IN std_logic_vector(7 downto 0);
-		BitVal : IN std_logic;
-		start : in std_logic;
-		whole : in std_logic;
-		done :  out std_logic;
-		dma_wr_grant : IN std_logic;
-		dma_rd_grant : IN std_logic;
-		Ram_data_in : out std_logic_vector(7 downto 0);          
-		dma_wr_request : OUT std_logic;
-		dma_rd_request : OUT std_logic;
-		ram_rd : OUT std_logic;
-		ram_wr : OUT std_logic;
-		ram_address : IN std_logic_vector(15 downto 0);
-		Ram_data_out : in std_logic_vector(7 downto 0)
-		);
-		End component SetBit;
--- définition du type etat de la machine à etat
-type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, 
-fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4,
-ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3,
- Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,
-  ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy);
-type fsm_ack is(ack0,ack1,ack2,ack3,ack4,ack5,ack6);
-type mem32 is array (natural range <>) of std_logic_vector (31 downto 0);
-signal Next_Ex2_state,ex2_state :fsm_states;
-signal ack_state,next_ack_state : fsm_ack;
--- machine a etat du module
-signal packet_type : std_logic_vector(3 downto 0);
-signal P_len_i,P_len : std_logic_vector(Word-1 downto 0);
-signal barrier_counter : std_logic_vector(3 downto 0);
-signal pading_data,data_to_ram :  std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal n,n_i : natural range 0 to 15;
-signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0');
-signal data_to_write_fifo :  std_logic_vector(Word-1 downto 0);
---*******************************************
---signaux pour la fonction SetBit
-signal		sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
-signal		sb_BitVal,sb_start,sb_done : std_logic:='0';
-signal  sb_whole : std_logic:='0'; --écrire le mot entier
-signal		sb_Ram_data_in : std_logic_vector(7 downto 0);          
-signal		sb_dma_wr_request :  std_logic;
-signal		sb_dma_rd_request :  std_logic;
-signal		sb_ram_rd : std_logic;
-signal		sb_ram_wr : std_logic;
-signal		sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
-signal		sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
--- deuxième module pour set busy bit
-signal Set_Wbusy : std_logic:='0'; --choix du Mux
-signal	GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl
-
---*********************************************
-signal Ex2_on : std_logic:='0';
-signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
-signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement
-signal  dest_ack:std_logic_vector(3 downto 0) :=(others=>'0');
-signal  to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0');
-signal Result_i :  STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0');
---signaux pour l'untilisation du composant de réception 
-signal rfifo_empty,rfifo_full:std_logic;
-signal rcv_start,rcv_comp,rcv_ack:std_logic;
-signal rpop:std_logic;
---signal mem:memory(0 to Msize-1));
---jusqu'à 16 Get peuvent être attendus!
-signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés
-signal WStart,WPost,WBUSY ,RGET: std_logic:='0'; --
-signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0');
-signal Waited_Get,Waited_Get_i : mem32(0 to 15);
-Signal Rec_Data_i : Typ_PortIO(0 to 3);
-signal Get_Instr,Put_instr :memory(0 to 8);
-signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0');
-signal P_G: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get
-signal Ptr_Get,Ptr_Get_i : natural range 0 to 15:=0;
-signal Received_get : std_logic_vector(15 downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu
-begin
-ram_address <= dest_address;
---fifo_data <= data_to_write_fifo;
-Result<=Result_i;
-p_instr_fifo:process(ack_state,data_to_write_fifo,wr_ack,to_fifo_ack,instr_ack)
-begin
-  if instr_ack='1' then
-    fifo_data<=to_fifo_ack;
-else
-  fifo_data<=data_to_write_fifo;
-end if;
-end process p_instr_fifo;
-
-
-
-R0:proto_receiv generic map (sizemem =>4)
-	port map (
-	clk=>clk,
-	reset=>reset,
-	rcv_start=>rcv_start,
-	rcv_comp=>rcv_comp,
-	rcv_ack=>rcv_ack,
-	fifo_empty=>rfifo_empty,
-	fifo_full=>rfifo_full,
-	fifo_out=>switch_port_out_data,
-	pop=>rpop,
-	mem=>open
-	
-	);
---envoie de l'acquittement
-setbit1:SetBit
-	PORT MAP (
-		clk =>clk,
-		reset =>reset,
-		BitMask =>sb_bitMask,
-		BitVal =>sb_bitval,
-		dma_wr_grant =>dma_wr_grant,
-		dma_rd_grant =>dma_rd_grant,
-		Ram_data_in => sb_Ram_data_in,         
-		dma_wr_request =>sb_dma_wr_request,
-		dma_rd_request =>sb_dma_rd_request,
-		ram_rd =>sb_ram_rd,
-		ram_wr =>sb_ram_wr,
-		ram_address =>dest_address,
-		Ram_data_out =>sb_ram_data_out,
-		Start =>sb_start,
-		whole=>sb_whole,
-		done =>sb_done
-		);
-
--- processus de transistion entre les etats 
-ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized,
- switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len,
- sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter,
- dest_ack,rec_wpost,Gcomp,rec_data)
-variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
-variable tempval : std_logic_vector(Word-1 downto 0);
-variable n_e,i:natural range 0 to 15 :=0;
-variable mode_get,match_get:std_logic:='0';
---=================================================================-
-procedure read_nocdat_fsm(sdata_avail: std_logic;
-signal rd,wr:out std_logic;
-signal Plen : inout std_logic_vector(Word-1 downto 0);
-variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is
---lit la suite des données qui sont dans le NoC et identifie le paramètre important
-begin
-if n_e<3 then 
-			                 wr<='0';
-											if sdata_avail='1' then
-												n:=n_e+1;
-												rd<='1';
-												plen <=plen-1;
-											else
-												rd<='0';
-											end if;
-											--result_i<=(others=>'0');
-										elsif n_e=3 then
-											if sdata_avail='1' then
-												n:=n_e+1;
-												rd<='0';
-												--P_len <=P_len_i -1;
-												--data_to_ram<=sportdout;
-												--Result_i<=sport_out_data;
-											else
-												rd<='0';	
-											end if;
-										end if;
-end procedure;
-
-begin
- 
-	Next_Ex2_state <= Ex2_state;
-	Ex2_on<='0';
-	barrier_counter <= "0000";
-  GPost_Set_i<=GPost_Set;
-  Rec_WPost_i<=Rec_WPost;
-  GPost_i<=GPost;
-  GComp_i<=GComp;
-  dest_address_i<=dest_address;
-   for i in 0 to 15 loop 
-  Waited_get_i(i)<=Waited_get(i);
-  end loop;
-
-		Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
-		  n_i<=n; --valeur par défaut de n_i
-		  P_len_i<=P_len;
-		  for i in 0 to 3 loop 
-	  Rec_Data_i(i)<=Rec_Data(i); 
-	  end loop;
-		  case ex2_state is
-		   when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then
-        		        Next_Ex2_state  <= fetch_packet_type;
-                    		     end if;
-                    		     rd_ok<='0';wr_ok<='0';
-			 when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1'  then 	--and initialized ='1'						
-											      Next_Ex2_state  <= decode_packet_type;
-											      packet_type<=switch_port_out_data(7 downto 4);
-											      Dest_ack<=switch_port_out_data(3 downto 0);
-											      Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue !
-											      rd_ok<='1';
-									         else
-											      --Next_Ex2_state <= Ex2_Ready;
-											      rd_ok<='0';
-								           end if;
-								           n_i<=0;
-			when decode_packet_type => rd_ok<='0';
-			                 if switch_data_available ='0' then
-													Next_Ex2_state <= decode_packet_type;
-												else
-												    rd_ok<='1';
-												    Rec_Data_i(1)<=switch_port_out_data-2;
-													 if packet_type = MPI_PUT then
-													    P_len_i <= switch_port_out_data - 2;
-														  n_i<=0;
-														  
-														 Next_Ex2_state <= decode_packet_type2;
-													  elsif packet_type = MPI_GET then
-													    P_len_i <=switch_port_out_data-2;
-														 Next_Ex2_state <= decode_packet_type2;
-													  elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
-													    P_len_i <= switch_port_out_data;
-														 n_i<=0;
-														 Next_Ex2_state <= ex2_barrier1;
-													  elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
-													   n_i<=0;
-													   wr_ok<='0';
-													   --rd_ok<='1';
-														P_len_i <= switch_port_out_data-2;
-														Rec_Data_i(1)<=switch_port_out_data;
-														Next_Ex2_state <= ex2_init1;
-														 elsif packet_type = MPI_ACK then
-													   n_i<=0;
-													   wr_ok<='0';
-													   rd_ok<='0';
-														P_len_i <= switch_port_out_data-2;
-														Next_Ex2_state <= ex2_ack1;
-														elsif packet_type = MPI_WIN_SYNC then
-													   n_i<=0;
-													   wr_ok<='0';
-													   rd_ok<='0';
-														P_len_i <= switch_port_out_data-2;
-														Next_Ex2_state <= ex2_Wsync;
-													  elsif packet_type = MPI_SPAWN  then
-													    Next_Ex2_state <= ex2_spawn1;
-													    wr_ok<='0';
-													   rd_ok<='0';
-													  else
-														  Next_Ex2_state <= decode_packet_type;
-														  rd_ok<='0';
-													 end if;
-												end if;
-			when decode_packet_type2 => if packet_type = MPI_PUT then
-													Next_Ex2_state <= fetch_addresses;
-												  else
-												 	Next_Ex2_state <= ex2_get1;							  
-							               end if;        									
-         when fetch_addresses => if  n=0 then
-                               if switch_data_available = '1'  then
-												            dest_address_i(15 downto 8) <= switch_port_out_data;
-												            Rec_data_i(2)<=switch_port_out_data;												             
-												              n_i <= n + 1;
-												                  rd_ok<='1';
-												        else
-												                  rd_ok<='0';												        												             
-												        end if;												      
-												       elsif n=1 then 
-												            if switch_data_available = '1'  then
-												              dest_address_i(Word-1 downto 0) <= switch_port_out_data;
-												                Rec_data_i(3)<=switch_port_out_data;
-												                P_len_i <= P_len - 2;	
-												                Next_Ex2_state <= ex2_put1;
-												                n_i<=0;
-												                rd_ok<='1';
-												                else
-												                  rd_ok<='0';
-												                    Next_Ex2_state <= fetch_addresses;
-								                        end if;	
-								               end if;			
-            when Ex2_ack2 =>if unsigned(p_len)>0 then
-                        If Dma_rd_grant='1' then
-			                  if n=0  then
-												  n_i<=n+1; --cycle d'attente pour la RAM
-												elsif n=1 then 
-												  dest_address_i <= dest_address+1; 
-												  n_i<=2;
-												elsif n>=2 then
-											
-													    --creer un délai sur ces signaux par rapport à src_adress
-													     
-                          n_i<=n+1;
-                          rd_ok<='1';
---                          if n>1 then
-													dest_address_i <= dest_address+1; 
-													p_len_i <= p_len - 1;
-													--end if;
-													Get_Instr(n-2)<=Ram_data_out; --deux cycles de retard
-													Next_ex2_state <= ex2_ack2;
-												end if;	
-												end if;
-												dma_rd<='1';
-												rd_ok<='1';	
-												else
-												  if P_G=1 then
-												    dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16));
-												  else
-												    dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16));
-													Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id
-													Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur
-													Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas
-													Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut
-													RGET<='1';									
-													
-													Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter
-													end if;
-													Next_ex2_state <= ex2_ack3;
-													n_i<=0; --suite du process ack
-													rd_ok<='0';
-													dma_rd<='0';
-												end if;
-    when ex2_ack1 =>  rd_ok<='0';
-                  if n<2 then --réception de l'acquittement.
-                    n_e:=n_i;
-                	   read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
-                	   n_i<=n_e;
-              	   elsif n=2  then
-              	     	if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												
-												data_to_ram<=switch_port_out_data;
-												Result_i<=switch_port_out_data;	
-											end if;
-              	     
-              elsif n=3 then
-              	     n_i<=n+1;P_G<=0;
-                    if data_to_ram(7 downto 4)=MPI_PUT then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16));
-														wr_ok<='1';
-														P_G<=1; --put ou get
-														P_len_i<=x"06"; --longueur de l'entête à parcourir
-												elsif	data_to_ram(7 downto 4)=MPI_GET then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														P_G<=2; --put get
-														P_len_i<=x"06";--taille de l'instruction en mémoire
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16));
-												elsif data_to_ram(7 downto 4)=MPI_SPAWN then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16));
-												elsif data_to_ram(7 downto 4)=MPI_INIT then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16));		
-														wr_ok<='1'; --
-														-- 
-												else 
-														Result_i<="00000000";
-														wr_ok<='0'; --
-														n_i<=n; --code inconnu !
-												end if;
-										elsif n=4 then
-										  if P_G=1 or P_G=2 then
-										    Next_ex2_state<=ex2_ack2;
-										   else
-										      Next_ex2_state<=ex2_ack3;
-										   end if;
-										   n_i<=0;
-										end if;
-          
-when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction
-            	     sb_start<='1';
-            	     sb_bitMask<=x"20";--cinquième bit à un
-            	     sb_bitval<='1';
-            	     sb_whole<='0';--Modifier un seul bit !
-            	     if sb_done='1' then
-            	       n_i<=1;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-            	       dest_address_i<=dest_address+1;
-        	       end if;
-	       
-	       elsif n=1 then
-	                sb_start<='1';
-            	     sb_bitMask<=Rec_Data(2);
-            	     sb_bitval<='1';
-            	     sb_whole<='1'; 
-            	     if sb_done='1' then
-            	       n_i<=n+1;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-            	       sb_whole<='0';
-        	       end if;
-
-	        elsif n=2 then
-	             Next_Ex2_state<=Ex2_Ready;
-	             n_i<=0;
-            end if;
-            
-    when ex2_Wsync =>  rd_ok<='0';
-                  if n<2 then --réception de la synchronisation.
-                    n_e:=n;
-                	   read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
-                	   n_i<=n_e;
-              	   elsif n=2  then
-              	     	if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												
-												data_to_ram<=switch_port_out_data;
-												Result_i<=switch_port_out_data;	
-											end if;
-              	     
-              elsif n=3 then
-              	     n_i<=n+1;P_G<=0;
-                    if data_to_ram(7 downto 4)=SYNC_WSTART then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
-														wr_ok<='1';
-														P_G<=1; --put ou get
-														P_len_i<=x"06"; --longueur de l'entête à parcourir
-												elsif	data_to_ram(7 downto 4)=SYNC_WPOST then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														P_G<=2; --put get
-														P_len_i<=x"06";--taille de l'instruction en mémoire
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
-												elsif data_to_ram(7 downto 4)=SYNC_WWAIT then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16));
-												elsif data_to_ram(7 downto 4)=SYNC_WCOMP then
-														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));		
-														wr_ok<='1'; --
-														Next_Ex2_State<=Ex2_WCOMP;
-														n_i<=0;
-												else 
-														Result_i<="00000000";
-														wr_ok<='0'; --
-														n_i<=n; --code inconnu !
-												end if;
-										
-										end if;  
-          when Ex2_Wcomp => dma_rd<='1';
-                        rd_ok<='1';	
-                        
-			                  if n=0  then
-												  n_i<=n+1; --cycle d'attente pour la RAM
-												  i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-													 GComp_i(i)<='1';
-												elsif n=1 then 
-												  dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));
-												  If Dma_rd_grant='1' then
-												  n_i<=2;
-												  end if;
-												elsif n=2 then
-											      If Dma_rd_grant='1' then
-													    --creer un délai sur ces signaux par rapport à dest_adress							     
-                                n_i<=n+1;
-                                rd_ok<='1';
-													       dest_address_i <= dest_address+1; 
-													       GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard
-													       
-													 else
-													   n_i<=1;
-													  end if;
-													elsif n=3 then
-													  If Dma_rd_grant='1' then
-													  GPost_i(15 downto 8)<=Ram_data_out;
-													 n_i<=n+1;
-													 rd_ok<='1';
-													 dma_rd<='1';
-													 end if;
-													elsif n=4 then
-													  GPost_i(15 downto 8)<=Ram_data_out;
-													 rd_ok<='1';
-													 dma_rd<='1';	
-													 n_i<=n+1;	
-													 elsif n=5 then		
-													 rd_ok<='0';
-													 dma_rd<='0';										 
-													n_i<=0;
-													If GPost=GComp then --le même nombre de post que de COmpleted ?
-													GPost_Set_i<='1';
-													end if;
-
-													Next_ex2_state <= ex2_set_busy;
-												end if;	
-												
-												          
-			when ex2_init1 => if n<2 then 	-- execution du mpi Init
-			                 wr_ok<='0';
-											if switch_data_available='1' then
-												n_i<=n+1;
-												rd_ok<='1';
-												P_len_i <=P_len-1;
-												Rec_Data_i(n+2)<=switch_port_out_data;
-												data_to_ram<=switch_port_out_data;
-												Result_i<=switch_port_out_data;
-											else
-												rd_ok<='0';
-												n_i<=n;
-											end if;
-											result_i<=(others=>'0');
-										elsif n=2 then
-												n_i<=n+1;
-												rd_ok<='0';
-
-										elsif n=3 then 
-										  rd_ok<='0'; -- normalement plus rien à lire
-										  n_i<=n+1;
-											if Initialized='1' then
-												if data_to_ram(7 downto 4)=INIT_SEEKMAIN then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --permet d'activer Init de Ex_4
-												elsif	data_to_ram(7 downto 4)=INIT_STAT then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --permet d'activer Init de Ex_4
-												elsif data_to_ram(7 downto 4)=INIT_REGISTER then
-														Result_i<=data_to_ram;
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-														report "Mise à jour des données d'initialisation";
-														Next_Ex2_state<=ex2_ready;
-														n_i<=0;
-												elsif data_to_ram(7 downto 4)=INIT_SPAWN then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --permet d'activer Init de Ex_4
-														-- il faut mettre à jour l'état de Spawn
-												else 
-														Result_i<="00000000";
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-												end if;
-											end if;
-											elsif n=4 then 
-										    n_i<=n+1;
-										  elsif n=5 then
-												if p_len=0 then 
-													Next_Ex2_state<=ex2_init2;
-													rd_ok<='0';
-												else
-													p_len_i <=p_len -1;
-													rd_ok<='1'; --vider le tampon de lecture pour ce paquet !
-												end if;
-											
-										end if;
-			when ex2_init2=>  if n=5 then 
-			                         if AppInitAck='1' then
-											             n_i<=n+1;
-											             Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init
-											         end if;
-											     elsif n=6 then 
-											         	Next_Ex2_state<=Ex2_Ready;
-												        n_i<=0;
-											     end if;
-										
-			when ex2_put1 => rd_ok<='0'; --ne  pas autoriser la lecture du switch
-			                 wr_ok<='0';
-			                 if n=0 then
-			                   	 instr_ack_i<='1'; --activer  l'envoie de l'accusé de réception
-			                   	 data_to_write_fifo<=to_fifo_ack;
-			                   	 wr_ok<=wr_ack;
-			                   	 if sent_ack='1' then
-			                   	   n_i<=1;
-			                   	   instr_ack_i<='0';
-			                   	  end if;
-			                   	  
-			                   	elsif n=1 then
-			                   	if dma_wr_grant = '1' then
-  										          Next_Ex2_state <= ex2_put2;
-  										          data_to_ram<=switch_port_out_data;
-  										          rd_ok<='0';
-  										          n_i<=0;
-  										          delai:=0;
-										  	   else
-										          Next_Ex2_state <= ex2_put1;
-								          end if;
-								          end if;	
-			when ex2_put2 =>	rd_ok<='0';
-			                 n_i<=1;
-			                 i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0)));
-			                 --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-			               if unsigned( P_len) > 0  then 
-												
-											if switch_data_available = '1' and delai=0  then
-													   delai:=1; --une donné lue
-														 P_len_i <= P_len - 1;
-														 Next_Ex2_state <= ex2_put2;
-														 rd_ok<='1';
-														 data_to_ram<=switch_port_out_data;
-											end if;
-											if  dma_wr_grant='1' and delai=1 then
-											 -- if n=1 then
-													  wr_ok<='1';
-													  dest_address_i <= dest_address + 1;
-													  delai:=0;--une donnée écrite
-											--	else
-											--	    dest_address_i <= dest_address ;
-											--	end if;
-														--if delai=1 then 
-														--data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
-														--end if;
-														 
-												else
-												  dest_address_i<=dest_address;
-												  wr_ok<='0';
-												  n_i<=0;
-												end if;
-											
-													Next_Ex2_state <= ex2_put2;
-										
-										else 
-										  rd_ok<='0';
-										  
-
-											if dma_wr_grant='1' and n=1 then 
-
-												 Next_Ex2_state <= ex2_put3;
-												Wr_ok<='0';
-												 n_i<=0;
-											 end if;
-									    end if;
-									 
-			when ex2_put3 =>			if dma_rd_grant='1' then 
-													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-													Next_Ex2_state <= ex2_put4;
-													n_i<=0;
-													rd_ok<='1';
-													wr_ok<='0';
-												end if;
-			
-			when ex2_put4 => if n<=4 and n>0 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-										if n=0 then
-										  if RGET='1' then
-									L1:	  for i in 1 to 15 loop  -- to Ptr_get normalement
-										  if i<=Ptr_Get then
-										  if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and
-										    waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and
-										    waited_get(i-1)(23 downto 16)=rec_data(2) and
-											   waited_get(i-1)(31 downto 24)=rec_data(3) then
-                          if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then
-                          received_get(i-1)<='1';
-             													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
-             													mode_get:='1';
-             													match_get:='1';
-                          end if;
-                        else
-                      
-										      end if;
-										 end if;
-										exit L1 when i= Ptr_get;
-										end loop L1;
-										end if;
-											
-											n_i<=n+1;
-											rd_ok<='1';
-											wr_ok<='0';
-											
-											elsif n=1 then
-											 if match_get='0' then
-											   i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-											  Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-                      end if;
-												if dma_rd_grant='1' then 
-												if RGET='1' then --si on est en mode attente d'un Get
-												RGET<='0';  --Supposons tous les Gets reçus !
-                        test_wcomp:for i in 1 to 15 loop --Tous les Get reçus ?
-                          if Ptr_get>=i then
-                          if received_get(i-1)='0' then
-                            RGET<='1';    --Non !
-                        end if;
-                      end if;
-								exit test_wcomp when i=Ptr_get;
-                        end loop test_wcomp;
-                       
-                      end if;
-													n_i<=n+1;
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												end if;
-											elsif n=2 then
-												if dma_rd_grant='1' and dma_wr_grant='1' then 
-													n_i<=n+1;
-													tempval:=Ram_data_out;
-													tempval(4):='1';			--SET du bit DReceived
-												  if Mode_Get='1' then                    --si get ack est détecté
-													   tempval(6):=RGET;  -- Bit 6  Busy=0 si dernier get reçu !!
-													   mode_get:='1';
-													end if;
-													data_to_ram<=tempval;
-													rd_ok<='0';
-													wr_ok<='1';
-												else
-												rd_ok<='1';
-												wr_ok<='0';
-												n_i<=0;
-												end if;
-											elsif n=3 then
-												if dma_wr_grant='1' then
-													rd_ok<='0';
-													wr_ok<='1';
-													n_i<=n+1;
-												end if;
-											elsif n=4 then
-												if dma_wr_grant='1' then
-													rd_ok<='0';
-													wr_ok<='1';
-													
-													n_i<=5;
-												end if;
-										 elsif n=5 then
-										     Next_Ex2_state <= ex2_set_busy;
-										     n_i<=0;
-										     rd_ok<='0';
-													wr_ok<='0';
-													mode_get:='0';
-													match_get:='0';
-											end if;
-											
-										 
-								  
-									--	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
-			when ex2_put5 => 
-										   Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put
-										
-			when ex2_spawn1 => 
-											
-											if n<2 then
-											 n_e:=n;
-											read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);	
-											n_i<=n_e;
-											Rec_Data_i(2)<=Switch_port_out_data;
-											elsif n=2 then
-											    Rec_Data_i(3)<=Switch_port_out_data;
-													Result_i<=Switch_port_out_data;
-													Data_to_ram<=Switch_port_out_data;
-													n_i<=n+1;
-													rd_ok<='1';
-											elsif n=3 then
-												if data_to_ram(7 downto 4)=SPAWN_LOAD then
-														Result_i<=data_to_ram;
-														wr_ok<='1'; --permet d'activer Init de Ex_4
-												elsif	data_to_ram(7 downto 4)=SPAWN_COMP then
-														Result_i<=data_to_ram;
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-
-												elsif	data_to_ram(7 downto 4)=SPAWN_ERR then
-														Result_i<=data_to_ram;
-														wr_ok<='0'; --permet d'activer Init de Ex_4
-												else
-														Result_i<=(others=>'0');
-													
-												end if;
-												n_i<=n+1;
-												rd_ok<='0';
-											elsif n=4 then	
-											     wr_ok<='1';
-														if AppInitAck='1' then
-															wr_ok<='0';
-															rd_ok<='0';
-															n_i<=n+1;
-														end if;
-											elsif n=5 then
-															wr_ok<='0';
-															rd_ok<='0';
-															n_i<=0;
-												Next_Ex2_state <=Ex2_Ready;
-											end if;
-			when Ex2_Spawn2=> 
-			               Next_Ex2_state <=Ex2_Ready;
-			when ex2_get1 =>  rd_ok<='0'; --ne  pas autoriser la lecture du switch
-			                 --ack_state<=next_ack_state; --MAE d'envoie de AR
-			                 if n=0 then
-			                   	 instr_ack_i<='1'; --activer  l'envoie de l'accusé de réception
-			                   	 data_to_write_fifo<=to_fifo_ack;
-			                   	 wr_ok<=wr_ack;
-			                   	if sent_ack='1' then
-			                   	   n_i<=1;
-			                   	   instr_ack_i<='0';
-			                   	   wr_ok<='0';
-			                   	   --if switch_data_available='1' then
-			                   	   rd_ok<='0';--
-			                   	   --P_len<=P_len-1;
-			                   	   --end if;
-			                   	  end if;
-			                   	  
-			                   	elsif n=1 then
-			                   	if   switch_data_available='1' then
-			                   	if fifo_full = '0' then  -- conversion du get en put en empilement dans le fifo
-										    	     data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put						       	 
-											         wr_ok<='1';
-											         rd_ok<='1'; --autoriser la lecture du crossbar
-											         P_len_i<=P_len-1;
-											         n_i<=n+1;
-											     else
-											       Wr_ok<='0';
-											       Rd_ok<='0';
-								        	  end if;	
-								        	  else
-								        	    Wr_ok<='0';
-								        	    rd_ok<='0';
-								        	  end if;
-								        	 elsif n=2 then
-								        	  if   switch_data_available='1' then
-								        	   if fifo_full = '0' then  -- conversion du get en put en empilement dans le fifo
-										    	     --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put						       	 
-											       	--P_len_i <= P_len-1;--le nombre d'octet qui restent à copier
-											       	 Next_Ex2_state <= ex2_get2;
-											         wr_ok<='0';
-											         rd_ok<='0'; --autoriser la lecture du crossbar
-											         n_i<=0;
-											       else
-											         rd_ok<='0';
-											         wr_ok<='0';
-											      end if;
-											     else
-											         rd_ok<='0';
-											         wr_ok<='0';
-								        	  end if;	
-								      end if;
-			when ex2_get2 => if P_len>0 then 
-			                 if fifo_full = '0' and switch_data_available ='1' then
-  										        data_to_write_fifo <= switch_port_out_data;--la longueur initiale du GET
-  											     p_len_i <= P_len - 1;
-  										        Next_Ex2_state <= ex2_get2;
-  											     wr_ok<='1';
-  											     Rd_ok<='1';
-										    elsE
-										         
-											         wr_ok<='0';
-											         Rd_ok<='0';
-											 END IF;
-										  else
-										  if n=0 then
-										   if fifo_full='0' then
-											 wr_ok<='0';--une impulsion en plus
-											 n_i<=n+1;
-											 Next_Ex2_state <= ex2_get2;
-											 else
-											  wr_ok<='0';
-											end if;
-											
-											else
-											  Next_Ex2_state <= ex2_get3;
-											  n_i<=0;
-											  wr_ok<='0';
-											 end if;
-											rd_ok<='0';
-								    end if;
-								    i:=to_integer(unsigned(Rec_Data(0)(3 downto 0)));
-			               Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données !
-
-								    --préparer en avance l'adresse de lecture/écriture
-								    dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-		   when ex2_get3 => wr_ok<='0';
-		                    if dma_rd_grant='1' then -- fin du mpi_get
-										   Next_Ex2_state <= ex2_get4;
-											n_i<=0;
-											--activer le bit sending du registre de transfert
-										  else
-											Next_Ex2_state <= ex2_get3;
-								      end if;
-											
-										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-			when ex2_get4 => if n <4 then     
-			
-												dma_wr<='1';  --demander un accès exclusif au bus
-												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-											else
-												dma_wr<='0';										
-												dma_rd<='0';
-											end if;
-											if n=0 then
-												if dma_rd_grant='1' then
-												n_i<=n+1;
-												
-												end if;
-												rd_ok<='1';
-												wr_ok<='0';
-											elsif n=1 then
-												if dma_rd_grant='1' then
-													n_i<=n+1;
-													
-													end if;
-													rd_ok<='1';
-													wr_ok<='0';
-												
-											elsif n=2 then
-													if dma_rd_grant='1' and dma_wr_grant='1' then
-														n_i<=n+1;
-														tempval:=Ram_data_out;
-														tempval(2):='1';  	--mise à 1 du Bit DSending
-														--tempval(5):='0'; 		--Mise à 0 du Bit Sent
-														data_to_ram<=tempval;
-														rd_ok<='1';
-														wr_ok<='0';
-													else
-													rd_ok<='1';
-													wr_ok<='0';
-													n_i<=0;
-												end if;
-											
-											elsif n=3 then
-												if dma_wr_grant = '1' then
-												n_i<=n+1;
-												rd_ok<='0';
-												wr_ok<='1';
-												end if;
-											elsif n=4 then
-											  if dma_wr_grant = '1' then
-													n_i<=0;
-													Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get
-											  else
-													rd_ok<='0';
-													wr_ok<='1';
-													--n<=n-1;
-											 end if;
-											end if;
-										   
-										 
-										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-					when ex2_Set_Busy => if n=0 then --set busy bit of the instruction
-            	             dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-                          n_i<=1;
-                              if Gpost_Set='1' then
-                                if  (rec_wpost=gpost) and RGET='0' then
-                                    Wbusy<='0';
-                                    Gpost_Set_i<='0';
-                                    GComp_i<=(others=>'0');
-                                    rec_wpost_i<=(others=>'0');--reset des messages reçu
-                                else
-                                    Wbusy<='1';
-                                end if;
-                            else
-                                
-                                n_i<=2;
-                              end if;
-                              if RGET='1' then 
-                                  WBusy<='1';
-                             end if;
-          	     elsif n=1 then
-            	     sb_start<='1';
-            	     sb_bitMask<=x"40";--6e bit à 1
-            	     sb_bitval<=WBusy;
-            	     if sb_done='1' then
-            	       n_i<=2;
-            	       sb_start<='0';
-            	       sb_bitval<='0';
-        	       end if;
-	       elsif n=2 then
-	             Next_Ex2_state<=Ex2_Ready;
-	             n_i<=0;
-            end if;
-								-- execution du barrier
-			when ex2_barrier1 => if switch_data_available = '1' then
-												 pading_data <= switch_port_out_data;
-												 Next_Ex2_state <= ex2_barrier2;
-											  else
-											    Next_Ex2_state <= ex2_barrier1;	
-											 end if;	
-			when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then
-												 barrier_counter <= barrier_counter + 1;
-												 Next_Ex2_state <= ex2_barrier4;	
-											  else
-											    Next_Ex2_state <= ex2_barrier3;	
-											 end if;	
-			when ex2_barrier3 => if n < 10 then
-												 n_i<= n + 1;
-												 Next_Ex2_state <= ex2_barrier3;	
-											  else
-											    Next_Ex2_state <= Ex2_Ready;	
-											 end if;	
-			when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED 
-												 data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000";
-												 Next_Ex2_state <= ex2_barrier5;	
-											  else
-											    Next_Ex2_state <= Ex2_Ready;	
-											 end if;	
-			when ex2_barrier5 => if fifo_full = '0' then  -- taille du packet MPI_BARRIER_COMPLETED
-												 data_to_write_fifo <= "00000011";
-												 Next_Ex2_state <= ex2_barrier6;	
-											  else
-											    Next_Ex2_state <= ex2_barrier5;	
-											 end if;		
-			when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
-												 data_to_write_fifo <= "00000000";
-												 Next_Ex2_state <= ex2_barrier7;	
-											  else
-											    Next_Ex2_state <= ex2_barrier6;	
-											 end if;				
-			when ex2_barrier7 => if fifo_full = '0' then
-												 barrier_counter <= "0000";
-												 Next_Ex2_state <= Ex2_Ready;	
-											  else
-											    Next_Ex2_state <= ex2_barrier7;	
-											 end if;				
-			
-			when others => Next_Ex2_state <= Ex2_Ready;
-		   end case;
-        
- end process;
- 
- -- sortie de la machine à etat
---
- ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr,
- switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request,
- appInitAck,n)
-  variable transact : std_logic_vector(Word-1 downto 0);
-  begin   
--- code fonctionnel	
-	case Ex2_state is
-		when  Ex2_Ready => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='1';
-										  AppInitReq<='0';
-		when  fetch_packet_type => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='0';
-										  AppInitReq<='0';
-										  
-								  
-		when decode_packet_type => fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when decode_packet_type2 => fifo_wr_en <= '0';
-										    switch_port_out_rd_en <= '0';
-										    packet_received <= '0'; 
-										    dma_wr_request <= '0';
-										    dma_rd_request <= '0';
-										    Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										    barrier_completed <= '0';
-										    AppInitReq<='0';	
-											Ready<='0';
-		when fetch_addresses =>  fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		when ex2_ack1 |ex2_Wsync =>		  
-										Ready<='0';
-										switch_port_out_rd_en<=rd_ok;
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;
-				when ex2_ack2|Ex2_WCOMP =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= dma_rd;
-										dma_wr_request <= '0';
-										Ram_rd<=rd_ok;
-										Ram_wr<='0';
-			when ex2_ack3 =>		  
-										Ready<='0';
-										switch_port_out_rd_en<=rd_ok;
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;							
-		when ex2_put1 =>  fifo_wr_en <= wr_ok;
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '1';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when  ex2_put2 =>   Ready<='0';
-										fifo_wr_en <= '0';
-										switch_port_out_rd_en <=rd_ok;
-									   
-										if rd_ok = '1' then
-										
-										 Ram_data_in<=switch_port_out_data;
-										else
-											Ram_data_in<=data_to_ram;
-										end if;
-										Ram_wr<=wr_ok;
-										Ram_rd<='0';
-										packet_received <= '0';
-										dma_rd_request <= '0'; 
-										dma_wr_request <= '1';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-		when  ex2_put3 => 	 Ready<='0';
-										fifo_wr_en <= '0';
-									   switch_port_out_rd_en <='0';	
-										--ne pas corrompre le contenu de la RAM
-										--Ram_data_in<=data_to_ram; 					
-										Ram_wr<='0';
-										Ram_rd<='1';
-										packet_received <= '0';
-										dma_rd_request <= '1'; 
-										dma_wr_request <= '0';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-										
-		
-		when ex2_put4 =>    fifo_wr_en <= '0';
-										Ready<='0';
-										switch_port_out_rd_en <= '0';
-										 packet_received <= '1'; 
-										 dma_rd_request <= dma_rd;
-										 dma_wr_request <=dma_wr;
-										 Ram_wr<=wr_ok;
-										 Ram_rd<=rd_ok;
-										 AppInitReq<='0';	 
-										 barrier_completed <= '0';	
-										 Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution 
-											
-		when ex2_put5 =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								        packet_received <= '1';
-								        AppInitReq<='0';
-								        barrier_completed <= '0';
-								        dma_rd_request <= dma_rd;
-										dma_wr_request <= dma_wr;
-										Ram_rd<=rd_ok;
-										Ram_wr<=wr_ok;
-										Ram_data_in<=data_to_ram;
-										--Result <=(1=>'1',others=>'0'); --put completed								  
-		
-		when ex2_get1=>   fifo_wr_en <= wr_ok;
-										  switch_port_out_rd_en <= rd_ok;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-											Ready<='0';
-		
-		when ex2_get2 =>	     										    
-											 switch_port_out_rd_en <=rd_ok;
-										  fifo_wr_en <= Wr_ok;
-										  Ready<='0';
-										  packet_received <= '0';
-										  dma_rd_request <= '0'; 
-										  dma_wr_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0'; 
-										  AppInitReq<='0';	
-										    
-		when ex2_get3 =>      		fifo_wr_en <= '0';
-										Ready<='0';
-										switch_port_out_rd_en <= '0';
-										 packet_received <= '1'; 
-										 dma_rd_request <= '1';
-										 dma_wr_request <='0';
-										 Ram_wr<='0';
-										 Ram_rd<='1';
-										  AppInitReq<='0';	
-										  barrier_completed <= '0';	
-										 --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
-											
-		when ex2_get4 =>		  
-										Ready<='0';
-										barrier_completed <= '0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								        packet_received <= '1';
-								        AppInitReq<='0';
-								        dma_rd_request <= dma_rd;
-										dma_wr_request <= dma_wr;
-										Ram_rd<=rd_ok;
-										Ram_wr<=wr_ok;
-										Ram_data_in<=data_to_ram; --activer le bit DSending
-		
-		
-		when ex2_barrier1 =>  fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= switch_data_available;
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0'; 
-											Ready<='0';
-										  AppInitReq<='0';	
-										  
-		when ex2_barrier2 =>  fifo_wr_en <= '0';
-										Ready<='0';
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';    
-										  AppInitReq<='0';	
-										  
-		when ex2_barrier3 =>	fifo_wr_en <= '0';
-										  switch_port_out_rd_en <='0';
-										  Ready<='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '1';	 
-											AppInitReq<='0';	
-		
-		when ex2_barrier4 =>   fifo_wr_en <= '0';
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  
-										  
-		when ex2_barrier5 =>  fifo_wr_en <= not(fifo_full);
-										  switch_port_out_rd_en <='0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-											Ram_wr<='0';
-											Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';										  
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  
-		when ex2_barrier6 =>  fifo_wr_en <= not(fifo_full);										 
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';
-										  Ready<='0';		 	
-		
-		when ex2_barrier7 =>  fifo_wr_en <= not(fifo_full); 
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'0');
-										  barrier_completed <= '0';
-										  AppInitReq<='0';	
-										  Ready<='0';
-										  	
-     when ex2_spawn1 =>				fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <= rd_ok;--switch_data_available;
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-										   Ready<='0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<=wr_ok;
-	when  ex2_Spawn2 =>   Ready<='0';
-										fifo_wr_en <= '0';
-										switch_port_out_rd_en <='0';
-									   									
-											Ram_data_in<=data_to_ram;
-										
-										Ram_wr<=wr_ok;
-										Ram_rd<='0';
-										packet_received <= '0';
-										dma_rd_request <= '0'; 
-										dma_wr_request <= '1';
-										AppInitReq<='0';	
-										barrier_completed <= '0';
-	  when ex2_init1 =>    	fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <= rd_ok;--switch_data_available;
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-										   Ready<='0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<=wr_ok;
-											
-		
-		when ex2_init2 =>    	fifo_wr_en <= '0'; 
-										   switch_port_out_rd_en <='0';
-										   packet_received <= '0'; 
-										   dma_wr_request <= '0';
-										   dma_rd_request <= '0';
-										   Ram_rd<='0';
-											Ram_wr<='0';
-										   barrier_completed <= '0';
-											Ram_data_in<=(others =>'0');
-											AppInitReq<= not(AppInitAck);
-											Ready<='0';
-
-            
-		when ex2_Set_Busy =>		  
-										Ready<='0';
-										switch_port_out_rd_en<='0';
-										fifo_wr_en <= '0';
-								    packet_received <= '0';
-								    AppInitReq<='0';
-								    barrier_completed <= '0';
-								    dma_rd_request <= sb_dma_rd_request;
-										dma_wr_request <= sb_dma_wr_request;
-										Ram_rd<=sb_ram_rd;
-										Ram_wr<=sb_ram_wr;
-										sb_ram_data_out<=Ram_data_out;
-										Ram_data_in<=sb_ram_data_in;				
-		when others => 			 Ready<='1';   -- le module est à nouveau libre
-									fifo_wr_en <= '0';
-										  switch_port_out_rd_en <= '0';
-										  packet_received <= '0'; 
-										  dma_wr_request <= '0';
-										  dma_rd_request <= '0';
-										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'0');
-										  Ram_rd<='0';
-										  Ram_wr<='0';
-										  Ready<='1';
-										  AppInitReq<='0';
-	end case;
-	
- end process;
- 
- ex2_fsm_sync:process(clk,reset)
- 
- begin
-   
-	if reset = '1' then
-	ex2_state <= Ex2_Ready;
-	ack_state<=ack0; --MAE d'envoie de AR
-	n<=0;
-	P_len<=(others=>'0');
-	GPost<=(others =>'0');
-	else
-	if rising_edge(clk) then
-	  ex2_state<=next_ex2_state;
-	  ack_state<=next_ack_state; --MAE d'envoie de AR
-	  n<=n_i;
-	  P_len<=P_len_i;
-	  dest_address <= dest_address_i;
-	  Sent_ack<=sent_ack_i;
-	  Instr_ack<=Instr_ack_i;
-	  Ptr_Get<=Ptr_Get_i;
-	  Rec_Wpost<=Rec_WPost_i;
-	  GPost<=GPost_i;
-	  GComp<=GComp_i;
-	  GPost_set<=GPost_Set_i;
-	  For i in 0 to 15 loop
-	     Waited_get(i)<=Waited_get_i(i);
-	  end loop;
-	  for i in 0 to 3 loop 
-	  Rec_Data(i)<=Rec_Data_i(i); 
-	  end loop;
-	 end if;
-	end if;
- end process ex2_fsm_sync;
-snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,Packet_type)
---ce processus est chargé d'emettre  l'accusé de réception pour chaque instruction reçu
-begin	
---  if rising_edge(clk) then
-    
-    if  reset='1' then
-        next_ack_state<=ack0;
-  else
-    next_ack_state<=ack_state;
-	case ack_state is 
-	when ack0 =>to_fifo_ack<=(others=>'0'); 
-	               Wr_ack<='0';
-	               if instr_ack='1' then 
-	               next_ack_state<=ack1;
-	               to_fifo_ack <= MPI_ACK & Dest_ack;
-	               wr_ack<='0';
-	             end if;
-	             
-	             sent_ack_i<='0';
-	             
-	when ack1 =>  if fifo_full = '0' then  -- conversion envoie lack à l'emetteur  
-	       	           -- en empilement dans le fifo
-										    to_fifo_ack <= MPI_ACK & Dest_ack;
-											  next_ack_state <= ack2;
-											  wr_ack<='1';
-								else
-								        wr_ack<='0';
-								 end if;	
-								      sent_ack_i<='0';
-	when ack2 =>     if fifo_full = '0' then
-										   to_fifo_ack <= "00000100";--la longueur
-											
-										   next_ack_state <= ack3;
-											wr_ack<='1';
-										else --
-										  next_ack_state <= ack2;
-											wr_ack<='0';
-										 
-								    end if;
-								    sent_ack_i<='0';
-	when ack3 =>     if fifo_full = '0' then
-	                     to_fifo_ack <= "00000000";--
-										   next_ack_state <= ack4;
-											wr_ack<='1';
-										else --
-										  next_ack_state <= ack3;
-											wr_ack<='0';
-										 
-								    end if;	
-								    sent_ack_i<='0';
-	when ack4 =>     if fifo_full = '0' then
-											to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur
-										  next_ack_state <= ack5;
-											wr_ack<='1';
-											sent_ack_i<='0';
-										else --
-										  next_ack_state <= ack4;
-											wr_ack<='0';
-										 sent_ack_i<='0';
-								    end if;	
-			when ack5 => if Instr_ack='0' then --dernier pulse
-			           				next_ack_state <= ack0;
-			           			else
-			           			  next_ack_state <= ack6;
-			           		 end if;
-			           		 wr_ack<='0';
-										sent_ack_i<='1';
-										to_fifo_ack<=(others=>'1');
-			when ack6 => if Instr_ack='0' then
-			           				next_ack_state <= ack0;
-			           				
-			           		 end if;
-			           		 wr_ack<='0';
-										sent_ack_i<='1';
-										to_fifo_ack<=(others=>'1');
-end case;
-end if;
---end if;
-end process;	
-
-	    
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX3_FSM.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX3_FSM.vhd	(revision 96)
+++ 	(revision )
@@ -1,75 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: GAMOM / KIEGAING
--- 
--- Create Date:    09:22:58 05/20/2011 
--- Design Name: 
--- Module Name:    EX3_FSM - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
--- module du core mpi chargé d'exécuter les fonctions mpi_get_size et mpi_get_rank
--- Dependencies: 
---
--- Revision: 23/02/2012
--- Revision 0.02 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
---package Packet_type
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use Work.Packet_type.ALL;
-Library NocLib;
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX3_FSM is
- generic (
-				pid : unsigned(Word-1 downto 0) :=  "00000001"; -- id du processeur
-				nprocs : unsigned(Word-1 downto 0):="00000011"-- nombre de processeur du MPSOC
-			);
-    Port ( instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           ResOut : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  pid_nprocs: out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           clk : in  STD_LOGIC;
-			  IsMain: in STD_LOGIC;
-           reset : in  STD_LOGIC);
-end EX3_FSM;
-
-
-architecture Behavioral of EX3_FSM is
-
-signal instruction_signal : std_logic_vector(3 downto 0);
-signal rank : unsigned(Word-1 downto 0) := pid;
-signal size : unsigned(Word-1 downto 0) := nprocs;
-begin
-instruction_signal <= instruction(7 downto 4);
-ex3_fsm_process : process(clk)
-begin
-
-
-if rising_edge(clk) then
- if reset ='1' then
-   ResOut <= (others=>'0');
- else
-  if instruction_signal = MPI_GET_RANK then
-   ResOut <=  std_logic_vector(rank);
-  elsif instruction_signal = MPI_GET_SIZE then
-   ResOut <=  std_logic_vector(size);
-	elsif instruction_signal=MPI_INIT then
-	if IsMain='1' then  --master est associé à la bibliothèque de rang 0
-	rank<=rank+1;    -- elle est responsable d'affecter de nouveaux rangs
-	end if;
- end if;
- end if; 
-end if;
-end process;
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX4_FSM.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX4_FSM.vhd	(revision 96)
+++ 	(revision )
@@ -1,1950 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: GAMOM 
--- 
--- Create Date:    14:44:36 03/07/2012 
--- Design Name: 
--- Module Name:    EX4_FSM - Behavioral 
--- Project Name: MPI_CORE_COMPONENTS
--- Target Devices: SPARTAN 3E xc3s1200e
--- Tool versions: 
--- Description: Ce module renferme les fonctions permettant d'initialiser la 
--- bibliothèque matériel MPI
--- Dependencies:
---
--- Revision: 25/juin/2012 au 24/Octobre/2012
--- Revision 0.03 - File updated
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
-Library NocLib;
-use NoCLib.CoreTypes.all;
-use work.packet_type.all;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX4_FSM is
-    Port ( Instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Instruction_En : in  STD_LOGIC;
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           ResultOut : out  STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0');
-           Result_En : out  STD_LOGIC:='0';
-           Ready : out STD_LOGIC; --indique que le module est disponible
-           NocSize : out  STD_LOGIC_VECTOR(3 downto 0);
-			     PortId : out  STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');
-           AppRank : out  STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');
-           AppSize : out  STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');
-           IsMain : out  STD_LOGIC;
-           I_fifo_full :in STD_LOGIC; --instruction fifo
-		       I_fifo_wr_en: out STD_LOGIC;--instruction fifo Write enable
-		       I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); --instruction fifo data
-			     Initialized : out STD_LOGIC;
-			  Snd_Ack : IN std_logic;
-		Rec_Rdy : IN std_logic;
-		Rec_Data : IN Typ_PortIO(0 to 3);
-		Snd_data : OUT Typ_PortIO(0 to 3);
-		Snd_Start : buffer std_logic;
-		Rec_Ack : OUT std_logic;       
-				   dma_wr_grant : in  STD_LOGIC;
-				   dma_wr_request : out  STD_LOGIC;
-				dma_rd_grant : in  STD_LOGIC;
-				dma_rd_request : out  STD_LOGIC;
-				ram_rd : out std_logic;
-				ram_wr : out std_logic;
-				ram_address : out std_logic_vector(ADRLEN-1 downto 0);--accès au stockage
-				Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-				Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
-			
-			  AppAck : in  STD_LOGIC;
-           AppReq : in  STD_LOGIC;
-			  port_in_cmd_en : out  STD_LOGIC:='0';
-			  port_in_wr_en : out  STD_LOGIC:='0';
-			  port_in_empty : in  STD_LOGIC;
-           port_in_full : in  STD_LOGIC;
-           port_in_data : out  STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'-');
-			  port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           port_out_rd_en : out  STD_LOGIC:='0';
-           port_out_data_available : in  STD_LOGIC);
-end EX4_FSM;
-
-architecture Behavioral of EX4_FSM is
-
-COMPONENT SetBit
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		BitNum : IN std_logic_vector(0 to 2);
-		BitVal : IN std_logic;
-		dma_wr_grant : IN std_logic;
-		dma_rd_grant : IN std_logic;
-		Ram_data_in : IN std_logic_vector(7 downto 0);
-		   
-		dma_wr_request : OUT std_logic;
-		dma_rd_request : OUT std_logic;
-		ram_rd : OUT std_logic;
-		ram_wr : OUT std_logic;
-		ram_address : OUT std_logic_vector(15 downto 0);
-		Ram_data_out : OUT std_logic_vector(7 downto 0)
-		);
-	END COMPONENT;
-Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in;
-Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out;
-
-	--MAE pour emission de init
-   --type init1_type is (init,NocSize,InitToNoc,NextPort,EndBCast); 
-	--	MAE pour affectation des rangs aux différentes librairies MPI
-	type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,ReadNoc,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendPeerStat,AskPeerStat,GetPeerStat,SendApp,SpawnApp,SpawnLoad,ErrSpawn,EndInit);
-   -- MAE pour réception de init depuis le réseau;
-	type init3_type is  (init,GetNocSize,ReadInitHead,StorePort,EndInit); 
-	type typ_send is (s_init,s_head,s_len,s_len2,s_data,s_end);
-	type typ_receiv is (r_wait,r_dlen,r_drop,r_glen,r_data,r_pulse,r_end);
-	type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout);
-  type typ_mem16 is array(natural range <>) of std_logic_vector(15 downto 0);--
-		signal etsnd : typ_send;
-		signal etrec:typ_receiv;   --pour la machine à état de réception
-		signal etcmd :typ_cmd;     --pour la machine à état de commande
-signal IS_state,next_Is_state : natural range 0 to 3:=0;
-
---	signal stInit1, next_stInit1 : init1_type; 
-	signal stInit2, next_stInit2 : init2_type; 
-	--signal stInit3, next_stInit3 : init3_type; 
-	--signaux pour l'interface avec les ports
-	signal cport_in_wr_en,sport_in_wr_en:std_logic;
-	signal cport_out_rd_en,rport_out_rd_en:std_logic;
-	signal rdy:std_logic:='0'; --signal busy/ready
-	signal tosend,tosend4 :std_logic_vector(Word-1 downto 0);
-	signal PeerStat,PeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres Lib initialisées
-  signal SpawnReq,SpawnReq_Q : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres HT qui ont appelés le Spawn	
-	signal Spawn_grp,Spawn_grp_Q :typ_mem16(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); --un max de quatre groupes de fils est prévu
-	signal Grp_id,grp_id_i :natural range 0 to 3:=0; --id du groupe des HT fils
-	signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port
-	--signaux pour les états des MAE
-	signal  NocSizeOk,PortCountFlag : std_logic;
-	signal PortNumFlag,PortNumFlag_i,EquFlag,EquFlag_i,MainResp: std_logic:='0';
-	signal StatAsked,RankAsked,RankSent:std_logic;
-	signal  nextr,nextr_i : natural :=0;
-   signal RTS_cmd,RTS_dat,RTS_I,CTR,BCast,Send_Ack,DS_Ack,CM_Ack:std_logic:='0';
-	signal I_Send_Ack,I_Send_Rdy:std_logic:='0';
-	signal Rcv_On,Snd_On,Cmd_On : std_logic:='0'; --status des MAE d'envoie et de réception
-	signal SpawnOn,SpawnInit :std_logic:='0'; --indique que le Spawn est activé
-	signal SpawnNbReq,SpawnNbAck,SpawnNBAck_i : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement
-	signal SpawnNbReq_Q : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement
-	signal SpawnCmd0,SpawnCmd1, SpawnCmd2 :std_logic_vector(Word-1 downto 0):=(others=>'0');
-	signal SpawnCmd0_Q,SpawnCmd1_Q, SpawnCmd2_Q :std_logic_vector(Word-1 downto 0):=(others=>'0');
-	signal SpawnDest :std_logic_vector(3 downto 0);
-	Signal Ht_Start,Ht_Start_i : natural range 0 to 15:=0;
-	Signal vPeerStat,vPeerStat_i : std_logic_vector(15 downto 0):=(others=>'0');
-	signal IsMain_i,IsMain1,Initialized_i,HCL_init,HCL_Init_i: std_logic:='0';
-	signal DS_RDY ,BCast_Rdy,Send_RDY,CM_RDY:std_logic:='0';
-	signal ExecTime_out:std_logic;
-	--signaux de gestion de la RAM
-	signal Ram_Next_Address : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16));
-	signal Ram_NExt_Address_i :std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16));
-	signal n,n_i:natural range 0 to 15 :=0;
-	signal n0,n0_i:natural range 0 to 7:=0;
-	signal DataToRam : std_logic_vector(Word-1 downto 0) ;
-	signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
-	--Signaux des résultats et de l'état
-  signal PortNum_i,PortNum,MyPort : std_logic_vector(3 downto 0);  -- 
-	signal NocMax ,NocMax_i: std_logic_vector(3 downto 0):=(others=>'0'); -- Nombre de ports du réseau -1 ?
-	signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE
-	signal AppSize_i,AppSize1:std_logic_vector(3 downto 0) ;--taille de l'application
-	signal Spawn_done,Spawn_done_i:std_logic:='0'; --indique que le Spawn a été effectué
-	signal MainPort,MainPort_i : std_logic_vector(3 downto 0) ; --Port de la lib main
-	signal NextRank,NextRank_i : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI
-   signal Data_To_Send,Data_to_send_i : Typ_PortIo(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); -- permet d'empiler les données à envoyer
-	signal RankToPort :Typ_PortIo(0 to 15);--permet d'associer un port réseau à chaque  rang
-	signal CmdReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
-	signal DataReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
-	signal Datalen,DataLen_i : natural range 0 to 7:=0; --indique la longueur des données
-	--other outputs
-	signal StatAsked_i,RankAsked_i,MainResp_i,RankSent_i,Result_i:std_logic:='0';
-	signal snd_start_i:std_logic:='0';--version interne des signaux de sortie
-   --signal BCast_Rdy_i : std_logic;
-	signal cdlen,dcount : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd
-	signal timeout,timeout_i : natural range 0 to 4095:=0;
-	signal PortStat,PortStat_i : std_logic_vector(3 downto 0):=(others=>'0');
-	signal PeerPort,PeerPort_i : natural range 0 to 15:=0; -- désigne le port qui emet une requête
-	signal PeerRTS,PeerRTS_i,PeerCTR:std_logic:='0';
-	signal cpt,cpt_peer : natural range 0 to 31:=0; --compteur pour le nombre de HT initialisés
-	signal clk_cyl,clk_cyl_i : natural range 0 to 15:=0;
-begin
---=======================================================================================
---fonctions du module
---=======================================================================================
---=======================================================================================
- 
--- Inst_SetBit: SetBit PORT MAP(
---		clk => clk,
---		reset => reset ,
---		ce => cmd,
---		BitNum => ,
---		BitVal => '1',
---		dma_wr_grant => dma_wr_grant ,
---		dma_wr_request => dma_wr_request,
---		dma_rd_grant => dma_rd_grant,
---		dma_rd_request => dma_rd_request,
---		ram_rd => ram_rd,
---		ram_wr => ram_wr,
---		ram_address => ,
---		Ram_data_in => Ram_data_in,
---		Ram_data_out => Ram_data_out
---	);
-
- 
-   -- Gestion de l'initialisation du Core MPI
-  sync_Init2 : process (clk,reset)
-  begin
-	if reset='1' then
-		stinit2<=init;
-		StatAsked<='0';
-		MyPort<=(others=>'0');
-		NextRank<=(others =>'0');
-	elsif rising_edge(clk) then
-		stinit2<=next_stinit2;
-		IS_State<=Next_IS_State;
-		n0<=n0_i;
-		--ajout des autres affectations ici
-		Ram_Next_Address<=Ram_Next_Address_i;
-		PortNumFlag<=PortNumFlag_i;
-		RankAsked<=RankAsked_i;
-		RankSent<=RankSent_i;
-		AppRank<=MyRank;
-		timeout<=timeout_i;
-		cpt<=cpt_peer;
-		clk_cyl<=clk_cyl_i;
-		NextRank<=NextRank_i;
-		StatAsked<=StatAsked_i;
-		MainResp<=MainResp_i;
-		AppSize1<=AppSize_i;
-		n<=n_i;
-		Ht_Start<=Ht_Start_i;
-		Grp_Id<=Grp_Id_i;
-		vPeerStat<=vPeerStat_i;
-		SpawnNbAck<=SpawnNbAck_i;
-		PortStat<=PortStat_i;
-		EquFlag<=EquFlag_i;
-		--IsMain1<=IsMain_i;
-		if ismain_i='1' then
-			IsMain1<='1';
-			
-		else
-			IsMain1<=IsMain1;
-		end if;
-		if stInit2=DecodeData then 
-			MyPort<=Cmdreceived(2)(3 downto 0);
-		end if;
-		
-		if stInit2=StoreRank and ExecTime_Out='1' then
-			MyRank<=MyPort;
-		elsif stInit2=StoreRank then
-			MyRank<=DataReceived(2)(3 downto 0);
-		elsif stInit2=SetMainFlag then
-		  MyRank<=MyPort;
-		end if;
-		Ready<=Rdy;
-		snd_start<=snd_start_i;
-		SpawnNbReq_q<=SpawnNbReq;
-		SpawnReq_Q<=SpawnReq;
-		SpawnCmd0_Q<=SpawnCmd0;
-		SpawnCmd1_Q<=SpawnCmd1;
-		SpawnCmd2_Q<=SpawnCmd2;
-		Spawn_grp_q<=Spawn_grp;
-		PeerRTS<=PeerRTS_i;
-		PortNum<=PortNum_i;
-		Spawn_done<=Spawn_done_i;
-		HCL_init<=Hcl_init_i;
-		PeerStat<=PeerStat_i;
-		DataLen<=DataLen_i;
-		MainPort<=MainPort_i;
-		Nextr<=NextR_i;
-		NocMax<=NoCMax_i;
-		PeerPort<=PeerPort_i;
-		grp_id<=grp_id_i;
-		for i in 0 to 3 loop
-			data_to_send(i)<=data_to_send_i(i);
-		end loop;
-	end if;
-end process;
-
-AppSize<=AppSize1;
-
-  Init2_DECODE: process (stinit2,n, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, 
-  SpawnOn,Ram_Next_Address,PeerRTS,PortSTAT,dma_rd,dma_wr,Send_rdy,I_Send_rdy,rd_ok,wr_ok,Instruction,
-  MainPort,PeerStat,SpawnCmd0,SpawnCmd1,SpawnCmd2,SpawnInit,BCast_rdy)
-   variable nextadr : natural :=0;--to_integer(unsigned(Ram_Next_Address));
-	variable nport : natural range 0 to 15:=0;
-	begin
-      for i in 0 to 3 loop
-			data_to_send_i(i)<=data_to_send(i);
-		end loop;
-		PortNum_i<=PortNum;
-		PortNumFlag_i<=PortNumFlag;
-		PortID<=MyPort;
-		PeerPort_i<=PeerPort;
-		NocMax_i<=NoCMax;
-		NextRank_i<=NextRank;
-		MainPort_i<=MainPort;
-		PeerStat_i<=PeerStat;
-		EquFlag_i<=EquFlag;
-		RankAsked_i<=RankAsked;
-		NextR_i<=NextR;
-		Ram_Next_Address_i<=Ram_Next_Address;
-		Ram_address<=(others=>'1');
-		Ram_data_in<=(others=>'1');
-		dma_rd_request<='0';
-		dma_wr_request<='0';
-		Initialized_i<='0';
-		rdy<='0';
-		ram_rd<='0';
-		ram_wr<='0';
-		I_Send_ack<='0';
-		IsMain_i<='0';
-		send_ack<='0';
-		DataLen_i<=0;
-      Case stInit2 is
-		When Init =>
-			RTS_cmd<='0';
-			--RTS_dat<='0';
-			RTS_I<='0';
-			BCast<='0';
-			Result_En<='0';
-			Initialized_i<='0';
-			CM_Ack <='0';
-			CTR<='0' ;
-			DS_ACK<='0';
-			Send_Ack<='0';
-			ram_wr<='0';
-			rdy<='1';--le module est disponible
-			ResultOut<=(others=>'0');
-			if PortNumFlag='1'  and IsMain1='1' then
-				PortNum_i<=Instruction(3 downto 0);
-			else
-				PortNum_i<=(others=>'-');
-			end if;
-			EquFlag_i<='0';
-			RankAsked_i<='0';
-			dma_wr_request<='0';
-			dma_rd_request<='0';
-		When GetPortNum =>
-			RTS_cmd<='1';
-			RTS_I<='0';
-			
-			Result_En<='0';
-			Initialized_i<='0';
-			BCast<='0';   --réalise un envoie non collectif
-			CM_Ack<='0';   -- les données sont maintenant attendues
-			CTR<='0' ;
-			data_to_send_i(0)<=X"0" & GETPORTID;
-			DS_ACK<='0';
-			Send_Ack<='0';
-			ram_wr<='0';
-			rdy<='0';
-			IsMain_i<='0';
-			ResultOut<=(others=>'0');
-			PortNum_i<=(others=>'-');
-			RankAsked_i<='0';
-			dma_wr_request<='0';
-		When DecodeData =>
-			EquFlag_i<=(All_zeros(Cmdreceived(2)(3 downto 0)));
-			RTS_cmd<='0';
-			RTS_I<='0';
-			BCast<='0';
-			
-			Result_En<='0';
-			
-			CM_Ack <='1'; --les données ont été reçues
-			--MyPort<=Cmdreceived(2)(3 downto 0);
-			PortNum_i<=Cmdreceived(2)(3 downto 0); --récupère les valeurs de port
-			PeerPort_i<=To_integer(unsigned(Cmdreceived(2)(3 downto 0)));
-			NocMax_i<=Cmdreceived(2)(7 downto 4);  -- et la taille du réseau
-			PortNumFlag_i<='1';  -- le numéro du port est maintenant connu
-			CTR<='0' ;
-			DS_ACK<='0';
-			Send_Ack<='0';
-			ram_wr<='0';
-			rdy<='0';
-			RankAsked_i<='0';
-			ResultOut<=(others=>'0');
-			dma_wr_request<='0';
-		When IsPortZero => --Ce port est-il le n° 0 du NoC ?
-			BCast<='0';
-			Result_En<='0';
-			RTS_cmd<='0';
-			RTS_I<='0';
-			NextRank_i<="0001"; -- le prochain rang à affecter sera le n° 1
-			nextr_i<=1;
-			IsMain_i<=EquFlag;
-			--MyRank<="0000";
-			MainPort_i<="0000";
-			--MainAdr<="0000";   -- le port 0 est le main Lib par défaut;
-			CTR<='0' ;
-			DS_ACK<='0';
-			ram_wr<='0';
-						rdy<='0';
-			RankAsked_i<='0';
-			ResultOut<=(others=>'0');
-			dma_wr_request<='0';
-		When SeekMain1 =>    -- recherche de la lib main
-				RTS_cmd<='0';
-				--RTS_DAT<='1';
-				RTS_I<='1';
-				CTR<='1' ; -- prêt à recevoir les données Clear To Receive
-				DS_ACK<='0'; --les données sont attendus
-				Send_Ack<=BCast_rdy;
-				I_Send_Ack<=BCAst_rdy;
-				data_to_send_i(0)<=MPI_INIT & MyPort ;
-				data_to_send_i(1)<="00000100"; -- la longueur du packet =4
-				data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse
-				data_to_send_i(3)<=INIT_SEEKMAIN & MyPort ;
-				DataLen_i<=4;
-				BCast<='1';
-				
-				Result_En<='0';
-				Initialized_i<='0';
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When SeekMain2 =>    -- recherche de la lib main
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='1' ; -- prêt à recevoir les données Clear To Receive
-				DS_ACK<= DS_RDY; --les données sont acquittées aussitôt reçues
-				Send_Ack<=BCast_rdy;
---				data_to_send_i(0)<=INIT_SEEKMAIN & MyPort ;
---				data_to_send_i(1)<="00000011"; -- la longueur du packet =3
---				data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse
---				DataLen<=3;
-				BCast<='0';				
-				Result_En<='0';
-				Initialized_i<='0';
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				EquFlag_i<='0';
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When StoreMain =>     -- la Main Lib est une autre
-				BCAST<='0';
-				Result_En<='0';
-				IsMain_i<='0';
-				Initialized_i<='0';
-				DS_ACK<=DS_RDY;
-				Send_Ack<='0';
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<=not(MainResp);  -- essayer de recevoir tant que le main n'a pas répondu
-				ram_wr<='1';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				RankAsked_i<='0';
-				EquFlag_i<='0';
-				MainPort_i<=DataReceived(0)(3 downto 0);
-				ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16));
-				ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0);  --MainPort & MyRank
-				dma_wr_request<= '0';  ---pas très sûr
-		
-		When AskPeerStat =>    -- Interroge les données d'initialisation
-				RTS_cmd<='0';
-				if n=0 then
-				--RTS_DAT<='0'; --on peut envoyer les données
-				RTS_I<='1';
-				else
-				  --RTS_DAT<='0'; --on désactive l'envoie des données
-				  RTS_I<='0';
-				 end if;
-				CTR<='0' ; -- prêt à recevoir les données Clear To Receive
-				DS_ACK<='0'; --les données sont attendus
-				I_Send_Ack<=I_Send_rdy;
-				Send_Ack<=Send_rdy;
-				data_to_send_i(0)<=MPI_INIT & MainPort ;
-				data_to_send_i(1)<="00000100"; -- la longueur du packet =4
-				data_to_send_i(2)<="0000" & MyPort; --indique sa propre adresse
-				data_to_send_i(3)<=INIT_STAT & MyPort ;
-				DataLen_i<=4;
-				BCast<='0';
-				Result_En<='0';
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				EquFlag_i<='0';
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When SetMainFlag =>   -- Cette Lib est la Main Lib 
-				if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then 
-					RankAsked_i<='1';
-				else 
-					RankAsked_i<='0';
-				end if;
-				RTS_cmd<='0';
-				Initialized_i<='0';
-		      RTS_I<='0';
-				BCast<='0';
-				IsMain_i<='1';
-				Result_En<='0';
-				--MyRank<="0000";
-				MainPort_i<="0000";
-				PeerStat_i(0)<='1'; --la main lib est initialisée
-				CTR<='1';
-				DS_ACK<='0';
-				ram_wr<='1';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				EquFlag_i<='0';
-				ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16));
-				ram_data_in<=(others =>'0');  -- le port vaut 0 et la mainlib est aussi à 0
-				dma_wr_request<='1';
-		When ReadNoc =>
-				if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then
-					RankAsked_i<='1' ;
-				else 
-					RankAsked_i<='0';
-				end if;
-				ram_wr<='0';  -- pas d'écriture en RAM
-				rdy<='0';
-				BCast<='0';
-				DS_ACK<='0';
-				--IsMain<='0';
-				Result_En<='0';			
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='1';
-				ResultOut<=(others=>'0');
-				PortNum_i<=DataReceived(2)(3 downto 0); -- le port qui demande un rang;
-				PeerPort_i<= To_integer(unsigned(DataReceived(2)(3 downto 0)));
-				--EquFlag<='1';
-				dma_wr_request<='0';
-		When GetMainReq  =>
-				--RankAsked_i<='1';
-				ram_wr<='0';  -- pas
-				BCast<='0';
-				DS_ACK<='1';				
-				Result_En<='0';				
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='1';
-				ResultOut<=(others=>'0');
-				PortNum_i<=DataReceived(0)(3 downto 0); -- le port qui demande un rang;
-				EquFlag_i<='1';
-				dma_wr_request<='0';
-		When GetPeerStat  =>
-				--RankAsked_i<='1';
-				ram_wr<='0';  -- pas
-				BCast<='0';
-				DS_ACK<=DS_RDY;
-				Result_En<='0';
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<=not MainResp;
-				ResultOut<=(others=>'0');
-				PortNum_i<=DataReceived(0)(3 downto 0); --adresse du Main Port
-				PeerStat_i(7 downto 0)<=DataReceived(2); -- état des initialisations
-				EquFlag_i<='0';
-				dma_wr_request<=dma_wr;
-				ram_wr<=wr_ok;
-				rdy<='0';
-				ram_rd<=rd_ok;
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_Init_Adr+2,ADRLEN)); --incr_vec(Ram_Next_Address,'1');
-				ram_address<=Ram_Next_Address;  -- 
-				ram_data_in<=DataReceived(2); --enregistrer les ports actifs
-				
-		When NewRank =>
-				nport:=to_integer(Unsigned(PortNum)); --port ayant sollicité le rang
-				nextr_i<=to_integer(unsigned(nextrank));
-				if PeerStat(nport)='0' then -- si le rang n'a pas encore été affecté à ce port
-				nextrank_i<=incr_vec(nextrank,'1');
-				RankToPort(to_integer(unsigned(nextrank)))<="0000" & PortNum;
-				NextAdr:=NextAdr+1;
-				end if;
-				data_to_send_i(0)<=MPI_INIT & PortNum ;
-				data_to_send_i(1)<="00000100";
-				data_to_send_i(2)<="0000" & NextRank;  --ici c'est la valeur avant incrémentation !
-				data_to_send_i(3)<=INIT_SETRANK & PortNum ;
-				PeerStat_i(nport)<='1'; -- mise à jour du status
-				DataLen_i<=4;
-				BCast<='0';
-				DS_ACK<='0';
-				Result_En<='0';
-				EquFlag_i<='1';
-				RTS_cmd<='0';
-				RTS_I<='1';
-				CTR<='0' ;
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='1';
-				ResultOut<=(others=>'0');
-				dma_wr_request<='0';
-				
-		When SendRank =>
-				BCast<='0';
-				Result_En<='0';
-				EquFlag_i<='1';
-
-				RTS_I<='1';
-				DataLen_i<=4;
-				RTS_cmd<='0';
-				DS_ACK<='0';
-				Send_Ack<='0';
-				CTR<='0' ;
-				ram_wr<='0';
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16));
-				ResultOut<=(others=>'0');
-				RankAsked_i<='1';
-				dma_wr_request<='0';
-		When RegRank =>
-					RankAsked_i<='0';
-
-				CTR<='1' ; -- continuer à recevoir les données du NoC
-				Result_En<='0';
-				RTS_cmd<='0';
-				DS_ACK<='0';
-				Send_Ack<=Send_RDY;
-				I_Send_ack<=i_send_rdy;
-				Rts_I<='0';
-				BCast<='0';
-				EquFlag_i<='1';
-				ram_wr<='1';
-				
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); --incr_vec(Ram_Next_Address,'1');
-				ram_address<=Ram_Next_Address;  -- le rang qui a été envoyé;
-				-- "le motif 0001 indique juste que le port est bien activé
-				ram_data_in<="0001" & PortNum; --enregistrer le port qui a fait la demande en RAM
-				ResultOut<=(others=>'0');
-				dma_wr_request<='1';
-		When SendPeerStat =>
-				BCast<='0';
-				Result_En<='0';
-				EquFlag_i<='0';
-				RTS_I<=PeerRTS;
-				RTS_cmd<='0';
-				DS_ACK<='0';
-				data_to_send_i(0)<=MPI_INIT & PortStat ;
-				data_to_send_i(1)<="00000100";
-				data_to_send_i(2)<=PeerStat(7 downto 0);
-				data_to_send_i(3)<=INIT_REGISTER & MyPort ;
-				Send_Ack<=Send_Rdy;
-				I_Send_Ack<=I_Send_Rdy;
-				CTR<='0' ;
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				RankAsked_i<='1';
-				dma_wr_request<='0';
-				Initialized_i<='1';
-		When StoreRank => --le processus qui écoute le Port et qui 
-								--stoke les adresses des autres bib va gérer le stockage du rang
-				BCAST<='0';
-				DS_ACK<='1';
-				Send_Ack<='0';
-				RTS_cmd<='0';
-				EquFlag_i<='0';
-				RTS_I<='0';
-				CTR<='0';
-				Result_En<='0';
-				
-				if ExecTime_out='1' then
-				MainPort_i<="0000";
-				--MyRank<=MyPort;
-				initialized_i<='0';
-				else
-				MainPort_i<=DataReceived(0)(3 downto 0);
-				--MyRank<=DataReceived(2)(3 downto 0);
-				Initialized_i<='1'; 
-				end if;
-				ram_wr<='1';
-				--ram_address<=DataReceived(2);  -- le rang qui a été envoyé;
-				ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16));
-				ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0);  --MainPort & MyRank
-				ResultOut<=(others=>'0');
-				RankAsked_i<='0';
-				dma_wr_request<='1';
-		When SendApp =>  --ajouter du code pour recevoir l'adr du reg status
-				Initialized_i<='1';
-				ResultOut<="00000001"; -- Init Ok
-				Result_En<='1';
-				PortId<=MyPort;
-				BCAST<='0';
-				DS_ACK<='1';
-				Send_Ack<='0';
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='0';
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When SpawnApp =>
-				RTS_cmd<='0';
-				RTS_I<='0';
-				Result_En<='0';
-				DS_ACK<=DS_RDY;
-				BCAST<='0';
-				CTR<='0';  --cette mise à 1 permet de ctrler la fin de réception
-				rdy<='0';
-				ram_wr<=wr_ok;
-				ram_rd<=rd_ok;
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_BASE_ADR,ADRLEN)); --incr_vec(Ram_Next_Address,'1');
-				ram_address<=Ram_Next_Address;  -- le rang qui a été envoyé;
-				-- "le motif 0001 indique juste que le port est bien activé
-				ram_data_in<=DataToRam; --enregistrer le port qui a fait la demande en RAM
-				dma_rd_request <= dma_rd;
-				dma_wr_request <=dma_wr;
-				RankAsked_i<='0';
-				if n>=3 then
-					ResultOut<=("00000010");--spawn completed
-				else
-					ResultOut<=("00000000");--spawn message received 
-				end if;
-				
-		When SpawnLoad =>
-		    RTS_cmd<='0';
-				--RTS_DAT<='1'; --à tester
-				RTS_I<=PeerRTS; -- pour le timing
-				Result_En<='0';
-				DS_ACK<='0';
-				BCAST<='0';
-				CTR<='0';
-				rdy<='0';
-				ram_wr<=wr_ok;
-				ram_rd<=rd_ok;
-		      data_to_send_i(0)<=SpawnCmd0;
-          data_to_send_i(1)<="00000100";
-          data_to_send_i(2)<=SpawnCmd1;
-          data_to_send_i(3)<=SpawnCmd2; -- SPAWN_LOAD & MyPort ;
-          Send_Ack<=Send_Rdy;
-    				I_Send_Ack<=I_Send_rdy;
-          RankAsked_i<='0';
-				if SpawnInit='1' then
-					ResultOut<=("10000000"); --spawn completed
-				else
-					ResultOut<=("01000000");--spawn in progress
-				end if;
-		When ErrSpawn =>
-				RTS_cmd<='0';
-				RTS_I<='0';
-				Result_En<='1';
-				DS_ACK<='0';
-				Send_Ack<='0';
-				BCAST<='0';
-				CTR<='0';
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='0';
-				
-				ResultOut<=(others=>'0');
-				dma_wr_request<='0';
-				dma_rd_request<='0';
-		When EndInit =>
-				RTS_cmd<='0';
-				RTS_I<='0';				
-				Result_En<='0';
-				DS_ACK<='0';
-				Send_Ack<='0';
-				BCAST<='0';
-				CTR<='0';
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='0';
-				ResultOut<=(others=>'0');
-				dma_wr_request<='0';
-				dma_rd_request<='0';
-		end case;
-   end process;
-	
-result_proc:process (ISMain_i,Initialized_i,stInit2,reset)
-begin
-if reset='1' then
-	--IsMain1<='0';
-	Initialized<='0';
-	HCL_Init_i<='0';
-	
-Else
-	HCL_init_i<=HCl_init;
-	Initialized<=Hcl_init;
---	if ismain_i='1' then
---		IsMain1<='1';
---	end if;
-
-	if Initialized_i='1' and stInit2=EndInit then
-		Initialized<='1';
-		HCL_Init_i<='1';
-	elsif stInit2=SendApp then
-	  HCL_Init_i<='1';
-	end if;
-end if;
-end process result_proc;
- --================
- --Traitement du Spawn
- --===================
- 
- --==================
-   NEXT_STInit2_DECODE: process (stInit2,AppReq,Instruction_en, AppAck,PortNumFlag,EquFlag,MainResp,StatAsked,RankAsked,RankSent,CM_RDY, CmdReceived, 
-	BCast_Rdy, DS_RDY, DataReceived,Ht_Start,vPeerStat, Send_RDY,	I_Send_RDY,TimeOut,Dma_rd_grant,Dma_wr_grant,cpt,n,clk_cyl,IsMain1,SpawnOn,
-	Instruction,Hcl_Init,Spawn_done,mainport,PeerStat,PeerRTS,Rec_Data,SpawnInit,grp_id,SpawnNbReq,Ram_data_out,Spawn_grp,MyPort)
-   variable InitTimeOut :natural:=0;
-	variable LastPort,Ht_hole : std_logic:='0';
-	variable i,nbSpawn,htloc,Ht_Id : natural range 0 to 15:=0;
-	--variable vPeerStat : std_logic_vector(15 downto 0);
-   variable vPortStat,nulvect : std_logic_vector(3 downto 0):="0000";	
-	variable tempval : std_logic_vector(Word-1 downto 0);
-  begin
-      --declare default state for next_state to avoid latches
-      next_stInit2 <= stInit2;  --default is to stay in current state
-      --insert statements to decode next_state
-      --below is a simple example
-		vPeerStat_i<=vPeerStat;
-		SpawnNbReq<=SpawnNbReq_q;
-		StatAsked_i<=StatAsked;
-		MainResp_i<=MainResp;
-		AppSize_i<=AppSize1;
-		PortStat_i<=PortStat;
-		grp_id_i<=grp_id;
-		PeerRTS_i<=PeerRTS;
-		--PortNumFlag_i<=PortNumFlag;
-		SpawnReq<=SpawnReq_q;
-		Spawn_done_i<=Spawn_done;
-		Ht_Start_i<=Ht_Start;
-		SpawnCmd0<=SpawnCmd0_Q;
-		SpawnCmd1<=SpawnCmd1_Q;
-		SpawnCmd2<=SpawnCmd2_Q;
-		Timeout_i<=Timeout;
-		clk_cyl_i<=clk_cyl;
-		n_i<=n;
-		Cpt_peer<=cpt;
-		DataToRam<=(others=>'0');--A revoir
-		dma_rd<='0';
-		dma_wr<='0';
-		rd_ok<='0';
-		wr_ok<='0';
-		for i in 0 to 3 loop
-		Spawn_grp(i)<=Spawn_grp_q(i);
-		end loop;
-      case (stInit2) is
-         
-			
-		When Init =>If Instruction_en='1' and AppReq='1'  then
-					 If PortNumFlag='1'  and IsMain1='1' then
-						if instruction(7 downto 4)=INIT_SEEKMAIN and (instruction(3 downto 0)/=MyRank) then 
-							Next_stInit2 <=NewRank;--affecter un rang au demandeur.
-						elsif instruction(7 downto 4)=INIT_STAT then
-						  StatASked_i<='1';
-							Next_stInit2 <=SendPeerStat; --envoyer des stat au demandeur
-						elsif instruction(7 downto 4)=SPAWN_LOAD then
-							SpawnInit<='0'; -- indique le debut du Spawn 
-							Next_stInit2 <=SpawnLoad; 
-						elsif instruction(7 downto 4)=INIT_SPAWN then
-							SpawnInit<='1'; -- indique la fin du 
-							Next_stInit2 <=SpawnLoad; --dans ce cas il s'agit de terminer le spawn
-						else --ignorer ce message
-							Next_stInit2 <=SendApp;
-						end if;
-					 elsif HCL_Init='1' and IsMain1='0' then 
-						Next_stInit2 <=SendApp; --ignorer ce message simplement
-					else 
-						Next_stInit2 <=GetPortNum; -- initialiser la bibliothèque normalement
-					end if;
-					TimeOut_i<=0;PeerRTS_i<='0';
-					
-				 elsif SpawnOn='1' and Spawn_done='0' then 
-					Next_stInit2 <=SpawnApp;
-					TimeOut_i<=0;
-				 end if;
-				cpt_peer<=0;LastPort:='0';n_i<=0;
-		When GetPortNum =>  -- récupérer le numéro du port
-												
-						if CM_RDY='1' then 
-							Next_stInit2 <=DecodeData;
-						end if;
-						
-		When DecodeData =>  -- cet état permet de lire les données reçues du port
-							--if CM_RDY='1' then 
-								if ((Cmdreceived(2)(3 downto 0) or nulvect)=nulvect) then -- teste si le n° du port est zero
-								  --EquFlag<='1';
-								 else
-								  --EquFlag<='0';
-								end if;
-								
-								Next_stInit2 <=IsPortZero;
-							--end if;
-		When IsPortZero => 
-						if PortNumFlag='1' then 
-						
-						End if;
-						if EquFlag='0'  then  --tester le numéro de port obtenu
-							Next_stInit2 <=SeekMain1; -- chercher le numéro de port sur le réseau
-						else 
-							Next_stInit2<=SetMainFlag; -- enregistrer le numéro de port
-						End If;
-						TimeOut_i<=0;
-		
-		When SeekMain1 =>If BCast_RDY='1' then  -- si tous les envois ont été postés
-									Next_stInit2<=SeekMain2;
-							End if;				
-		When SeekMain2 =>  
-							If DS_RDY='1' then  -- Si un jeu de données a été reçu
-										if (Datareceived(3)(7 downto 4) = INIT_SETRANK) then 
-												MainResp_i<='1';
-												Next_stInit2 <=StoreMain; -- de la librairie pricipale
-									 else
-												MainResp_i<='0';
-												Timeout_i<=0;
-									 end if;	
-										
-							elsif (ExecTime_Out='1') then 
-									
-												-- le Noc ne répond pas
-												-- affecter un numéro en raport avec le port
-										Next_stInit2 <=SeekMain2;
-							elsif TimeOut=800 then
-												--essayer de redemander l'initialisation
-									assert true report "Ex4:seekmain ->redemander l'initialisation"
-                      severity failure;
-									Timeout_i<=0;			
-									Next_stInit2 <=SeekMain1;
-							else
-										Timeout_i<=TimeOut+1;
-							End if;
-							
-							 
-							 
-		When StoreMain =>
-				if DataReceived(3)(7 downto 4)= INIT_SETRANK then
-				-- enregistrer le Main Adresse et les adresses des autres processus
-				-- dans la variable prévue à cet effet
-				Next_stInit2 <=StoreRank;
-				
-				elsif Datareceived(3)(7 downto 4) = INIT_SEEKMAIN then 
-				-- ignorer ce message
-				Next_stInit2 <=StoreMain; --essayer de recevoir le rang
-				
-				
-				end if;
-					
-		When StoreRank =>
-					--il faut prévoir du code pour s'assurer que la RAM a bien enregistrer
-					-- la donnée ...
-					if dma_wr_grant = '1' then 
-						if clk_cyl=2 then --prévoir deux cycle d'horloge pour lire en RAM
-							Next_stInit2 <=AskPeerStat;
-							TimeOut_i<=0;
-							clk_cyl_i<=0;
-						else 
-							clk_cyl_i<=clk_cyl+1;
-						end if;
-					else
-							Next_stInit2 <=StoreRank;
-							TimeOut_i<=0;
-							clk_cyl_i<=0;
-					end if;
-		When AskPeerStat =>if n=0 then 
-		        If I_SEND_RDY='1' then  -- si tous les envois ont été postés
-									n_i<=1;
-									StatAsked_i<='0';
-							End if;		
-						elsif n=1 then 
-						If I_SEND_RDY='0' then  -- si tous les envois ont été postés
-									Next_stInit2<=GetPeerStat;
-									StatAsked_i<='1';
-									MainResp_i<='0';
-							   n_i<=0;
-							End if;		
-						end if;		
-		When GetPeerStat =>  
-							if n=0 then
-							If DS_RDY='1' then  -- Si un jeu de données a été reçu
-									 if (Datareceived(3) = INIT_REGISTER & MainPort ) then 
-												MainResp_i<='1';
-												n_i<=n+1;
-												
-									 else
-												MainResp_i<='0';
-												Timeout_i<=0;
-												n_i<=n;
-									 end if;	
-										
-							elsif TimeOut=1800 then
-												--essayer de redemander les statistiques
-									assert true report "Ex4:GetPeerStat timeout  ->Les statistiques n'ont pas été reçu"
-									severity failure;
-									Timeout_i<=0;	
-									If StatAsked='1' then
-									Next_stInit2 <=AskPeerStat; -- ceci n'est pas sûr
-									else
-									Next_stInit2 <=GetPeerStat;
-									end if;
-							else
-										Timeout_i<=TimeOut+1;
-							End if;  
-							elsif n=1 then  --écrire le résultat de l'initialisation
-							dma_wr<='1';
-							if dma_wr_grant='1' then
-								n_i<=n+1;
-								wr_ok<='1';
-							end if;
-							elsif n=2 then
-								n_i<=n+1;   --écriture dans la RAM
-							elsif n=3 then
-								n_i<=0;
-								dma_wr<='0';
-								Next_stInit2 <=SendApp; -- de la librairie pricipale
-							end if;
-		When SetMainFlag =>
-				if dma_wr_grant='1' then   
-						TimeOut_i<=0;
-						Next_stInit2 <=ReadNoc;
-					elsif Timeout=800 then
-					  	assert true report "Ex4:SetMainFlag timeout  ->La mémoire n'est pas dispo dma_wr_grant=0"
-					  	severity failure;
-						Next_stInit2 <=SendApp;
-					else
-						TimeOut_i<=TimeOut+1;
---					end if; -- il est envisagée de terminer le programme à ce point
-				end if;
-		when ReadNoc => if DS_RDY='1' then
-									if (Datareceived(3)(7 downto 4) = INIT_STAT) then
-											StatAsked_i<='1' ;
-											Next_stInit2 <=SendPeerStat;
-											LastPort:='0';
-									else 
-										StatAsked_i<='0';
-										Next_stInit2 <=GetMainReq;
-									end if;
-									
-									Timeout_i<=0;
-								elsif Timeout=400 then
-									assert true report "Ex4:ReadNoc timeout pas de données lues sur le NoC après 200 cycles"	
-									severity failure;							  
-									Timeout_i<=0;
-									--if StatAsked = '1' then
-										--Next_stInit2 <=ErrSpawn; --il y a eu une erreur
-										Next_stInit2 <=SendApp;
-								--	else
-									--	Next_stInit2 <=SendPeerStat;
-								--	end if;
-								else
-									TimeOut_i<=TimeOut+1;
-								end if; 
-				
-		When GetMainReq => if RankAsked='1' and PeerStat(PeerPort)='0' then
-									Next_stInit2 <=NewRank; -- un nouveau rang est demandé
-								else
-									Next_stInit2 <=ReadNoC; -- sinon essayer encore de lire un jeu de données.
-								end if;
-		When NewRank =>
-				Next_stInit2 <=SendRank;
-		When SendRank =>
-					if I_Send_RDY='1' then  --RankSent
-						Next_stInit2 <=RegRank;
-						RankSent_i<='1';  -- le rang a été envoyé
-						TimeOut_i<=0;   -- prépare le traitement de la prochaine requête
-												-- d'attente des ports
-				  elsif Timeout=800 then
-				    assert true report "Impossible d'envoyer le rang"
-				    severity failure;
-				    timeout_i<=0;
-				  else 
-				    TimeOut_i<=TimeOut+1; 
-					end if;
-		When RegRank =>
-					--il faut prévoir du code pour s'assurer que la RAM a bien enregistrer
-					-- la donnée ...
-					if dma_wr_grant = '1' then 
---							if DS_RDY='1' then
-								RankSent_i<='0';
-								if DS_RDY='0' then
-								 
-									Next_stInit2 <=ReadNoc;
-								end if;
-							elsif Timeout=800 then
-								Next_stInit2 <=SendApp;
-								assert true report "Ex4:RegRank Timeout dma_wr_grant=0 "
-				    severity failure;
-							else
-								TimeOut_i<=TimeOut+1;
---							end if; -- il est envisagée
-					end if;
-					--calcul de la taille de l'appli
-					HtLoc:=0;
-					for i in 0 to 7 loop
-						if peerStat(i)='1' then --trouve le prochai rang libre
-							HtLoc:=HtLoc+1;
-						end if;
-					end loop;
-					AppSize_i<=std_logic_vector(to_unsigned(HtLoc,4));
-		
-		When SendPeerStat =>
-					
-					if cpt<=unsigned(NoCMax)and LastPort='0' then
-						if peerRts='0' then -- pas encore envoyer les données alors les préparer
-								if StatAsked='1' then 
-									
-									PortStat_i<=PortNum;
-									vPortStat:=std_logic_vector(to_unsigned(PeerPort,4));
-								else
-									PortStat_i<=std_logic_vector(to_unsigned(cpt,4));--Port à contacter
-									vPortStat:=std_logic_vector(to_unsigned(cpt,4));
-								end if;
-								
-								if StatAsked='1' then 
-									LastPort:='1';  -- on traite u seul port celui qui en a fait la demande
-									if PeerStat(PeerPort)='1' then
-									PeerRts_i<='1';
-									end if;
-								else
-									if (PeerStat(cpt)='1') and not(vPortStat=MyPort) then
-										PeerRts_i<='1';
-									end if;
-									if cpt<unsigned(NoCMax) then 
-										cpt_peer<=cpt+1;
-										LastPort:='0';
-									else
-										if LastPort='0' then
-												LastPort:='1';
-												cpt_peer<=cpt+1;--ceci permet de déclencher l'évaluation du process
-										end if;
-									end if;
-								end if;
-								TimeOut_i<=0;
-					else
-							if I_Send_RDY='1' then  
-										
-										RankSent_i<='1';  	-- les stat ont été envoyé
-										TimeOut_i<=0;  	 	-- prépare le traitement de la prochaine requête
-										PeerRts_i<='0';										-- d'attente des ports
-							  elsif TimeOut=800 then
-									Next_stInit2 <=EndInit ;-- impossible d'envoyer sur le NoC
-							   assert true report "Ex4:SendPeerStat Timeout -> Impossible d'envoyer sur le NoC"
-				        severity failure;
-							  else
-									TimeOut_i<=TimeOut+1; 
-							end if;
-					end if;
-					elsif PeerRTS='1' then -- le dernier port est il activé ?
-						if I_Send_RDY='1' then  
-								RankSent_i<='1';  	-- les stat ont été envoyé
-										TimeOut_i<=0;  	 	-- prépare le traitement de la prochaine requête
-										PeerRts_i<='0';
-							if statAsked='1' then 
-							 -- Next_stInit2<=ReadNoc;
-							
-							Next_stInit2<=SendApp; --terminer l'application
-						  end if;
-						
-						elsif TimeOut=100 then
-							Next_stInit2 <=EndInit;
-							assert true report "Ex4:SendPeerStat Timeout -> Impossible d'envoyer sur le NoC"
-				        severity failure;
-						else 
-							TimeOut_i<=TimeOut+1; 
-						end if;
-					else
-						Next_stInit2<=SendApp;
-					end if;
-		When SendApp =>  -- envoyer au programme un signal 
-					-- et attendre un acquittement et l'adresse de base
-					If AppAck='1' then
-						Next_stInit2 <=EndInit;
-					end if;
-		
-		When SpawnLoad =>
-		
-				if n=0 then
-					ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0)));
-					vPeerStat_i<=PeerStat; --récupérer la situation actuelle des tâches créées
-					if IsMain1='1' and SpawnInit='0' then 
-					 SpawnNbReq<=to_integer(unsigned(Instruction(3 downto 0))); -- sauver le nombre de HT à créer
- 
-					n_i<=1;
-					SpawnReq(ht_id)<='1'; --Note l'id de HT qui a appelé le Spawn
-					elsif IsMain1='1' and SpawnInit='1'  then -- il faut envoyer les acquittements
-					ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0)));
-					Spawn_grp(grp_id)(ht_id)<='1'; --noter le port du Fils Spawné dans ce groupe
-					Ht_start_i<=0; --compte le nombre de tâches chargées
-							n_i<=6;
-					
-					else 
-					   if SpawnOn='1' then --if IsMain_i='0' then  -- il faut juste charger puis activer la tâche
-					     n_i<=7;
-					    end if;
-					    assert true
-					   Report "SpawnLoad : Cas non prévu !"
-					  severity failure;
-					end if;
-				elsif n=1 then
-				if PeerStat=SpawnReq then --tous les Hts ont appelés Spawn ?
-				ht_hole:='0';		
-	L1:			for i in 0 to 15 loop
-						if vPeerStat(i)='0' then
-							SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à activer
-							SpawnCmd0<=MPI_SPAWN & std_logic_vector(to_unsigned(i,4));
-							vPeerStat_i(i)<='1';
-							Ht_Start_i<=Ht_Start+1;
-							Ht_Hole:='1'; -- une place a été trouvé
-						else
-							Ht_hole:='0'; -- pas de place trouvé
-						end if;
-						exit L1 when ht_hole='1';
-					end loop L1;
-					if Ht_hole='0' then -- toutes les tâches n'ont pas été créés
-						-- aller à la fin ! en signalant une erreur!
-						SpawnCMd2<=Spawn_Err & "0001"; --erreur pas assez de ports sur le NoC
-						n_i<=9;
-					else
-						n_i<=n+1;
-						SpawnCmd1<=PeerStat(7 downto 0);
-						SpawnCmd2<=SPAWN_START & MyPort;
-					end if;
-					else --Tous les Hts n'ont pas appelé Spawn encore
-					  Next_stInit2<=SendApp; --on termine normalement
-					  n_i<=0;
-					end if;
-				elsif n=2 then
-				PeerRTS_i<='1'; -- envoyer les données du Spawn
-				n_i<=n+1;
-				elsif n=3 then
-					if I_Send_RDy='1' then
-						n_i<=n+1;
-						PeerRts_i<='0';
-					end if;
-				elsif n=4 then
-					if SpawnInit='0' then
-					if Ht_Start>=SpawnNbReq then
-						n_i<=n+1;
-					else
-						n_i<=1; -- passer à la création du HT suivant
-					end if;
-					else
-						n_i<=7; -- passer au contact du HT suivant
-					end if;
-				elsif n=5 then
-								-- Aller à la fin le résultat du Spawn
-				
-				n_i<=10;
-				elsif n=6 then
-				  nbSpawn:=0;
-				  for i in 0 to 15 loop
-				      if Spawn_grp(grp_id)(i)='1' then
-				         nbSpawn:=nbSpawn+1;
-				       end if;
-				   end loop;
-				  if nbSpawn=SpawnNbReq then
-				  n_i<=n+1; --aller renvoyer les réponses
-				  else
-				    n_i<=10; --fin du Spawn
-				    
-				   end if;
-				elsif n=7 then
-				Ht_hole:='0';
-L2:			for i in 0 to 7 loop --for i in Ht_start to 7 loop
-						if i>=Ht_start then
-						if vPeerStat(i)='1' and Spawn_grp(grp_id)(i)='0' then  --on avertit les membres du groupe parent
-						  --mais pas ceux du groupe Fils !
-							SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à avertir
-							SpawnCmd0<=MPI_ACK & std_logic_vector(to_unsigned(i,4));
-							vPeerStat_i(i)<='0';
-							Ht_Start_i<=i+1; -- le prochain Ht à prévenir 
-							Ht_Hole:='1'; -- Une tâche doit être avertie
-						else
-							Ht_hole:='0'; -- 
-						end if;
-						end if;
-						exit L2 when ht_hole='1';
-					end loop L2;
-					n_i<=n+1;
-			elsif n=8 then
-				 if Ht_hole='1' then --
-						-- un HT existant à prévenir ! 
-						SpawnCmd1<=Spawn_grp(grp_id)(7 downto 0);
-						SpawnCMd2<=MPI_SPAWN & MyRank; -- fin du Spawn
-						n_i<=2; --envoyer la  donnée sur le réseau
-					elsif vpeerstat /=spawn_grp(grp_id) then --il ne reste plus de membres à prévenir ?
-              n_i<=7; --on est sorti mais ce n'est pas la fin
-
-					else -- fin du Spawn car tous ont été averti
-						n_i<=10;
-						SpawnNbReq<=0;
-						SpawnReq<=(others=>'0');
-						vPeerStat_i<=(others=>'0');
-						grp_id_i<=grp_id+1; --incrementer le compteur de groupes************
-					end if;
-				elsif n=9 then
-				  assert true report "error in Spawn command"
-				   severity failure;
-				elsif n=10 then
-				  n_i<=0;
-				  Next_stInit2<=SendApp;
-				 end if;
-		
-	When SpawnApp=>
-	  	--Mise à jour du bit 6 du registre status du COre.
-		if n>=0 and n <4 then     
-			
-			dma_wr<='1';  --demander un accès exclusif au bus
-			dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-		else
-			dma_wr<='0';										
-			dma_rd<='0';
-		end if;
-		
-		if n=0 then
-		  if DS_RDY='1' then ---
-		      if Datareceived(3)(7 downto 4)=SPAWN_START then
-		        n_i<=n+1;
-		       else
-		         Next_stInit2<=ErrSpawn;
-		         n_i<=0; --erreur instruction incorrecte
-		        end if;
-			   
-			   rd_ok<='1';
-			   wr_ok<='0';
-			end if;
-		elsif n=1 or n=2 then
-			if dma_rd_grant='1' then
-				n_i<=n+1;
-				tempval:=Ram_data_out;
-			end if;
-				rd_ok<='1';
-				wr_ok<='0';
-			 
-		elsif n=3 then
-				if dma_rd_grant='1' and dma_wr_grant='1' then
-					n_i<=n+1;
-					tempval:=Ram_data_out;
-					tempval(6):='1';  	
-							
-					dataToram<=tempval;
-					rd_ok<='0';
-					wr_ok<='1';
-				else
-					rd_ok<='1';
-					wr_ok<='0';
-				end if;
-		elsif n=4 then
-		if spawninit='0' then
-		  Spawn_done_i<='1';
-		end if;
-		rd_ok<='0';
-		wr_ok<='0';
-		n_i<=0;
-		Next_stInit2<=EndInit;
-		end if;
-			
-		When ErrSpawn =>
-		  assert true
-		  report "Ex4/stInit2/SpawnApp:Erreur lors de Spawn"
-		  severity failure;
-			Next_stInit2<=Init;
-		When EndInit=>
-		  
-			StatAsked_i<='0'; --reset de ces variables
-			Next_stInit2<=Init;
-      end case;      
-   end process;
-	
---================================================
---sauvegarde du rang et du main port à l'adresse de retour de la fonction Init
---==================================================
-
---====================================================
---envoie des données sur le port
---===================================================
-selector<=(Rcv_on,Cmd_on,Snd_on);
-
-process (selector,Rport_out_rd_en,cport_out_rd_en,sPort_in_wr_en ,cPort_in_wr_en,
-				tosend ,tosend4)
-begin
-   case selector is
-	
-      when "000" => port_in_data<=(others=>'-');
-						Port_in_wr_en<='0';
-						Port_out_rd_en<='0';
-      
-		when "001" => port_in_data<=tosend; --envoie de données
-						Port_in_wr_en<=sPort_in_wr_en ;
-						Port_out_rd_en<='0';
-      when "101" => port_in_data<=tosend; --envoie de données
-						Port_in_wr_en<=sPort_in_wr_en ;
-						Port_out_rd_en<=Rport_out_rd_en ;
-		when "010" | "110" | "011" | "111" => 
-						port_in_data<=tosend4; --envoie de commande GetPort
-						Port_in_wr_en<=cPort_in_wr_en;
-						Port_out_rd_en<=cport_out_rd_en;
-     
-	  when "100" => port_in_data<=(others=>'-'); -- réception de données
-						Port_in_wr_en<='0';
-						Port_out_rd_en<=Rport_out_rd_en ;
-      
-		when others => port_in_data<=(others=>'-');
-							Port_in_wr_en<='0';							
-							Port_out_rd_en<='0';
-   end case;
-end process;
- 
---==================================================	
-	
-	--===============================================================
-	--processus d'accès au réseau
-	--===============================================================
-
-
-
-
-
-	preceiv:process(clk,reset)
-	
-	variable origport,destport : natural range 0 to 15;
-	variable dcount,dlen ,rtimeout:natural range 0 to 1023;
-	variable ptype : std_logic_vector(3 downto 0);
-	variable bad_paquet :std_logic:='0';
-	begin
---				
-	
-	if reset='1' then
-		etrec<=r_wait;
-		destport:=1;
-		rtimeout:=0;
-		bad_paquet:='0';
-	else
-	if  rising_edge(clk) then 
-			case  etrec is
-			when r_wait =>
-				
-				rtimeout:=0;
-				bad_paquet:='0';	
-				--modifier le 01-08-pour gérer le Spawn
-			if Port_out_data_available='1' and Cmd_on='0' then 
-				ptype:=port_out_data(7 downto 4);
-				origport:=to_integer(unsigned(port_out_data(3 downto 0)));
-				
-				if ptype=MPI_SPAWN and not(portnumflag='1') then
-						etrec<=r_dlen; --identification de la signature d'en tête valide
-						Datareceived(0)<=Port_out_data; --stocker l'entête
-						bad_paquet:='0';
-						SpawnOn<='1'; --le spawn est actif
-				elsif Instruction_en='0' and CTR='0' and Hcl_init= '0' then
-				  --il faut éliminer ce paquet qui est inoportun !
-				  Bad_paquet:='1';
-				  etrec<=r_dlen; --il faut ignorer cette donnée et quitter
-					dcount:=1;
-				elsif CTR='1' then
-				if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN or ptype=INIT_REGISTER then 
-						etrec<=r_dlen; --identification de la signature d'en tête valide
-						Datareceived(0)<=Port_out_data; --stocker l'entête
-						bad_paquet:='0';
-				else
-					--une donnée non attendue est présente sur le port
-					etrec<=r_dlen; --il faut ignorer cette donnée et quitter
-					dcount:=1;
-					bad_paquet:='1';
-					Datareceived(0)<=(others=>'0');
-				end if;
-				end if;
-			--elsif Port_out_data_available='1' and CTR='0' then
-			--		etrec<=r_drop;
-			else
-				
-				etrec<=r_wait;
-			end if;
-			DS_RDY<='0';
-			When r_drop => -- ignorer les messages qui arrivent à ce noeud tant que 
-								--l'application n'a pas été initialisée
-						if port_out_data_available='0' then 
-							etrec<=r_end;
-							dcount:=0;
-							
-						end if;
-						
-						
-						
-						--Rport_out_rd_en<='1'; --lire les données qui sont dans le tampon de sortie		
-						DS_RDY<='0';
-			when r_Dlen =>   --positionnement du mot de longueur des données
-			if Port_out_data_available ='1' then 
-			
-			--Rport_out_rd_en<='1';
-			etrec<=r_glen;
-			rtimeout:=0;
-			else
-				rtimeout:=rtimeout+1;
-					if rtimeout>=30 then 
-					  assert true report "Ex4:etrec r_glen Timeout -> Impossible de recevoir du NoC"
-				        severity failure;
-					Exectime_out<='0';  --read Noc time out
-						etrec<=r_end;             -- données pas prêtes
-					end if;
-			
-			
-			end if;
-			DS_RDY<='0';
-			--  
-			when r_glen =>   --lecture effective de la longueur des données
-			if port_out_data_available='1' then 
-			dlen:=to_integer(unsigned(port_out_data(Word-1 downto 0)));
-			Datareceived(1)<=Port_out_data;
-			--RPort_out_rd_en<='0';
-			etrec<=r_data;
-			dcount:=2;  -- initialisation du compteur de reception (il y a 
-							-- déjà deux mots reçues
-			else
-				rtimeout:=rtimeout+1;
-					if rtimeout>=30 then 
-					 assert true report "Ex4:etrec Timeout -> Impossible de recevoir sur le NoC"
-				        severity failure;
-					ExecTime_out<='0';
-						etrec<=r_end;             -- données pas prêtes
-					end if;
-			
-			end if;
-			DS_RDY<='0';
-			when r_data =>    					-- lecture des données
-			if port_out_data_available='1'  then 
-					
-					--Rport_out_rd_en<='1';   --autoriser la lecture
-					if bad_paquet='0' then
-						DataReceived(dcount)<=Port_out_data; --récupération des données
-					else
-						DataReceived(2)<=(others=>'0');
-					  --ignorer ces données
-					end if;
-					--assert true report "Donnée lue :"; --& string(unsigned(port4_out(Word-1 downto 0)))
-					DS_RDY<='0';
-					dcount:=dcount+1;
-					--severity note;
-					if dlen <=dcount then -- ce doit être égale ici et non <= ???
-						etrec<=r_end;
-						DS_RDY<= not bad_paquet; -- jeu de données disponibles
-					elsif dcount=255 then   --dépassement de la capacité
-						DS_RDY<='0';
-						etrec<=r_end;
-					end if;
-			else
-					rtimeout:=rtimeout+1;
-					if rtimeout>=30 then 
-					   ExecTime_out<='0';
-						etrec<=r_end;             -- données pas prêtes
-					end if;
-					DS_RDY<='0';
-					
-			end if;
-			when r_pulse =>
-					etrec<=r_end; 
-					DS_RDY<=not bad_paquet;
-			when r_end =>
-						
-			--rPort_out_rd_en <='0';
-			
-			if DS_ACK='1' or rtimeout> 30 or (CTR='0' and SpawnOn='0') or bad_paquet='1' then 
-				DS_RDY<='0';
-				SpawnOn<='0';
-				etrec<=r_wait;
-			else
-				DS_RDY<=DS_RDY;
-			end if;			
-			end case;
-		 end if;--reset='1'
-		end if;   
-  end process preceiv;
-  
- val_preceiv: process (etrec)
-  begin
-  case etrec is
-					when r_wait  =>
---						DS_RDY<='0';
-						rcv_on<='0';
-						Rport_out_rd_en <='0';
-					when r_dlen  =>
---							DS_RDY<='0';
-							Rport_out_rd_en <='1';
-							rcv_On<='1';
-					when r_drop  =>
---							DS_RDY<='0';
-							Rport_out_rd_en <='1';
-							rcv_On<='1';
-					when r_glen =>
-							Rport_out_rd_en <='1';
---							DS_RDY<='0';
-							rcv_On<='1';
-					when r_data =>
-							Rport_out_rd_en <='1';
---							DS_RDY<='0';
-							rcv_On<='1';
-					when r_pulse =>
-								Rport_out_rd_en <='0';
-								rcv_On<='1';
---								DS_RDY<='1';
-					when r_end =>
-							Rport_out_rd_en <='0';
---							DS_RDY<='0';
-							rcv_On<='0';
-					when others =>
-							Rport_out_rd_en <='0';
---							DS_RDY<='0';
-							rcv_On<='0';
-				end case;
-	end process;
-  
-  psend:process(clk,reset)
-		--génération des paquets à partir du  port courant
-		variable pactype :natural range 0 to 15;
-		variable destport : natural range 0 to 15:=0;
-		variable realdlen, i,i_pair : natural range 0 to 255;
-		variable MaxPort : natural :=4; -- en fait ne doit pas être 0
-		
-		
-				begin
-				if rising_edge(clk) then 
-						 if reset='1' then 
-								etsnd<=s_init;
-				 
-				    
-						 
-						else -- le process s'exécute sur chaque front 
-															-- montant de l'horloge
-						case etsnd is
-						when s_init => tosend<=(others=>'-');
-											MaxPort :=to_integer(unsigned(NOCMAX));
-								sPort_in_wr_en<='0';
-							if port_in_full='0' and Rts_dat='1' then   --on peut aussi tester si le port est vide
-							        BCast_RDY<='0';  -- pas la fin de du Broadcasting
-									  Send_RDY<='0';
-									  Snd_on<='1';
-									  if Bcast='1' then -- envoyer à tous les ports le même message ?
-									  DestPort :=0;
-									  else
-										DestPort:=to_integer(unsigned(data_to_send(0)(3 downto 0)));
-									  end if;
-									  etsnd<=s_head;
-							end if;
-						when s_head  =>    -- construction et envoie de l'en-tête
-						Send_RDY<='0'; --l'envoi commence
-						BCast_RDY<='0';
-						Snd_on<='1';
-						--pactype:=to_integer(MPI_INIT);--
-						pactype:=to_integer(unsigned(data_to_send(0)(7 downto 4)));
-						--realdlen:=to_integer(unsigned(Datalen));
-						--? destport:=MAXPORT; -- le port de destination
-						
-						tosend <=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
-						 sPort_in_wr_en<='1';   -- 
-						 
-						 i:=1;
-						 etsnd<=s_len2;  -- passer à l'état suivant
-						 
-						when s_len => 
-							BCast_RDY<='0';
-							Send_RDY<='0';
-							Snd_on<='1';
-							--tosend<=(STD_LOGIC_VECTOR(to_unsigned(Realdlen,8)));
-							tosend<=data_to_send(1);
-							sPort_in_wr_en <='1';
-							
-
-							--port1_in<=tosend1; --copie directe sur le port 
-							etsnd<=s_len2;
-						when s_len2 => 
-							--tosend<=(STD_LOGIC_VECTOR(to_unsigned(realdlen,8)));
-							sPort_in_wr_en<='1';
-							tosend<=data_to_send(1);
-
-							--port1_in<=tosend1; --copie directe sur le port 
-							etsnd<=s_data;	
-							BCast_RDY<='0';
-							Send_RDY<='0';
-							Snd_on<='1';
-							i:=i+1;
-						when s_data =>
-							Snd_on<='1';
-							if Port_in_full='0' and RTS_dat='1' then
-								sPort_in_wr_en<='1';
-								
-								     --envoie des données sur le port   
-									tosend<=data_to_send(i);
-								
-								
-								if i+1>=datalen then 
-									etsnd<=s_end;
-									Send_RDY<='1'; --l'envoi est terminé
-									if BCast='1' and destport=MAXPort then
-										BCAST_RDY<='1'; --l'envoi collectif aussi
-									else 
-										BCast_RDY<='0';
-							
-									end if;
-								else
-									BCast_RDY<='0';
-									Send_RDY<='0';
-									i:=i+1;
-								end if;
-							elsif port_in_full='1' then
-          							sPort_in_wr_en<='0';
-							else
-								sPort_in_wr_en<='0';
-								BCast_RDY<='0';
-								Send_RDY<='0';
-							end if;
-						when s_end  =>
-						 tosend<=(others=>'-');
-							
-							sPort_in_wr_en<='0';
-							if Bcast='1' then
-							if destPort<Maxport then
-								DestPort:=Destport+1;
-								etsnd<=s_head;
-								
-								else
-								BCast_RDY<='1' ; -- BroadCast End=Ok
-									if Send_ack='1' then
-										etsnd<=s_init;
-										Send_RDY<='0';
-										Snd_on<='0';
-									end if;
-								end if;
-							else
-								BCast_RDY<='0';
-								if Send_ack='1' then
-									etsnd<=s_init;
-									Send_RDY<='0';
-									Snd_on<='0';
-								end if;
-								
-							end if;
-						end case;	
-						
-										
-						end if;  --reset ='1'
-					end if; --rising_edge...
-		end process psend;	
-
--- envoi des commandes		
-pcmd:process(clk,reset)
-	
-	variable origport,destport,pid,mport : natural range 0 to 15;
-	variable ctimeout:natural range 0 to 255;
-	begin
-	
-	
-		if reset='1' then
-			etcmd<=cmdstart;
-			
-	--		sorigport<=origport;
-		else
-		if  rising_edge(clk) then
-					case  etcmd is
-					when cmdstart =>
-						if Port_in_empty='1' and RTS_Cmd='1' then 
-									etcmd<=cmdpost;
-						
-						end if;
-						destport:=0;
-						ctimeout:=0;
-						origport:=1;
-				 when cmdpost =>
-					if Port_in_empty='1' then 
-						etcmd<=cmdread;
-					end if;
-					
-				when cmdpostidle  =>   --permet juste la prise en compte de la commande
-						etcmd<=cmdread;
-						dcount<=0;-- initialisation du compteur de reception
-				 when cmdread =>
-						
-						
-						ctimeout:=0;
-						
-					if Port_out_data_available='1' then 
-						mport:=to_integer(unsigned(port_out_data(7 downto 4)));
-						pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1;
-						CmdReceived(dcount)<=port_out_data;
-						--cdata_out_en(origport)<='1';
---						if pid=origport then --le port a été bien identifié
-								etcmd<=cmdglen; --
-								dcount<=dcount+1;
---							else
---							etcmd<=cmdtimeout;
---						end if;
-					else
-
-						etcmd<=cmdread;
-					end if;
-					
-					
-					when cmdlen =>   --positionnement du mot de longueur des données
-					if Port_out_data_available='1' then 
-					
-					etcmd<=cmdglen;
-					ctimeout:=0;
-					else
-						ctimeout:=ctimeout+1;
-							if ctimeout>=30 then 
-							  assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC"
-				        severity failure;
-								etcmd<=cmdtimeout;             -- données pas prêtes
-							end if;
-					
-					
-					end if;
-					when cmdglen =>   --lecture effective de la longueur des données
-					if Port_out_data_available='1' then 
-						cdlen<=to_integer(unsigned(port_out_data(Word-1 downto 0)));
-						CmdReceived(dcount)<=port_out_data;
-						etcmd<=cmddata;
-					  dcount<=dcount+1;
-					else
-						ctimeout:=ctimeout+1;
-							if ctimeout>=30 then 
-							--time_out(destport)<='1';
-							 assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC"
-				        severity failure;
-								etcmd<=cmdtimeout;             -- données pas prêtes
-							end if;
-					
-					end if;
-					
-					when cmddata =>
-					if (port_out_data_available='1' and ctimeout<30) then 
-							
-							--cdata_out_en(origport)<='1';
-							mport:=to_integer(unsigned(port_out_data(7 downto 4)));
-							--attention les ports sont numérotés à partir de 0
-							pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1;
-							CmdReceived(dcount)<=port_out_data;
-							if (dcount>=cdlen-1 ) then--attention le compteur de données commence à 0
-								etcmd<=cmdend;
-								--CM_RDY<='1';
-							else
-								dcount<=dcount+1;
-							end if;			
-					Else
-							
-							if ctimeout>=30 then 
-								--time_out(destport)<='1';
-								etcmd<=cmdtimeout;             -- données pas prêtes
-							 assert true report "Ex4:etcmd. cmddata Timeout -> impossible de recevoir du le NoC"
-				        severity failure;
-							else
-							ctimeout:=ctimeout+1;
-							etcmd<=cmdend;
-							end if;
-					end if;
-					when cmdend =>
-				
-							etcmd<=cmdstart;
-
-					when cmdtimeout =>
-
-					  etcmd<=cmdstart;
-					end case;
-		--sorigport<=origport;	
-		end if;   --reset='1'
-	end if;
-  end process pcmd;	
-
-majetcmd: process (etcmd,data_to_send, port_out_data_available, dcount,port_out_data)
-variable origport : natural;
-variable i:natural:=0;
-	begin
-			case  etcmd is
-		when cmdstart =>
-				i:=0;
-				Port_in_cmd_en<='0';
-				tosend4<=(others=>'-');
-				cport_out_rd_en<='0';
-				cport_in_wr_en<='0';
-				CM_RDY<='0';
-				Cmd_on<='0';
-		 when cmdpost | cmdpostidle =>
-				cport_in_wr_en<='1';
-				tosend4<=data_to_send(0); ---code pour getportid
-				Port_in_cmd_en<='1';
-				cport_out_rd_en<='0';
-				CM_RDY<='0';
-				Cmd_on<='1';
-		 when cmdread =>
-				tosend4<=(others=>'-');
-				cPort_in_wr_en<='0';
-				cport_out_rd_en<=port_out_data_available;
-				--CmdReceived(dcount)<=port_out_data;  --mettre les données dans le tampon
-				Port_in_cmd_en<='1';
-				CM_RDY<='0';
-				Cmd_on<='1';
-		when cmdlen |cmdglen =>   --positionnement du mot de longueur des données
-					tosend4<=(others=>'-');
-					cport_in_wr_en<='0';
-					cport_out_rd_en<=port_out_data_available;
-					Port_in_cmd_en<='1';
-					--CmdReceived(dcount)<=	port_out_data;
-					CM_RDY<='0';
-					Cmd_on<='1';
-		when cmddata =>
-					tosend4<=(others=>'-');
-					cport_in_wr_en<='0';
-					cport_out_rd_en<=Port_out_data_available;
-					Port_in_cmd_en<='1';
-					--CmdReceived(dcount)<=port_out_data;  --mettre les données dans le tampon
-					i:=i+1;
-					CM_RDY<='0';
-					Cmd_on<='1';
-			when cmdend =>
-					tosend4<=(others=>'-');
-				cport_in_wr_en<='0';
-				cport_out_rd_en<='0';
-				--CmdReceived(dcount)<=port_out_data; 
-				Port_in_cmd_en<='0';
-			    CM_RDY<='1';
-				 Cmd_on<='0';
-			when cmdtimeout =>
-					tosend4<=(others=>'-');
-				  cport_in_wr_en<='0';
-				  cport_out_rd_en<='0';
-				  Port_in_cmd_en<='0';
-					Cmd_on<='1';
-					cm_rdy<='0';
-			end case;
-		
-end process majetcmd ; 
-
-i_send_val:process(HCL_Init,Send_RDY,RTS_I,Snd_Ack,I_send_ack,data_to_send,Bcast_rdy,Bcast)
-begin
-snd_start_i<=snd_start;
-RTS_DAT<='0';
-
-if HCL_Init='1' then
- if RTS_I='1' and snd_ack='0' then
-  snd_start_i<='1';
- elsif i_send_ack='1' then
- 
- snd_start_i<='0';
- else
-   snd_start_i<='0';
- end if;
-  i_send_rdy<=snd_ack;
-
-  Snd_data<=data_to_send;
-else
-  if RTS_I='1' and i_send_ack='0' then
-  RTS_DAT<='1';
- elsif i_send_ack='1' then
- 
- RTS_DAT<='0';
- end if;
- i_send_rdy<=send_rdy;
- for i in 0 to 3 loop 
- Snd_data(i)<=(others=>'0');
- end loop;
-end if;
-end process;
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/EX4_FSM.vhd.bak
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/EX4_FSM.vhd.bak	(revision 96)
+++ 	(revision )
@@ -1,1948 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: GAMOM 
--- 
--- Create Date:    14:44:36 03/07/2012 
--- Design Name: 
--- Module Name:    EX4_FSM - Behavioral 
--- Project Name: MPI_CORE_COMPONENTS
--- Target Devices: SPARTAN 3E xc3s1200e
--- Tool versions: 
--- Description: Ce module renferme les fonctions permettant d'initialiser la 
--- bibliothèque matériel MPI
--- Dependencies:
---
--- Revision: 25/juin/2012 au 24/Octobre/2012
--- Revision 0.03 - File updated
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
-Library NocLib;
-use NoCLib.CoreTypes.all;
-use work.packet_type.all;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity EX4_FSM is
-    Port ( Instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Instruction_En : in  STD_LOGIC;
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           ResultOut : out  STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0');
-           Result_En : out  STD_LOGIC:='0';
-           Ready : out STD_LOGIC; --indique que le module est disponible
-           NocSize : out  STD_LOGIC_VECTOR(3 downto 0);
-			     PortId : out  STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');
-           AppRank : out  STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');
-           AppSize : out  STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');
-           IsMain : out  STD_LOGIC;
-           I_fifo_full :in STD_LOGIC; --instruction fifo
-		       I_fifo_wr_en: out STD_LOGIC;--instruction fifo Write enable
-		       I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); --instruction fifo data
-			     Initialized : out STD_LOGIC;
-			  Snd_Ack : IN std_logic;
-		Rec_Rdy : IN std_logic;
-		Rec_Data : IN Typ_PortIO(0 to 3);
-		Snd_data : OUT Typ_PortIO(0 to 3);
-		Snd_Start : buffer std_logic;
-		Rec_Ack : OUT std_logic;       
-				   dma_wr_grant : in  STD_LOGIC;
-				   dma_wr_request : out  STD_LOGIC;
-				dma_rd_grant : in  STD_LOGIC;
-				dma_rd_request : out  STD_LOGIC;
-				ram_rd : out std_logic;
-				ram_wr : out std_logic;
-				ram_address : out std_logic_vector(ADRLEN-1 downto 0);--accès au stockage
-				Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-				Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
-			
-			  AppAck : in  STD_LOGIC;
-           AppReq : in  STD_LOGIC;
-			  port_in_cmd_en : out  STD_LOGIC:='0';
-			  port_in_wr_en : out  STD_LOGIC:='0';
-			  port_in_empty : in  STD_LOGIC;
-           port_in_full : in  STD_LOGIC;
-           port_in_data : out  STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'-');
-			  port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           port_out_rd_en : out  STD_LOGIC:='0';
-           port_out_data_available : in  STD_LOGIC);
-end EX4_FSM;
-
-architecture Behavioral of EX4_FSM is
-
-COMPONENT SetBit
-	PORT(
-		clk : IN std_logic;
-		reset : IN std_logic;
-		BitNum : IN std_logic_vector(0 to 2);
-		BitVal : IN std_logic;
-		dma_wr_grant : IN std_logic;
-		dma_rd_grant : IN std_logic;
-		Ram_data_in : IN std_logic_vector(7 downto 0);
-		   
-		dma_wr_request : OUT std_logic;
-		dma_rd_request : OUT std_logic;
-		ram_rd : OUT std_logic;
-		ram_wr : OUT std_logic;
-		ram_address : OUT std_logic_vector(15 downto 0);
-		Ram_data_out : OUT std_logic_vector(7 downto 0)
-		);
-	END COMPONENT;
-Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in;
-Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out;
-
-	--MAE pour emission de init
-   --type init1_type is (init,NocSize,InitToNoc,NextPort,EndBCast); 
-	--	MAE pour affectation des rangs aux différentes librairies MPI
-	type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,ReadNoc,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendPeerStat,AskPeerStat,GetPeerStat,SendApp,SpawnApp,SpawnLoad,ErrSpawn,EndInit);
-   -- MAE pour réception de init depuis le réseau;
-	type init3_type is  (init,GetNocSize,ReadInitHead,StorePort,EndInit); 
-	type typ_send is (s_init,s_head,s_len,s_len2,s_data,s_end);
-	type typ_receiv is (r_wait,r_dlen,r_drop,r_glen,r_data,r_pulse,r_end);
-	type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout);
-  type typ_mem16 is array(natural range <>) of std_logic_vector(15 downto 0);--
-		signal etsnd : typ_send;
-		signal etrec:typ_receiv;   --pour la machine à état de réception
-		signal etcmd :typ_cmd;     --pour la machine à état de commande
-signal IS_state,next_Is_state : natural range 0 to 3:=0;
-
---	signal stInit1, next_stInit1 : init1_type; 
-	signal stInit2, next_stInit2 : init2_type; 
-	--signal stInit3, next_stInit3 : init3_type; 
-	--signaux pour l'interface avec les ports
-	signal cport_in_wr_en,sport_in_wr_en:std_logic;
-	signal cport_out_rd_en,rport_out_rd_en:std_logic;
-	signal rdy:std_logic:='0'; --signal busy/ready
-	signal tosend,tosend4 :std_logic_vector(Word-1 downto 0);
-	signal PeerStat,PeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres Lib initialisées
-  signal SpawnReq,SpawnReq_Q : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres HT qui ont appelés le Spawn	
-	signal Spawn_grp,Spawn_grp_Q :typ_mem16(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); --un max de quatre groupes de fils est prévu
-	signal Grp_id,grp_id_i :natural range 0 to 3:=0; --id du groupe des HT fils
-	signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port
-	--signaux pour les états des MAE
-	signal  NocSizeOk,PortCountFlag : std_logic;
-	signal PortNumFlag,PortNumFlag_i,EquFlag,EquFlag_i,MainResp: std_logic:='0';
-	signal StatAsked,RankAsked,RankSent:std_logic;
-	signal  nextr,nextr_i : natural :=0;
-   signal RTS_cmd,RTS_dat,RTS_I,CTR,BCast,Send_Ack,DS_Ack,CM_Ack:std_logic:='0';
-	signal I_Send_Ack,I_Send_Rdy:std_logic:='0';
-	signal Rcv_On,Snd_On,Cmd_On : std_logic:='0'; --status des MAE d'envoie et de réception
-	signal SpawnOn,SpawnInit :std_logic:='0'; --indique que le Spawn est activé
-	signal SpawnNbReq,SpawnNbAck,SpawnNBAck_i : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement
-	signal SpawnNbReq_Q : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement
-	signal SpawnCmd0,SpawnCmd1, SpawnCmd2 :std_logic_vector(Word-1 downto 0):=(others=>'0');
-	signal SpawnCmd0_Q,SpawnCmd1_Q, SpawnCmd2_Q :std_logic_vector(Word-1 downto 0):=(others=>'0');
-	signal SpawnDest :std_logic_vector(3 downto 0);
-	Signal Ht_Start,Ht_Start_i : natural range 0 to 15:=0;
-	Signal vPeerStat,vPeerStat_i : std_logic_vector(15 downto 0):=(others=>'0');
-	signal IsMain_i,IsMain1,Initialized_i,HCL_init,HCL_Init_i: std_logic:='0';
-	signal DS_RDY ,BCast_Rdy,Send_RDY,CM_RDY:std_logic:='0';
-	signal ExecTime_out:std_logic;
-	--signaux de gestion de la RAM
-	signal Ram_Next_Address : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16));
-	signal Ram_NExt_Address_i :std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16));
-	signal n,n_i:natural range 0 to 15 :=0;
-	signal n0,n0_i:natural range 0 to 7:=0;
-	signal DataToRam : std_logic_vector(Word-1 downto 0) ;
-	signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
-	--Signaux des résultats et de l'état
-  signal PortNum_i,PortNum,MyPort : std_logic_vector(3 downto 0);  -- 
-	signal NocMax ,NocMax_i: std_logic_vector(3 downto 0):=(others=>'0'); -- Nombre de ports du réseau -1 ?
-	signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE
-	signal AppSize_i,AppSize1:std_logic_vector(3 downto 0) ;--taille de l'application
-	signal Spawn_done,Spawn_done_i:std_logic:='0'; --indique que le Spawn a été effectué
-	signal MainPort,MainPort_i : std_logic_vector(3 downto 0) ; --Port de la lib main
-	signal NextRank,NextRank_i : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI
-   signal Data_To_Send,Data_to_send_i : Typ_PortIo(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); -- permet d'empiler les données à envoyer
-	signal RankToPort :Typ_PortIo(0 to 15);--permet d'associer un port réseau à chaque  rang
-	signal CmdReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
-	signal DataReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
-	signal Datalen,DataLen_i : natural range 0 to 7:=0; --indique la longueur des données
-	--other outputs
-	signal StatAsked_i,RankAsked_i,MainResp_i,RankSent_i,Result_i:std_logic:='0';
-	signal snd_start_i:std_logic:='0';--version interne des signaux de sortie
-   --signal BCast_Rdy_i : std_logic;
-	signal cdlen,dcount : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd
-	signal timeout,timeout_i : natural range 0 to 4095:=0;
-	signal PortStat,PortStat_i : std_logic_vector(3 downto 0):=(others=>'0');
-	signal PeerPort,PeerPort_i : natural range 0 to 15:=0; -- désigne le port qui emet une requête
-	signal PeerRTS,PeerRTS_i,PeerCTR:std_logic:='0';
-	signal cpt,cpt_peer : natural range 0 to 31:=0; --compteur pour le nombre de HT initialisés
-	signal clk_cyl,clk_cyl_i : natural range 0 to 15:=0;
-begin
---=======================================================================================
---fonctions du module
---=======================================================================================
---=======================================================================================
- 
--- Inst_SetBit: SetBit PORT MAP(
---		clk => clk,
---		reset => reset ,
---		ce => cmd,
---		BitNum => ,
---		BitVal => '1',
---		dma_wr_grant => dma_wr_grant ,
---		dma_wr_request => dma_wr_request,
---		dma_rd_grant => dma_rd_grant,
---		dma_rd_request => dma_rd_request,
---		ram_rd => ram_rd,
---		ram_wr => ram_wr,
---		ram_address => ,
---		Ram_data_in => Ram_data_in,
---		Ram_data_out => Ram_data_out
---	);
-
- 
-   -- Gestion de l'initialisation du Core MPI
-  sync_Init2 : process (clk,reset)
-  begin
-	if reset='1' then
-		stinit2<=init;
-		StatAsked<='0';
-		MyPort<=(others=>'0');
-		NextRank<=(others =>'0');
-	elsif rising_edge(clk) then
-		stinit2<=next_stinit2;
-		IS_State<=Next_IS_State;
-		n0<=n0_i;
-		--ajout des autres affectations ici
-		Ram_Next_Address<=Ram_Next_Address_i;
-		PortNumFlag<=PortNumFlag_i;
-		RankAsked<=RankAsked_i;
-		RankSent<=RankSent_i;
-		AppRank<=MyRank;
-		timeout<=timeout_i;
-		cpt<=cpt_peer;
-		clk_cyl<=clk_cyl_i;
-		NextRank<=NextRank_i;
-		StatAsked<=StatAsked_i;
-		MainResp<=MainResp_i;
-		AppSize1<=AppSize_i;
-		n<=n_i;
-		Ht_Start<=Ht_Start_i;
-		Grp_Id<=Grp_Id_i;
-		vPeerStat<=vPeerStat_i;
-		SpawnNbAck<=SpawnNbAck_i;
-		PortStat<=PortStat_i;
-		EquFlag<=EquFlag_i;
-		--IsMain1<=IsMain_i;
-		if ismain_i='1' then
-			IsMain1<='1';
-			
-		else
-			IsMain1<=IsMain1;
-		end if;
-		if stInit2=DecodeData then 
-			MyPort<=Cmdreceived(2)(3 downto 0);
-		end if;
-		
-		if stInit2=StoreRank and ExecTime_Out='1' then
-			MyRank<=MyPort;
-		elsif stInit2=StoreRank then
-			MyRank<=DataReceived(2)(3 downto 0);
-		elsif stInit2=SetMainFlag then
-		  MyRank<=MyPort;
-		end if;
-		Ready<=Rdy;
-		snd_start<=snd_start_i;
-		SpawnNbReq_q<=SpawnNbReq;
-		SpawnReq_Q<=SpawnReq;
-		SpawnCmd0_Q<=SpawnCmd0;
-		SpawnCmd1_Q<=SpawnCmd1;
-		SpawnCmd2_Q<=SpawnCmd2;
-		Spawn_grp_q<=Spawn_grp;
-		PeerRTS<=PeerRTS_i;
-		PortNum<=PortNum_i;
-		Spawn_done<=Spawn_done_i;
-		HCL_init<=Hcl_init_i;
-		PeerStat<=PeerStat_i;
-		DataLen<=DataLen_i;
-		MainPort<=MainPort_i;
-		Nextr<=NextR_i;
-		NocMax<=NoCMax_i;
-		PeerPort<=PeerPort_i;
-		grp_id<=grp_id_i;
-		for i in 0 to 3 loop
-			data_to_send(i)<=data_to_send_i(i);
-		end loop;
-	end if;
-end process;
-
-AppSize<=AppSize1;
-
-  Init2_DECODE: process (stinit2,n, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, 
-  SpawnOn,Ram_Next_Address,PeerRTS,PortSTAT,dma_rd,dma_wr,Send_rdy,I_Send_rdy,rd_ok,wr_ok,Instruction,
-  MainPort,PeerStat,SpawnCmd0,SpawnCmd1,SpawnCmd2,SpawnInit,BCast_rdy)
-   variable nextadr : natural :=0;--to_integer(unsigned(Ram_Next_Address));
-	variable nport : natural range 0 to 15:=0;
-	begin
-      for i in 0 to 3 loop
-			data_to_send_i(i)<=data_to_send(i);
-		end loop;
-		PortNum_i<=PortNum;
-		PortNumFlag_i<=PortNumFlag;
-		PortID<=MyPort;
-		PeerPort_i<=PeerPort;
-		NocMax_i<=NoCMax;
-		NextRank_i<=NextRank;
-		MainPort_i<=MainPort;
-		PeerStat_i<=PeerStat;
-		EquFlag_i<=EquFlag;
-		RankAsked_i<=RankAsked;
-		NextR_i<=NextR;
-		Ram_Next_Address_i<=Ram_Next_Address;
-		Ram_address<=(others=>'1');
-		Ram_data_in<=(others=>'1');
-		dma_rd_request<='0';
-		dma_wr_request<='0';
-		Initialized_i<='0';
-		rdy<='0';
-		ram_rd<='0';
-		ram_wr<='0';
-		I_Send_ack<='0';
-		IsMain_i<='0';
-		send_ack<='0';
-		DataLen_i<=0;
-      Case stInit2 is
-		When Init =>
-			RTS_cmd<='0';
-			--RTS_dat<='0';
-			RTS_I<='0';
-			BCast<='0';
-			Result_En<='0';
-			Initialized_i<='0';
-			CM_Ack <='0';
-			CTR<='0' ;
-			DS_ACK<='0';
-			Send_Ack<='0';
-			ram_wr<='0';
-			rdy<='1';--le module est disponible
-			ResultOut<=(others=>'0');
-			if PortNumFlag='1'  and IsMain1='1' then
-				PortNum_i<=Instruction(3 downto 0);
-			else
-				PortNum_i<=(others=>'-');
-			end if;
-			EquFlag_i<='0';
-			RankAsked_i<='0';
-			dma_wr_request<='0';
-			dma_rd_request<='0';
-		When GetPortNum =>
-			RTS_cmd<='1';
-			RTS_I<='0';
-			
-			Result_En<='0';
-			Initialized_i<='0';
-			BCast<='0';   --réalise un envoie non collectif
-			CM_Ack<='0';   -- les données sont maintenant attendues
-			CTR<='0' ;
-			data_to_send_i(0)<=X"0" & GETPORTID;
-			DS_ACK<='0';
-			Send_Ack<='0';
-			ram_wr<='0';
-			rdy<='0';
-			IsMain_i<='0';
-			ResultOut<=(others=>'0');
-			PortNum_i<=(others=>'-');
-			RankAsked_i<='0';
-			dma_wr_request<='0';
-		When DecodeData =>
-			EquFlag_i<=(All_zeros(Cmdreceived(2)(3 downto 0)));
-			RTS_cmd<='0';
-			RTS_I<='0';
-			BCast<='0';
-			
-			Result_En<='0';
-			
-			CM_Ack <='1'; --les données ont été reçues
-			--MyPort<=Cmdreceived(2)(3 downto 0);
-			PortNum_i<=Cmdreceived(2)(3 downto 0); --récupère les valeurs de port
-			PeerPort_i<=To_integer(unsigned(Cmdreceived(2)(3 downto 0)));
-			NocMax_i<=Cmdreceived(2)(7 downto 4);  -- et la taille du réseau
-			PortNumFlag_i<='1';  -- le numéro du port est maintenant connu
-			CTR<='0' ;
-			DS_ACK<='0';
-			Send_Ack<='0';
-			ram_wr<='0';
-			rdy<='0';
-			RankAsked_i<='0';
-			ResultOut<=(others=>'0');
-			dma_wr_request<='0';
-		When IsPortZero => --Ce port est-il le n° 0 du NoC ?
-			BCast<='0';
-			Result_En<='0';
-			RTS_cmd<='0';
-			RTS_I<='0';
-			NextRank_i<="0001"; -- le prochain rang à affecter sera le n° 1
-			nextr_i<=1;
-			IsMain_i<=EquFlag;
-			--MyRank<="0000";
-			MainPort_i<="0000";
-			--MainAdr<="0000";   -- le port 0 est le main Lib par défaut;
-			CTR<='0' ;
-			DS_ACK<='0';
-			ram_wr<='0';
-						rdy<='0';
-			RankAsked_i<='0';
-			ResultOut<=(others=>'0');
-			dma_wr_request<='0';
-		When SeekMain1 =>    -- recherche de la lib main
-				RTS_cmd<='0';
-				--RTS_DAT<='1';
-				RTS_I<='1';
-				CTR<='1' ; -- prêt à recevoir les données Clear To Receive
-				DS_ACK<='0'; --les données sont attendus
-				Send_Ack<=BCast_rdy;
-				I_Send_Ack<=BCAst_rdy;
-				data_to_send_i(0)<=MPI_INIT & MyPort ;
-				data_to_send_i(1)<="00000100"; -- la longueur du packet =4
-				data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse
-				data_to_send_i(3)<=INIT_SEEKMAIN & MyPort ;
-				DataLen_i<=4;
-				BCast<='1';
-				
-				Result_En<='0';
-				Initialized_i<='0';
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When SeekMain2 =>    -- recherche de la lib main
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='1' ; -- prêt à recevoir les données Clear To Receive
-				DS_ACK<= DS_RDY; --les données sont acquittées aussitôt reçues
-				Send_Ack<=BCast_rdy;
---				data_to_send_i(0)<=INIT_SEEKMAIN & MyPort ;
---				data_to_send_i(1)<="00000011"; -- la longueur du packet =3
---				data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse
---				DataLen<=3;
-				BCast<='0';				
-				Result_En<='0';
-				Initialized_i<='0';
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				EquFlag_i<='0';
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When StoreMain =>     -- la Main Lib est une autre
-				BCAST<='0';
-				Result_En<='0';
-				IsMain_i<='0';
-				Initialized_i<='0';
-				DS_ACK<=DS_RDY;
-				Send_Ack<='0';
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<=not(MainResp);  -- essayer de recevoir tant que le main n'a pas répondu
-				ram_wr<='1';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				RankAsked_i<='0';
-				EquFlag_i<='0';
-				MainPort_i<=DataReceived(0)(3 downto 0);
-				ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16));
-				ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0);  --MainPort & MyRank
-				dma_wr_request<= '0';  ---pas très sûr
-		
-		When AskPeerStat =>    -- Interroge les données d'initialisation
-				RTS_cmd<='0';
-				if n=0 then
-				--RTS_DAT<='0'; --on peut envoyer les données
-				RTS_I<='1';
-				else
-				  --RTS_DAT<='0'; --on désactive l'envoie des données
-				  RTS_I<='0';
-				 end if;
-				CTR<='0' ; -- prêt à recevoir les données Clear To Receive
-				DS_ACK<='0'; --les données sont attendus
-				I_Send_Ack<=I_Send_rdy;
-				Send_Ack<=Send_rdy;
-				data_to_send_i(0)<=MPI_INIT & MainPort ;
-				data_to_send_i(1)<="00000100"; -- la longueur du packet =4
-				data_to_send_i(2)<="0000" & MyPort; --indique sa propre adresse
-				data_to_send_i(3)<=INIT_STAT & MyPort ;
-				DataLen_i<=4;
-				BCast<='0';
-				Result_En<='0';
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				EquFlag_i<='0';
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When SetMainFlag =>   -- Cette Lib est la Main Lib 
-				if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then 
-					RankAsked_i<='1';
-				else 
-					RankAsked_i<='0';
-				end if;
-				RTS_cmd<='0';
-				Initialized_i<='0';
-		      RTS_I<='0';
-				BCast<='0';
-				IsMain_i<='1';
-				Result_En<='0';
-				--MyRank<="0000";
-				MainPort_i<="0000";
-				PeerStat_i(0)<='1'; --la main lib est initialisée
-				CTR<='1';
-				DS_ACK<='0';
-				ram_wr<='1';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				EquFlag_i<='0';
-				ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16));
-				ram_data_in<=(others =>'0');  -- le port vaut 0 et la mainlib est aussi à 0
-				dma_wr_request<='1';
-		When ReadNoc =>
-				if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then
-					RankAsked_i<='1' ;
-				else 
-					RankAsked_i<='0';
-				end if;
-				ram_wr<='0';  -- pas d'écriture en RAM
-				rdy<='0';
-				BCast<='0';
-				DS_ACK<='0';
-				--IsMain<='0';
-				Result_En<='0';			
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='1';
-				ResultOut<=(others=>'0');
-				PortNum_i<=DataReceived(2)(3 downto 0); -- le port qui demande un rang;
-				PeerPort_i<= To_integer(unsigned(DataReceived(2)(3 downto 0)));
-				--EquFlag<='1';
-				dma_wr_request<='0';
-		When GetMainReq  =>
-				--RankAsked_i<='1';
-				ram_wr<='0';  -- pas
-				BCast<='0';
-				DS_ACK<='1';				
-				Result_En<='0';				
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='1';
-				ResultOut<=(others=>'0');
-				PortNum_i<=DataReceived(0)(3 downto 0); -- le port qui demande un rang;
-				EquFlag_i<='1';
-				dma_wr_request<='0';
-		When GetPeerStat  =>
-				--RankAsked_i<='1';
-				ram_wr<='0';  -- pas
-				BCast<='0';
-				DS_ACK<=DS_RDY;
-				Result_En<='0';
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<=not MainResp;
-				ResultOut<=(others=>'0');
-				PortNum_i<=DataReceived(0)(3 downto 0); --adresse du Main Port
-				PeerStat_i(7 downto 0)<=DataReceived(2); -- état des initialisations
-				EquFlag_i<='0';
-				dma_wr_request<=dma_wr;
-				ram_wr<=wr_ok;
-				rdy<='0';
-				ram_rd<=rd_ok;
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_Init_Adr+2,ADRLEN)); --incr_vec(Ram_Next_Address,'1');
-				ram_address<=Ram_Next_Address;  -- 
-				ram_data_in<=DataReceived(2); --enregistrer les ports actifs
-				
-		When NewRank =>
-				nport:=to_integer(Unsigned(PortNum)); --port ayant sollicité le rang
-				nextr_i<=to_integer(unsigned(nextrank));
-				if PeerStat(nport)='0' then -- si le rang n'a pas encore été affecté à ce port
-				nextrank_i<=incr_vec(nextrank,'1');
-				RankToPort(to_integer(unsigned(nextrank)))<="0000" & PortNum;
-				NextAdr:=NextAdr+1;
-				end if;
-				data_to_send_i(0)<=MPI_INIT & PortNum ;
-				data_to_send_i(1)<="00000100";
-				data_to_send_i(2)<="0000" & NextRank;  --ici c'est la valeur avant incrémentation !
-				data_to_send_i(3)<=INIT_SETRANK & PortNum ;
-				PeerStat_i(nport)<='1'; -- mise à jour du status
-				DataLen_i<=4;
-				BCast<='0';
-				DS_ACK<='0';
-				Result_En<='0';
-				EquFlag_i<='1';
-				RTS_cmd<='0';
-				RTS_I<='1';
-				CTR<='0' ;
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='1';
-				ResultOut<=(others=>'0');
-				dma_wr_request<='0';
-				
-		When SendRank =>
-				BCast<='0';
-				Result_En<='0';
-				EquFlag_i<='1';
-
-				RTS_I<='1';
-				DataLen_i<=4;
-				RTS_cmd<='0';
-				DS_ACK<='0';
-				Send_Ack<='0';
-				CTR<='0' ;
-				ram_wr<='0';
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16));
-				ResultOut<=(others=>'0');
-				RankAsked_i<='1';
-				dma_wr_request<='0';
-		When RegRank =>
-					RankAsked_i<='0';
-
-				CTR<='1' ; -- continuer à recevoir les données du NoC
-				Result_En<='0';
-				RTS_cmd<='0';
-				DS_ACK<='0';
-				Send_Ack<=Send_RDY;
-				I_Send_ack<=i_send_rdy;
-				Rts_I<='0';
-				BCast<='0';
-				EquFlag_i<='1';
-				ram_wr<='1';
-				
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); --incr_vec(Ram_Next_Address,'1');
-				ram_address<=Ram_Next_Address;  -- le rang qui a été envoyé;
-				-- "le motif 0001 indique juste que le port est bien activé
-				ram_data_in<="0001" & PortNum; --enregistrer le port qui a fait la demande en RAM
-				ResultOut<=(others=>'0');
-				dma_wr_request<='1';
-		When SendPeerStat =>
-				BCast<='0';
-				Result_En<='0';
-				EquFlag_i<='0';
-				RTS_I<=PeerRTS;
-				RTS_cmd<='0';
-				DS_ACK<='0';
-				data_to_send_i(0)<=MPI_INIT & PortStat ;
-				data_to_send_i(1)<="00000100";
-				data_to_send_i(2)<=PeerStat(7 downto 0);
-				data_to_send_i(3)<=INIT_REGISTER & MyPort ;
-				Send_Ack<=Send_Rdy;
-				I_Send_Ack<=I_Send_Rdy;
-				CTR<='0' ;
-				ram_wr<='0';
-				rdy<='0';
-				ResultOut<=(others=>'0');
-				RankAsked_i<='1';
-				dma_wr_request<='0';
-				Initialized_i<='1';
-		When StoreRank => --le processus qui écoute le Port et qui 
-								--stoke les adresses des autres bib va gérer le stockage du rang
-				BCAST<='0';
-				DS_ACK<='1';
-				Send_Ack<='0';
-				RTS_cmd<='0';
-				EquFlag_i<='0';
-				RTS_I<='0';
-				CTR<='0';
-				Result_En<='0';
-				
-				if ExecTime_out='1' then
-				MainPort_i<="0000";
-				--MyRank<=MyPort;
-				initialized_i<='0';
-				else
-				MainPort_i<=DataReceived(0)(3 downto 0);
-				--MyRank<=DataReceived(2)(3 downto 0);
-				Initialized_i<='1'; 
-				end if;
-				ram_wr<='1';
-				--ram_address<=DataReceived(2);  -- le rang qui a été envoyé;
-				ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16));
-				ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0);  --MainPort & MyRank
-				ResultOut<=(others=>'0');
-				RankAsked_i<='0';
-				dma_wr_request<='1';
-		When SendApp =>  --ajouter du code pour recevoir l'adr du reg status
-				Initialized_i<='1';
-				ResultOut<="00000001"; -- Init Ok
-				Result_En<='1';
-				PortId<=MyPort;
-				BCAST<='0';
-				DS_ACK<='1';
-				Send_Ack<='0';
-				RTS_cmd<='0';
-				RTS_I<='0';
-				CTR<='0';
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='0';
-				dma_wr_request<='0';
-		When SpawnApp =>
-				RTS_cmd<='0';
-				RTS_I<='0';
-				Result_En<='0';
-				DS_ACK<=DS_RDY;
-				BCAST<='0';
-				CTR<='0';  --cette mise à 1 permet de ctrler la fin de réception
-				rdy<='0';
-				ram_wr<=wr_ok;
-				ram_rd<=rd_ok;
-				Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_BASE_ADR,ADRLEN)); --incr_vec(Ram_Next_Address,'1');
-				ram_address<=Ram_Next_Address;  -- le rang qui a été envoyé;
-				-- "le motif 0001 indique juste que le port est bien activé
-				ram_data_in<=DataToRam; --enregistrer le port qui a fait la demande en RAM
-				dma_rd_request <= dma_rd;
-				dma_wr_request <=dma_wr;
-				RankAsked_i<='0';
-				if n>=3 then
-					ResultOut<=("00000010");--spawn completed
-				else
-					ResultOut<=("00000000");--spawn message received 
-				end if;
-				
-		When SpawnLoad =>
-		    RTS_cmd<='0';
-				--RTS_DAT<='1'; --à tester
-				RTS_I<=PeerRTS; -- pour le timing
-				Result_En<='0';
-				DS_ACK<='0';
-				BCAST<='0';
-				CTR<='0';
-				rdy<='0';
-				ram_wr<=wr_ok;
-				ram_rd<=rd_ok;
-		      data_to_send_i(0)<=SpawnCmd0;
-          data_to_send_i(1)<="00000100";
-          data_to_send_i(2)<=SpawnCmd1;
-          data_to_send_i(3)<=SpawnCmd2; -- SPAWN_LOAD & MyPort ;
-          Send_Ack<=Send_Rdy;
-    				I_Send_Ack<=I_Send_rdy;
-          RankAsked_i<='0';
-				if SpawnInit='1' then
-					ResultOut<=("10000000"); --spawn completed
-				else
-					ResultOut<=("01000000");--spawn in progress
-				end if;
-		When ErrSpawn =>
-				RTS_cmd<='0';
-				RTS_I<='0';
-				Result_En<='1';
-				DS_ACK<='0';
-				Send_Ack<='0';
-				BCAST<='0';
-				CTR<='0';
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='0';
-				
-				ResultOut<=(others=>'0');
-				dma_wr_request<='0';
-				dma_rd_request<='0';
-		When EndInit =>
-				RTS_cmd<='0';
-				RTS_I<='0';				
-				Result_En<='0';
-				DS_ACK<='0';
-				Send_Ack<='0';
-				BCAST<='0';
-				CTR<='0';
-				ram_wr<='0';
-				rdy<='0';
-				RankAsked_i<='0';
-				ResultOut<=(others=>'0');
-				dma_wr_request<='0';
-				dma_rd_request<='0';
-		end case;
-   end process;
-	
-result_proc:process (ISMain_i,Initialized_i,stInit2,reset)
-begin
-if reset='1' then
-	--IsMain1<='0';
-	Initialized<='0';
-	HCL_Init_i<='0';
-	
-Else
-	HCL_init_i<=HCl_init;
-	Initialized<=Hcl_init;
---	if ismain_i='1' then
---		IsMain1<='1';
---	end if;
-
-	if Initialized_i='1' and stInit2=EndInit then
-		Initialized<='1';
-		HCL_Init_i<='1';
-	elsif stInit2=SendApp then
-	  HCL_Init_i<='1';
-	end if;
-end if;
-end process result_proc;
- --================
- --Traitement du Spawn
- --===================
- 
- --==================
-   NEXT_STInit2_DECODE: process (stInit2,AppReq,Instruction_en, AppAck,PortNumFlag,EquFlag,MainResp,StatAsked,RankAsked,RankSent,CM_RDY, CmdReceived, 
-	BCast_Rdy, DS_RDY, DataReceived,Ht_Start,vPeerStat, Send_RDY,	I_Send_RDY,TimeOut,Dma_rd_grant,Dma_wr_grant,cpt,n,clk_cyl,IsMain1,SpawnOn,
-	Instruction,Hcl_Init,Spawn_done,mainport,PeerStat,PeerRTS,Rec_Data,SpawnInit,grp_id,SpawnNbReq,Ram_data_out,Spawn_grp,MyPort)
-   variable InitTimeOut :natural:=0;
-	variable LastPort,Ht_hole : std_logic:='0';
-	variable i,nbSpawn,htloc,Ht_Id : natural range 0 to 15:=0;
-	--variable vPeerStat : std_logic_vector(15 downto 0);
-   variable vPortStat,nulvect : std_logic_vector(3 downto 0):="0000";	
-	variable tempval : std_logic_vector(Word-1 downto 0);
-  begin
-      --declare default state for next_state to avoid latches
-      next_stInit2 <= stInit2;  --default is to stay in current state
-      --insert statements to decode next_state
-      --below is a simple example
-		vPeerStat_i<=vPeerStat;
-		SpawnNbReq<=SpawnNbReq_q;
-		StatAsked_i<=StatAsked;
-		MainResp_i<=MainResp;
-		AppSize_i<=AppSize1;
-		PortStat_i<=PortStat;
-		grp_id_i<=grp_id;
-		PeerRTS_i<=PeerRTS;
-		--PortNumFlag_i<=PortNumFlag;
-		SpawnReq<=SpawnReq_q;
-		Spawn_done_i<=Spawn_done;
-		Ht_Start_i<=Ht_Start;
-		SpawnCmd0<=SpawnCmd0_Q;
-		SpawnCmd1<=SpawnCmd1_Q;
-		SpawnCmd2<=SpawnCmd2_Q;
-		Timeout_i<=Timeout;
-		clk_cyl_i<=clk_cyl;
-		n_i<=n;
-		Cpt_peer<=cpt;
-		DataToRam<=(others=>'0');--A revoir
-		dma_rd<='0';
-		dma_wr<='0';
-		rd_ok<='0';
-		wr_ok<='0';
-		for i in 0 to 3 loop
-		Spawn_grp(i)<=Spawn_grp_q(i);
-		end loop;
-      case (stInit2) is
-         
-			
-		When Init =>If Instruction_en='1' and AppReq='1'  then
-					 If PortNumFlag='1'  and IsMain1='1' then
-						if instruction(7 downto 4)=INIT_SEEKMAIN and (instruction(3 downto 0)/=MyRank) then 
-							Next_stInit2 <=NewRank;--affecter un rang au demandeur.
-						elsif instruction(7 downto 4)=INIT_STAT then
-						  StatASked_i<='1';
-							Next_stInit2 <=SendPeerStat; --envoyer des stat au demandeur
-						elsif instruction(7 downto 4)=SPAWN_LOAD then
-							SpawnInit<='0'; -- indique le debut du Spawn 
-							Next_stInit2 <=SpawnLoad; 
-						elsif instruction(7 downto 4)=INIT_SPAWN then
-							SpawnInit<='1'; -- indique la fin du 
-							Next_stInit2 <=SpawnLoad; --dans ce cas il s'agit de terminer le spawn
-						else --ignorer ce message
-							Next_stInit2 <=SendApp;
-						end if;
-					 elsif HCL_Init='1' and IsMain1='0' then 
-						Next_stInit2 <=SendApp; --ignorer ce message simplement
-					else 
-						Next_stInit2 <=GetPortNum; -- initialiser la bibliothèque normalement
-					end if;
-					TimeOut_i<=0;PeerRTS_i<='0';
-					
-				 elsif SpawnOn='1' and Spawn_done='0' then 
-					Next_stInit2 <=SpawnApp;
-					TimeOut_i<=0;
-				 end if;
-				cpt_peer<=0;LastPort:='0';n_i<=0;
-		When GetPortNum =>  -- récupérer le numéro du port
-												
-						if CM_RDY='1' then 
-							Next_stInit2 <=DecodeData;
-						end if;
-						
-		When DecodeData =>  -- cet état permet de lire les données reçues du port
-							--if CM_RDY='1' then 
-								if ((Cmdreceived(2)(3 downto 0) or nulvect)=nulvect) then -- teste si le n° du port est zero
-								  --EquFlag<='1';
-								 else
-								  --EquFlag<='0';
-								end if;
-								
-								Next_stInit2 <=IsPortZero;
-							--end if;
-		When IsPortZero => 
-						if PortNumFlag='1' then 
-						
-						End if;
-						if EquFlag='0'  then  --tester le numéro de port obtenu
-							Next_stInit2 <=SeekMain1; -- chercher le numéro de port sur le réseau
-						else 
-							Next_stInit2<=SetMainFlag; -- enregistrer le numéro de port
-						End If;
-						TimeOut_i<=0;
-		
-		When SeekMain1 =>If BCast_RDY='1' then  -- si tous les envois ont été postés
-									Next_stInit2<=SeekMain2;
-							End if;				
-		When SeekMain2 =>  
-							If DS_RDY='1' then  -- Si un jeu de données a été reçu
-										if (Datareceived(3)(7 downto 4) = INIT_SETRANK) then 
-												MainResp_i<='1';
-												Next_stInit2 <=StoreMain; -- de la librairie pricipale
-									 else
-												MainResp_i<='0';
-												Timeout_i<=0;
-									 end if;	
-										
-							elsif (ExecTime_Out='1') then 
-									
-												-- le Noc ne répond pas
-												-- affecter un numéro en raport avec le port
-										Next_stInit2 <=SeekMain2;
-							elsif TimeOut=800 then
-												--essayer de redemander l'initialisation
-									assert true report "Ex4:seekmain ->redemander l'initialisation"
-                      severity failure;
-									Timeout_i<=0;			
-									Next_stInit2 <=SeekMain1;
-							else
-										Timeout_i<=TimeOut+1;
-							End if;
-							
-							 
-							 
-		When StoreMain =>
-				if DataReceived(3)(7 downto 4)= INIT_SETRANK then
-				-- enregistrer le Main Adresse et les adresses des autres processus
-				-- dans la variable prévue à cet effet
-				Next_stInit2 <=StoreRank;
-				
-				elsif Datareceived(3)(7 downto 4) = INIT_SEEKMAIN then 
-				-- ignorer ce message
-				Next_stInit2 <=StoreMain; --essayer de recevoir le rang
-				
-				
-				end if;
-					
-		When StoreRank =>
-					--il faut prévoir du code pour s'assurer que la RAM a bien enregistrer
-					-- la donnée ...
-					if dma_wr_grant = '1' then 
-						if clk_cyl=2 then --prévoir deux cycle d'horloge pour lire en RAM
-							Next_stInit2 <=AskPeerStat;
-							TimeOut_i<=0;
-							clk_cyl_i<=0;
-						else 
-							clk_cyl_i<=clk_cyl+1;
-						end if;
-					else
-							Next_stInit2 <=StoreRank;
-							TimeOut_i<=0;
-							clk_cyl_i<=0;
-					end if;
-		When AskPeerStat =>if n=0 then 
-		        If I_SEND_RDY='1' then  -- si tous les envois ont été postés
-									n_i<=1;
-									StatAsked_i<='0';
-							End if;		
-						elsif n=1 then 
-						If I_SEND_RDY='0' then  -- si tous les envois ont été postés
-									Next_stInit2<=GetPeerStat;
-									StatAsked_i<='1';
-									MainResp_i<='0';
-							   n_i<=0;
-							End if;		
-						end if;		
-		When GetPeerStat =>  
-							if n=0 then
-							If DS_RDY='1' then  -- Si un jeu de données a été reçu
-									 if (Datareceived(3) = INIT_REGISTER & MainPort ) then 
-												MainResp_i<='1';
-												n_i<=n+1;
-												
-									 else
-												MainResp_i<='0';
-												Timeout_i<=0;
-												n_i<=n;
-									 end if;	
-										
-							elsif TimeOut=1800 then
-												--essayer de redemander les statistiques
-									assert true report "Ex4:GetPeerStat timeout  ->Les statistiques n'ont pas été reçu"
-									severity failure;
-									Timeout_i<=0;	
-									If StatAsked='1' then
-									Next_stInit2 <=AskPeerStat; -- ceci n'est pas sûr
-									else
-									Next_stInit2 <=GetPeerStat;
-									end if;
-							else
-										Timeout_i<=TimeOut+1;
-							End if;  
-							elsif n=1 then  --écrire le résultat de l'initialisation
-							dma_wr<='1';
-							if dma_wr_grant='1' then
-								n_i<=n+1;
-								wr_ok<='1';
-							end if;
-							elsif n=2 then
-								n_i<=n+1;   --écriture dans la RAM
-							elsif n=3 then
-								n_i<=0;
-								dma_wr<='0';
-								Next_stInit2 <=SendApp; -- de la librairie pricipale
-							end if;
-		When SetMainFlag =>
-				if dma_wr_grant='1' then   
-						TimeOut_i<=0;
-						Next_stInit2 <=ReadNoc;
-					elsif Timeout=800 then
-					  	assert true report "Ex4:SetMainFlag timeout  ->La mémoire n'est pas dispo dma_wr_grant=0"
-					  	severity failure;
-						Next_stInit2 <=SendApp;
-					else
-						TimeOut_i<=TimeOut+1;
---					end if; -- il est envisagée de terminer le programme à ce point
-				end if;
-		when ReadNoc => if DS_RDY='1' then
-									if (Datareceived(3)(7 downto 4) = INIT_STAT) then
-											StatAsked_i<='1' ;
-											Next_stInit2 <=SendPeerStat;
-											LastPort:='0';
-									else 
-										StatAsked_i<='0';
-										Next_stInit2 <=GetMainReq;
-									end if;
-									
-									Timeout_i<=0;
-								elsif Timeout=400 then
-									assert true report "Ex4:ReadNoc timeout pas de données lues sur le NoC après 200 cycles"	
-									severity failure;							  
-									Timeout_i<=0;
-									--if StatAsked = '1' then
-										--Next_stInit2 <=ErrSpawn; --il y a eu une erreur
-										Next_stInit2 <=SendApp;
-								--	else
-									--	Next_stInit2 <=SendPeerStat;
-								--	end if;
-								else
-									TimeOut_i<=TimeOut+1;
-								end if; 
-				
-		When GetMainReq => if RankAsked='1' and PeerStat(PeerPort)='0' then
-									Next_stInit2 <=NewRank; -- un nouveau rang est demandé
-								else
-									Next_stInit2 <=ReadNoC; -- sinon essayer encore de lire un jeu de données.
-								end if;
-		When NewRank =>
-				Next_stInit2 <=SendRank;
-		When SendRank =>
-					if I_Send_RDY='1' then  --RankSent
-						Next_stInit2 <=RegRank;
-						RankSent_i<='1';  -- le rang a été envoyé
-						TimeOut_i<=0;   -- prépare le traitement de la prochaine requête
-												-- d'attente des ports
-				  elsif Timeout=800 then
-				    assert true report "Impossible d'envoyer le rang"
-				    severity failure;
-				    timeout_i<=0;
-				  else 
-				    TimeOut_i<=TimeOut+1; 
-					end if;
-		When RegRank =>
-					--il faut prévoir du code pour s'assurer que la RAM a bien enregistrer
-					-- la donnée ...
-					if dma_wr_grant = '1' then 
---							if DS_RDY='1' then
-								RankSent_i<='0';
-								if DS_RDY='0' then
-								 
-									Next_stInit2 <=ReadNoc;
-								end if;
-							elsif Timeout=800 then
-								Next_stInit2 <=SendApp;
-								assert true report "Ex4:RegRank Timeout dma_wr_grant=0 "
-				    severity failure;
-							else
-								TimeOut_i<=TimeOut+1;
---							end if; -- il est envisagée
-					end if;
-					--calcul de la taille de l'appli
-					HtLoc:=0;
-					for i in 0 to 7 loop
-						if peerStat(i)='1' then --trouve le prochai rang libre
-							HtLoc:=HtLoc+1;
-						end if;
-					end loop;
-					AppSize_i<=std_logic_vector(to_unsigned(HtLoc,4));
-		
-		When SendPeerStat =>
-					
-					if cpt<=unsigned(NoCMax)and LastPort='0' then
-						if peerRts='0' then -- pas encore envoyer les données alors les préparer
-								if StatAsked='1' then 
-									
-									PortStat_i<=PortNum;
-									vPortStat:=std_logic_vector(to_unsigned(PeerPort,4));
-								else
-									PortStat_i<=std_logic_vector(to_unsigned(cpt,4));--Port à contacter
-									vPortStat:=std_logic_vector(to_unsigned(cpt,4));
-								end if;
-								
-								if StatAsked='1' then 
-									LastPort:='1';  -- on traite u seul port celui qui en a fait la demande
-									if PeerStat(PeerPort)='1' then
-									PeerRts_i<='1';
-									end if;
-								else
-									if (PeerStat(cpt)='1') and not(vPortStat=MyPort) then
-										PeerRts_i<='1';
-									end if;
-									if cpt<unsigned(NoCMax) then 
-										cpt_peer<=cpt+1;
-										LastPort:='0';
-									else
-										if LastPort='0' then
-												LastPort:='1';
-												cpt_peer<=cpt+1;--ceci permet de déclencher l'évaluation du process
-										end if;
-									end if;
-								end if;
-								TimeOut_i<=0;
-					else
-							if I_Send_RDY='1' then  
-										
-										RankSent_i<='1';  	-- les stat ont été envoyé
-										TimeOut_i<=0;  	 	-- prépare le traitement de la prochaine requête
-										PeerRts_i<='0';										-- d'attente des ports
-							  elsif TimeOut=800 then
-									Next_stInit2 <=EndInit ;-- impossible d'envoyer sur le NoC
-							   assert true report "Ex4:SendPeerStat Timeout -> Impossible d'envoyer sur le NoC"
-				        severity failure;
-							  else
-									TimeOut_i<=TimeOut+1; 
-							end if;
-					end if;
-					elsif PeerRTS='1' then -- le dernier port est il activé ?
-						if I_Send_RDY='1' then  
-								RankSent_i<='1';  	-- les stat ont été envoyé
-										TimeOut_i<=0;  	 	-- prépare le traitement de la prochaine requête
-										PeerRts_i<='0';
-							if statAsked='1' then 
-							 -- Next_stInit2<=ReadNoc;
-							
-							Next_stInit2<=SendApp; --terminer l'application
-						  end if;
-						
-						elsif TimeOut=100 then
-							Next_stInit2 <=EndInit;
-							assert true report "Ex4:SendPeerStat Timeout -> Impossible d'envoyer sur le NoC"
-				        severity failure;
-						else 
-							TimeOut_i<=TimeOut+1; 
-						end if;
-					else
-						Next_stInit2<=SendApp;
-					end if;
-		When SendApp =>  -- envoyer au programme un signal 
-					-- et attendre un acquittement et l'adresse de base
-					If AppAck='1' then
-						Next_stInit2 <=EndInit;
-					end if;
-		
-		When SpawnLoad =>
-		
-				if n=0 then
-					ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0)));
-					vPeerStat_i<=PeerStat; --récupérer la situation actuelle des tâches créées
-					if IsMain1='1' and SpawnInit='0' then 
-					 SpawnNbReq<=to_integer(unsigned(Instruction(3 downto 0))); -- sauver le nombre de HT à créer
- 
-					n_i<=1;
-					SpawnReq(ht_id)<='1'; --Note l'id de HT qui a appelé le Spawn
-					elsif IsMain1='1' and SpawnInit='1'  then -- il faut envoyer les acquittements
-					ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0)));
-					Spawn_grp(grp_id)(ht_id)<='1'; --noter le port du Fils Spawné dans ce groupe
-					Ht_start_i<=0; --compte le nombre de tâches chargées
-							n_i<=6;
-					
-					else 
-					   if SpawnOn='1' then --if IsMain_i='0' then  -- il faut juste charger puis activer la tâche
-					     n_i<=7;
-					    end if;
-					    assert true
-					   Report "SpawnLoad : Cas non prévu !"
-					  severity failure;
-					end if;
-				elsif n=1 then
-				if PeerStat=SpawnReq then --tous les Hts ont appelés Spawn ?
-				ht_hole:='0';		
-	L1:			for i in 0 to 15 loop
-						if vPeerStat(i)='0' then
-							SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à activer
-							SpawnCmd0<=MPI_SPAWN & std_logic_vector(to_unsigned(i,4));
-							vPeerStat_i(i)<='1';
-							Ht_Start_i<=Ht_Start+1;
-							Ht_Hole:='1'; -- une place a été trouvé
-						else
-							Ht_hole:='0'; -- pas de place trouvé
-						end if;
-						exit L1 when ht_hole='1';
-					end loop L1;
-					if Ht_hole='0' then -- toutes les tâches n'ont pas été créés
-						-- aller à la fin ! en signalant une erreur!
-						SpawnCMd2<=Spawn_Err & "0001"; --erreur pas assez de ports sur le NoC
-						n_i<=9;
-					else
-						n_i<=n+1;
-						SpawnCmd1<=PeerStat(7 downto 0);
-						SpawnCmd2<=SPAWN_START & MyPort;
-					end if;
-					else --Tous les Hts n'ont pas appelé Spawn encore
-					  Next_stInit2<=SendApp; --on termine normalement
-					  n_i<=0;
-					end if;
-				elsif n=2 then
-				PeerRTS_i<='1'; -- envoyer les données du Spawn
-				n_i<=n+1;
-				elsif n=3 then
-					if I_Send_RDy='1' then
-						n_i<=n+1;
-						PeerRts_i<='0';
-					end if;
-				elsif n=4 then
-					if SpawnInit='0' then
-					if Ht_Start>=SpawnNbReq then
-						n_i<=n+1;
-					else
-						n_i<=1; -- passer à la création du HT suivant
-					end if;
-					else
-						n_i<=7; -- passer au contact du HT suivant
-					end if;
-				elsif n=5 then
-								-- Aller à la fin le résultat du Spawn
-				
-				n_i<=10;
-				elsif n=6 then
-				  nbSpawn:=0;
-				  for i in 0 to 15 loop
-				      if Spawn_grp(grp_id)(i)='1' then
-				         nbSpawn:=nbSpawn+1;
-				       end if;
-				   end loop;
-				  if nbSpawn=SpawnNbReq then
-				  n_i<=n+1; --aller renvoyer les réponses
-				  else
-				    n_i<=10; --fin du Spawn
-				    
-				   end if;
-				elsif n=7 then
-				Ht_hole:='0';
-L2:			for i in 0 to 7 loop --for i in Ht_start to 7 loop
-						if i>=Ht_start then
-						if vPeerStat(i)='1' and Spawn_grp(grp_id)(i)='0' then  --on avertit les membres du groupe parent
-						  --mais pas ceux du groupe Fils !
-							SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à avertir
-							SpawnCmd0<=MPI_ACK & std_logic_vector(to_unsigned(i,4));
-							vPeerStat_i(i)<='0';
-							Ht_Start_i<=i+1; -- le prochain Ht à prévenir 
-							Ht_Hole:='1'; -- Une tâche doit être avertie
-						else
-							Ht_hole:='0'; -- 
-						end if;
-						end if;
-						exit L2 when ht_hole='1';
-					end loop L2;
-					n_i<=n+1;
-			elsif n=8 then
-				 if Ht_hole='1' then --
-						-- un HT existant à prévenir ! 
-						SpawnCmd1<=Spawn_grp(grp_id)(7 downto 0);
-						SpawnCMd2<=MPI_SPAWN & MyRank; -- fin du Spawn
-						n_i<=2; --envoyer la  donnée sur le réseau
-					elsif vpeerstat /=spawn_grp(grp_id) then --il ne reste plus de membres à prévenir ?
-              n_i<=7; --on est sorti mais ce n'est pas la fin
-
-					else -- fin du Spawn car tous ont été averti
-						n_i<=10;
-						SpawnNbReq<=0;
-						SpawnReq<=(others=>'0');
-						vPeerStat_i<=(others=>'0');
-						grp_id_i<=grp_id+1; --incrementer le compteur de groupes************
-					end if;
-				elsif n=9 then
-				  assert true report "error in Spawn command"
-				   severity failure;
-				elsif n=10 then
-				  n_i<=0;
-				  Next_stInit2<=SendApp;
-				 end if;
-		
-	When SpawnApp=>
-	  	--Mise à jour du bit 6 du registre status du COre.
-		if n>=0 and n <4 then     
-			
-			dma_wr<='1';  --demander un accès exclusif au bus
-			dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-		else
-			dma_wr<='0';										
-			dma_rd<='0';
-		end if;
-		
-		if n=0 then
-		  if DS_RDY='1' then ---
-		      if Datareceived(3)(7 downto 4)=SPAWN_START then
-		        n_i<=n+1;
-		       else
-		         Next_stInit2<=ErrSpawn;
-		         n_i<=0; --erreur instruction incorrecte
-		        end if;
-			   
-			   rd_ok<='1';
-			   wr_ok<='0';
-			end if;
-		elsif n=1 or n=2 then
-			if dma_rd_grant='1' then
-				n_i<=n+1;
-				tempval:=Ram_data_out;
-			end if;
-				rd_ok<='1';
-				wr_ok<='0';
-			 
-		elsif n=3 then
-				if dma_rd_grant='1' and dma_wr_grant='1' then
-					n_i<=n+1;
-					tempval:=Ram_data_out;
-					tempval(6):='1';  	
-							
-					dataToram<=tempval;
-					rd_ok<='0';
-					wr_ok<='1';
-				else
-					rd_ok<='1';
-					wr_ok<='0';
-				end if;
-		elsif n=4 then
-		if spawninit='0' then
-		  Spawn_done_i<='1';
-		end if;
-		rd_ok<='0';
-		wr_ok<='0';
-		n_i<=0;
-		Next_stInit2<=EndInit;
-		end if;
-			
-		When ErrSpawn =>
-		  assert true
-		  report "Ex4/stInit2/SpawnApp:Erreur lors de Spawn"
-		  severity failure;
-			Next_stInit2<=Init;
-		When EndInit=>
-		  
-			StatAsked_i<='0'; --reset de ces variables
-			Next_stInit2<=Init;
-      end case;      
-   end process;
-	
---================================================
---sauvegarde du rang et du main port à l'adresse de retour de la fonction Init
---==================================================
-
---====================================================
---envoie des données sur le port
---===================================================
-selector<=(Rcv_on,Cmd_on,Snd_on);
-
-process (selector,Rport_out_rd_en,cport_out_rd_en,sPort_in_wr_en ,cPort_in_wr_en,
-				tosend ,tosend4)
-begin
-   case selector is
-	
-      when "000" => port_in_data<=(others=>'-');
-						Port_in_wr_en<='0';
-						Port_out_rd_en<='0';
-      
-		when "001" => port_in_data<=tosend; --envoie de données
-						Port_in_wr_en<=sPort_in_wr_en ;
-						Port_out_rd_en<='0';
-      when "101" => port_in_data<=tosend; --envoie de données
-						Port_in_wr_en<=sPort_in_wr_en ;
-						Port_out_rd_en<=Rport_out_rd_en ;
-		when "010" | "110" | "011" | "111" => 
-						port_in_data<=tosend4; --envoie de commande GetPort
-						Port_in_wr_en<=cPort_in_wr_en;
-						Port_out_rd_en<=cport_out_rd_en;
-     
-	  when "100" => port_in_data<=(others=>'-'); -- réception de données
-						Port_in_wr_en<='0';
-						Port_out_rd_en<=Rport_out_rd_en ;
-      
-		when others => port_in_data<=(others=>'-');
-							Port_in_wr_en<='0';							
-							Port_out_rd_en<='0';
-   end case;
-end process;
- 
---==================================================	
-	
-	--===============================================================
-	--processus d'accès au réseau
-	--===============================================================
-
-
-
-
-
-	preceiv:process(clk,reset)
-	
-	variable origport,destport : natural range 0 to 15;
-	variable dcount,dlen ,rtimeout:natural range 0 to 1023;
-	variable ptype : std_logic_vector(3 downto 0);
-	variable bad_paquet :std_logic:='0';
-	begin
---				
-	
-	if reset='1' then
-		etrec<=r_wait;
-		destport:=1;
-		rtimeout:=0;
-		bad_paquet:='0';
-	else
-	if  rising_edge(clk) then 
-			case  etrec is
-			when r_wait =>
-				
-				rtimeout:=0;
-				bad_paquet:='0';	
-				--modifier le 01-08-pour gérer le Spawn
-			if Port_out_data_available='1' and Cmd_on='0' then 
-				ptype:=port_out_data(7 downto 4);
-				origport:=to_integer(unsigned(port_out_data(3 downto 0)));
-				
-				if ptype=MPI_SPAWN and not(portnumflag='1') then
-						etrec<=r_dlen; --identification de la signature d'en tête valide
-						Datareceived(0)<=Port_out_data; --stocker l'entête
-						bad_paquet:='0';
-						SpawnOn<='1'; --le spawn est actif
-				elsif Instruction_en='0' and CTR='0' and Hcl_init= '0' then
-				  --il faut éliminer ce paquet qui est inoportun !
-				  Bad_paquet:='1';
-				  etrec<=r_dlen; --il faut ignorer cette donnée et quitter
-					dcount:=1;
-				elsif CTR='1' then
-				if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN or ptype=INIT_REGISTER then 
-						etrec<=r_dlen; --identification de la signature d'en tête valide
-						Datareceived(0)<=Port_out_data; --stocker l'entête
-						bad_paquet:='0';
-				else
-					--une donnée non attendue est présente sur le port
-					etrec<=r_dlen; --il faut ignorer cette donnée et quitter
-					dcount:=1;
-					bad_paquet:='1';
-					Datareceived(0)<=(others=>'0');
-				end if;
-				end if;
-			--elsif Port_out_data_available='1' and CTR='0' then
-			--		etrec<=r_drop;
-			else
-				
-				etrec<=r_wait;
-			end if;
-			DS_RDY<='0';
-			When r_drop => -- ignorer les messages qui arrivent à ce noeud tant que 
-								--l'application n'a pas été initialisée
-						if port_out_data_available='0' then 
-							etrec<=r_end;
-							dcount:=0;
-							
-						end if;
-						
-						
-						
-						--Rport_out_rd_en<='1'; --lire les données qui sont dans le tampon de sortie		
-						DS_RDY<='0';
-			when r_Dlen =>   --positionnement du mot de longueur des données
-			if Port_out_data_available ='1' then 
-			
-			--Rport_out_rd_en<='1';
-			etrec<=r_glen;
-			rtimeout:=0;
-			else
-				rtimeout:=rtimeout+1;
-					if rtimeout>=30 then 
-					  assert true report "Ex4:etrec r_glen Timeout -> Impossible de recevoir du NoC"
-				        severity failure;
-					Exectime_out<='0';  --read Noc time out
-						etrec<=r_end;             -- données pas prêtes
-					end if;
-			
-			
-			end if;
-			DS_RDY<='0';
-			--  
-			when r_glen =>   --lecture effective de la longueur des données
-			if port_out_data_available='1' then 
-			dlen:=to_integer(unsigned(port_out_data(Word-1 downto 0)));
-			Datareceived(1)<=Port_out_data;
-			--RPort_out_rd_en<='0';
-			etrec<=r_data;
-			dcount:=2;  -- initialisation du compteur de reception (il y a 
-							-- déjà deux mots reçues
-			else
-				rtimeout:=rtimeout+1;
-					if rtimeout>=30 then 
-					 assert true report "Ex4:etrec Timeout -> Impossible de recevoir sur le NoC"
-				        severity failure;
-					ExecTime_out<='0';
-						etrec<=r_end;             -- données pas prêtes
-					end if;
-			
-			end if;
-			DS_RDY<='0';
-			when r_data =>    					-- lecture des données
-			if port_out_data_available='1'  then 
-					
-					--Rport_out_rd_en<='1';   --autoriser la lecture
-					if bad_paquet='0' then
-						DataReceived(dcount)<=Port_out_data; --récupération des données
-					else
-						DataReceived(2)<=(others=>'0');
-					  --ignorer ces données
-					end if;
-					--assert true report "Donnée lue :"; --& string(unsigned(port4_out(Word-1 downto 0)))
-					DS_RDY<='0';
-					dcount:=dcount+1;
-					--severity note;
-					if dlen <=dcount then -- ce doit être égale ici et non <= ???
-						etrec<=r_end;
-						DS_RDY<= not bad_paquet; -- jeu de données disponibles
-					elsif dcount=255 then   --dépassement de la capacité
-						DS_RDY<='0';
-						etrec<=r_end;
-					end if;
-			else
-					rtimeout:=rtimeout+1;
-					if rtimeout>=30 then 
-					   ExecTime_out<='0';
-						etrec<=r_end;             -- données pas prêtes
-					end if;
-					DS_RDY<='0';
-					
-			end if;
-			when r_pulse =>
-					etrec<=r_end; 
-					DS_RDY<=not bad_paquet;
-			when r_end =>
-						
-			--rPort_out_rd_en <='0';
-			
-			if DS_ACK='1' or rtimeout> 30 or (CTR='0' and SpawnOn='0') or bad_paquet='1' then 
-				DS_RDY<='0';
-				SpawnOn<='0';
-				etrec<=r_wait;
-			else
-				DS_RDY<=DS_RDY;
-			end if;			
-			end case;
-		 end if;--reset='1'
-		end if;   
-  end process preceiv;
-  
- val_preceiv: process (etrec)
-  begin
-  case etrec is
-					when r_wait  =>
---						DS_RDY<='0';
-						rcv_on<='0';
-						Rport_out_rd_en <='0';
-					when r_dlen  =>
---							DS_RDY<='0';
-							Rport_out_rd_en <='1';
-							rcv_On<='1';
-					when r_drop  =>
---							DS_RDY<='0';
-							Rport_out_rd_en <='1';
-							rcv_On<='1';
-					when r_glen =>
-							Rport_out_rd_en <='1';
---							DS_RDY<='0';
-							rcv_On<='1';
-					when r_data =>
-							Rport_out_rd_en <='1';
---							DS_RDY<='0';
-							rcv_On<='1';
-					when r_pulse =>
-								Rport_out_rd_en <='0';
-								rcv_On<='1';
---								DS_RDY<='1';
-					when r_end =>
-							Rport_out_rd_en <='0';
---							DS_RDY<='0';
-							rcv_On<='0';
-					when others =>
-							Rport_out_rd_en <='0';
---							DS_RDY<='0';
-							rcv_On<='0';
-				end case;
-	end process;
-  
-  psend:process(clk,reset)
-		--génération des paquets à partir du  port courant
-		variable pactype :natural range 0 to 15;
-		variable destport : natural range 0 to 15:=0;
-		variable realdlen, i,i_pair : natural range 0 to 255;
-		variable MaxPort : natural :=4; -- en fait ne doit pas être 0
-		
-		
-				begin
-				if rising_edge(clk) then 
-						 if reset='1' then 
-								etsnd<=s_init;
-				 
-				    
-						 
-						else -- le process s'exécute sur chaque front 
-															-- montant de l'horloge
-						case etsnd is
-						when s_init => tosend<=(others=>'-');
-											MaxPort :=to_integer(unsigned(NOCMAX));
-								sPort_in_wr_en<='0';
-							if port_in_full='0' and Rts_dat='1' then   --on peut aussi tester si le port est vide
-							        BCast_RDY<='0';  -- pas la fin de du Broadcasting
-									  Send_RDY<='0';
-									  Snd_on<='1';
-									  if Bcast='1' then -- envoyer à tous les ports le même message ?
-									  DestPort :=0;
-									  else
-										DestPort:=to_integer(unsigned(data_to_send(0)(3 downto 0)));
-									  end if;
-									  etsnd<=s_head;
-							end if;
-						when s_head  =>    -- construction et envoie de l'en-tête
-						Send_RDY<='0'; --l'envoi commence
-						BCast_RDY<='0';
-						Snd_on<='1';
-						--pactype:=to_integer(MPI_INIT);--
-						pactype:=to_integer(unsigned(data_to_send(0)(7 downto 4)));
-						--realdlen:=to_integer(unsigned(Datalen));
-						--? destport:=MAXPORT; -- le port de destination
-						
-						tosend <=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
-						 sPort_in_wr_en<='1';   -- 
-						 
-						 i:=1;
-						 etsnd<=s_len2;  -- passer à l'état suivant
-						 
-						when s_len => 
-							BCast_RDY<='0';
-							Send_RDY<='0';
-							Snd_on<='1';
-							--tosend<=(STD_LOGIC_VECTOR(to_unsigned(Realdlen,8)));
-							tosend<=data_to_send(1);
-							sPort_in_wr_en <='1';
-							
-
-							--port1_in<=tosend1; --copie directe sur le port 
-							etsnd<=s_len2;
-						when s_len2 => 
-							--tosend<=(STD_LOGIC_VECTOR(to_unsigned(realdlen,8)));
-							sPort_in_wr_en<='1';
-							tosend<=data_to_send(1);
-
-							--port1_in<=tosend1; --copie directe sur le port 
-							etsnd<=s_data;	
-							BCast_RDY<='0';
-							Send_RDY<='0';
-							Snd_on<='1';
-							i:=i+1;
-						when s_data =>
-							Snd_on<='1';
-							if Port_in_full='0' and RTS_dat='1' then
-								sPort_in_wr_en<='1';
-								
-								     --envoie des données sur le port   
-									tosend<=data_to_send(i);
-								
-								
-								if i+1>=datalen then 
-									etsnd<=s_end;
-									Send_RDY<='1'; --l'envoi est terminé
-									if BCast='1' and destport=MAXPort then
-										BCAST_RDY<='1'; --l'envoi collectif aussi
-									else 
-										BCast_RDY<='0';
-							
-									end if;
-								else
-									BCast_RDY<='0';
-									Send_RDY<='0';
-									i:=i+1;
-								end if;
-							elsif port_in_full='1' then
-          							sPort_in_wr_en<='0';
-							else
-								sPort_in_wr_en<='0';
-								BCast_RDY<='0';
-								Send_RDY<='0';
-							end if;
-						when s_end  =>
-						 tosend<=(others=>'-');
-							
-							sPort_in_wr_en<='0';
-							if Bcast='1' then
-							if destPort<Maxport then
-								DestPort:=Destport+1;
-								etsnd<=s_head;
-								
-								else
-								BCast_RDY<='1' ; -- BroadCast End=Ok
-									if Send_ack='1' then
-										etsnd<=s_init;
-										Send_RDY<='0';
-										Snd_on<='0';
-									end if;
-								end if;
-							else
-								BCast_RDY<='0';
-								if Send_ack='1' then
-									etsnd<=s_init;
-									Send_RDY<='0';
-									Snd_on<='0';
-								end if;
-								
-							end if;
-						end case;	
-						
-										
-						end if;  --reset ='1'
-					end if; --rising_edge...
-		end process psend;	
-
--- envoi des commandes		
-pcmd:process(clk,reset)
-	
-	variable origport,destport,pid,mport : natural range 0 to 15;
-	variable ctimeout:natural range 0 to 255;
-	begin
-	
-	
-		if reset='1' then
-			etcmd<=cmdstart;
-			
-	--		sorigport<=origport;
-		else
-		if  rising_edge(clk) then
-					case  etcmd is
-					when cmdstart =>
-						if Port_in_empty='1' and RTS_Cmd='1' then 
-									etcmd<=cmdpost;
-						
-						end if;
-						destport:=0;
-						ctimeout:=0;
-						origport:=1;
-				 when cmdpost =>
-					if Port_in_empty='1' then 
-						etcmd<=cmdread;
-					end if;
-					
-				when cmdpostidle  =>   --permet juste la prise en compte de la commande
-						etcmd<=cmdread;
-						dcount<=0;-- initialisation du compteur de reception
-				 when cmdread =>
-						
-						
-						ctimeout:=0;
-						
-					if Port_out_data_available='1' then 
-						mport:=to_integer(unsigned(port_out_data(7 downto 4)));
-						pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1;
-						CmdReceived(dcount)<=port_out_data;
-						--cdata_out_en(origport)<='1';
---						if pid=origport then --le port a été bien identifié
-								etcmd<=cmdglen; --
-								dcount<=dcount+1;
---							else
---							etcmd<=cmdtimeout;
---						end if;
-					else
-
-						etcmd<=cmdread;
-					end if;
-					
-					
-					when cmdlen =>   --positionnement du mot de longueur des données
-					if Port_out_data_available='1' then 
-					
-					etcmd<=cmdglen;
-					ctimeout:=0;
-					else
-						ctimeout:=ctimeout+1;
-							if ctimeout>=30 then 
-							  assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC"
-				        severity failure;
-								etcmd<=cmdtimeout;             -- données pas prêtes
-							end if;
-					
-					
-					end if;
-					when cmdglen =>   --lecture effective de la longueur des données
-					if Port_out_data_available='1' then 
-						cdlen<=to_integer(unsigned(port_out_data(Word-1 downto 0)));
-						CmdReceived(dcount)<=port_out_data;
-						etcmd<=cmddata;
-					  dcount<=dcount+1;
-					else
-						ctimeout:=ctimeout+1;
-							if ctimeout>=30 then 
-							--time_out(destport)<='1';
-							 assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC"
-				        severity failure;
-								etcmd<=cmdtimeout;             -- données pas prêtes
-							end if;
-					
-					end if;
-					
-					when cmddata =>
-					if (port_out_data_available='1' and ctimeout<30) then 
-							
-							--cdata_out_en(origport)<='1';
-							mport:=to_integer(unsigned(port_out_data(7 downto 4)));
-							--attention les ports sont numérotés à partir de 0
-							pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1;
-							CmdReceived(dcount)<=port_out_data;
-							if (dcount>=cdlen-1 ) then--attention le compteur de données commence à 0
-								etcmd<=cmdend;
-								--CM_RDY<='1';
-							else
-								dcount<=dcount+1;
-							end if;			
-					Else
-							
-							if ctimeout>=30 then 
-								--time_out(destport)<='1';
-								etcmd<=cmdtimeout;             -- données pas prêtes
-							 assert true report "Ex4:etcmd. cmddata Timeout -> impossible de recevoir du le NoC"
-				        severity failure;
-							else
-							ctimeout:=ctimeout+1;
-							etcmd<=cmdend;
-							end if;
-					end if;
-					when cmdend =>
-				
-							etcmd<=cmdstart;
-
-					when cmdtimeout =>
-
-					  etcmd<=cmdstart;
-					end case;
-		--sorigport<=origport;	
-		end if;   --reset='1'
-	end if;
-  end process pcmd;	
-
-majetcmd: process (etcmd,data_to_send, port_out_data_available, dcount,port_out_data)
-variable origport : natural;
-variable i:natural:=0;
-	begin
-			case  etcmd is
-		when cmdstart =>
-				i:=0;
-				Port_in_cmd_en<='0';
-				tosend4<=(others=>'-');
-				cport_out_rd_en<='0';
-				cport_in_wr_en<='0';
-				CM_RDY<='0';
-				Cmd_on<='0';
-		 when cmdpost | cmdpostidle =>
-				cport_in_wr_en<='1';
-				tosend4<=data_to_send(0); ---code pour getportid
-				Port_in_cmd_en<='1';
-				cport_out_rd_en<='0';
-				CM_RDY<='0';
-				Cmd_on<='1';
-		 when cmdread =>
-				tosend4<=(others=>'-');
-				cPort_in_wr_en<='0';
-				cport_out_rd_en<=port_out_data_available;
-				--CmdReceived(dcount)<=port_out_data;  --mettre les données dans le tampon
-				Port_in_cmd_en<='1';
-				CM_RDY<='0';
-				Cmd_on<='1';
-		when cmdlen |cmdglen =>   --positionnement du mot de longueur des données
-					tosend4<=(others=>'-');
-					cport_in_wr_en<='0';
-					cport_out_rd_en<=port_out_data_available;
-					Port_in_cmd_en<='1';
-					--CmdReceived(dcount)<=	port_out_data;
-					CM_RDY<='0';
-					Cmd_on<='1';
-		when cmddata =>
-					tosend4<=(others=>'-');
-					cport_in_wr_en<='0';
-					cport_out_rd_en<=Port_out_data_available;
-					Port_in_cmd_en<='1';
-					--CmdReceived(dcount)<=port_out_data;  --mettre les données dans le tampon
-					i:=i+1;
-					CM_RDY<='0';
-					Cmd_on<='1';
-			when cmdend =>
-					tosend4<=(others=>'-');
-				cport_in_wr_en<='0';
-				cport_out_rd_en<='0';
-				--CmdReceived(dcount)<=port_out_data; 
-				Port_in_cmd_en<='0';
-			    CM_RDY<='1';
-				 Cmd_on<='0';
-			when cmdtimeout =>
-					tosend4<=(others=>'-');
-				  cport_in_wr_en<='0';
-				  cport_out_rd_en<='0';
-				  Port_in_cmd_en<='0';
-					Cmd_on<='1';
-					cm_rdy<='0';
-			end case;
-		
-end process majetcmd ; 
-
-i_send_val:process(HCL_Init,Send_RDY,RTS_I,Snd_Ack,I_send_ack,data_to_send,Bcast_rdy,Bcast)
-begin
-snd_start_i<=snd_start;
-RTS_DAT<='0';
-
-if HCL_Init='1' then
- if RTS_I='1' and snd_ack='0' then
-  snd_start_i<='1';
- elsif i_send_ack='1' then
- 
- snd_start_i<='0';
- end if;
-  i_send_rdy<=snd_ack;
-
-  Snd_data<=data_to_send;
-else
-  if RTS_I='1' and i_send_ack='0' then
-  RTS_DAT<='1';
- elsif i_send_ack='1' then
- 
- RTS_DAT<='0';
- end if;
- i_send_rdy<=send_rdy;
- for i in 0 to 3 loop 
- Snd_data(i)<=(others=>'0');
- end loop;
-end if;
-end process;
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Ex0_Fsm.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Ex0_Fsm.vhd	(revision 96)
+++ 	(revision )
@@ -1,206 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: GAMOM 
--- 
--- Create Date:    05:37:34 03/06/2012 
--- Design Name: 
--- Module Name:    Ex0_Fsm - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: Fournit le temps en µs depuis l'initialisation de la bibliothèque
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library NocLib ;
-
---use NocLib.CoreTypes.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity Ex0_Fsm is
-    Port ( Initialized : in  STD_LOGIC;
-           
-           Instruction : in  STD_LOGIC_VECTOR (7 downto 0);
-			  instruction_en: in STD_LOGIC; --ceci n'est pas nécessaire dans ce module
-													-- car le module fonctionne en permanence.
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           ClkRate : in  STD_LOGIC_VECTOR; --la fréquence de l'horloge en Mhz
-			uTimeResult : out  STD_LOGIC_VECTOR; 
-			TickResult : out STD_LOGIC_VECTOR;
-			OvFus : out STD_Logic:='0'
-			  );
-end Ex0_Fsm;
-
-architecture Behavioral of Ex0_Fsm is
- 
- --Use descriptive names for the states, like st1_reset, st2_search
-   type state_type is (Init,COunt,UsOut,OverFlow); 
-   signal state, next_state : state_type; 
-   --Declare internal signals for all outputs of the state-machine
-   signal Tick_Count: std_logic_vector(31 downto 0):=(others=>'0');
-	signal Time_Ucount :std_logic_vector(31 downto 0):=(others=>'0');
-	signal OvF,Ovf_us,ovF_i,zero :std_logic;   -- overflow flag
-   signal ClkR_Count : std_logic_vector(ClkRate'high downto ClkRate'low):=(others=>'0');
-	signal en : std_logic:='1';
-	--other outputs
-begin
-utime_PROC: process (clk)
-   begin
-      if (rising_edge(clk)) then
-         if (reset = '1') or Initialized='0' then
-            state <= init;
-          --  Time_UCount<= (others=>'0');
-			--	Tick_Count <=(others=>'0');
-         else
-            state <= next_state;
-			TickResult<= Tick_Count;
-			uTimeResult <=Time_ucount;
-			OvF<=OvF_i;
-			OvfUs<=Ovf_us;
-           -- <output> <= <output>_i;
-         -- assign other outputs to internal signals
-         end if;        
-      end if;
-   end process;
- 
-   --MOORE State-Machine - Outputs based on state only
-   OUTPUT_DECODE: process (state)
-   FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
-                  --this function increments a std_logic_vector type by '1' 
-        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
-        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
-        BEGIN 
-        tb(s1'low) := en; 
-        V := s1; 
-        for i in (V'low + 1) to V'high loop 
-            tb(i) := V(i - 1) and tb(i -1); 
-        end loop; 
-        for i in V'low to V'high loop 
-            if(tb(i) = '1') then 
-                V(i) := not(V(i)); 
-            end if; 
-        end loop; 
-        return V; 
-        end incr_vec; -- end function
-
-
-FUNCTION  dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
-                  --this function decrements a std_logic_vector type by '1' 
-        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
-        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
-        BEGIN 
-        tb(s1'low) := not(en); 
-        V := s1; 
-        for i in (V'low + 1) to V'high loop 
-            tb(i) := V(i - 1) or tb(i -1); 
-        end loop; 
-        for i in V'low to V'high loop 
-            if(tb(i) = '0') then 
-                V(i) := not(V(i)); 
-            end if; 
-        end loop; 
-        return V; 
-        end dcr_vec; -- end function
-FUNCTION all_ones(s1:std_logic_vector) return std_logic is 
-                  --this function tells if all bits of a vector are '1' 
-                  --return value Z is '1', then vector has all 1 bits 
-        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
-        VARIABLE Z : std_logic; 
-        BEGIN 
-        Z := s1(s1'low); 
-        FOR i IN (s1'low+1) to s1'high LOOP 
-            Z := Z AND s1(i); 
-        END LOOP; 
-        RETURN Z; 
-        END all_ones; -- end function
-FUNCTION all_zeros(s1:std_logic_vector) return std_logic is 
-                  --this function tells if all bits of a vector are '0' 
-                  --return value Z if '1', then vector has all 0 bits 
-        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
-        VARIABLE Z : std_logic; 
-        BEGIN 
-        Z := '0'; 
-        FOR i IN (s1'low) to s1'high LOOP 
-            Z := Z OR s1(i); 
-        END LOOP; 
-        RETURN not(Z); 
-        END all_zeros; -- end function
-
-	begin
-      --insert statements to decode internal output signals
-      --below is simple example
-      case state is
-		When Init =>
-			Clkr_Count<=ClkRate;  --initialiser le décompte
-			Time_uCount<=( others =>'0'); -- mettre à 0 le compteur des µS
-			Tick_Count<=(others =>'0');  --mettre à 0 les ticks
-		When Count =>
-		  Tick_count<=incr_vec(Tick_Count,en);
-		  ClkR_Count<=dcr_vec(Clkr_Count,en); --compteur de µs
-		  zero<=all_zeros(ClkR_Count);   --
-		  OvF_i<=All_ones(Tick_count);   --
-		when UsOut =>
-			Time_Ucount<=incr_vec(time_ucount,en);
-			Clkr_Count<=ClkRate;
-			Tick_count<=incr_vec(Tick_Count,en);
-			OvF_i<=All_ones(Tick_count);
-			zero<='0';
-         OvF_us<=All_ones(Time_Ucount);
-      when OverFlow =>
-         Tick_count<=incr_vec(Tick_Count,en); --compteur de tick
-		  ClkR_Count<=dcr_vec(Clkr_Count,en);
-			OvF_us<=All_ones(Time_Ucount);
-		   OvF_i<=All_ones(Tick_count); 
-     end case;
-   end process;
- 
-   NEXT_STATE_DECODE: process (state, Initialized, zero, OvF)
-   begin
-      --declare default state for next_state to avoid latches
-      next_state <= state;  --default is to stay in current state
-      --insert statements to decode next_state
-      --below is a simple example
-      case (state) is
-         when Init =>
-            if Initialized = '1' then
-				   
-               next_state <= count;
-            end if;
-         when Count =>
-            if Zero = '0'  then
-               next_state <= Count;
-				elsif Zero = '1'  then
-					next_state <=Usout;
-			
-            end if;
-         when UsOut =>
-				If OvF='0'  then
-					next_state <= count;
-				elsif OvF='1' then
-					next_state <= OverFlow;
-				end if;
-			When OverFlow =>
-					next_state<=Count;
---         when others =>
---            next_state <= Init;
-      end case;      
-   end process;
-
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Ex5_FSM.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Ex5_FSM.vhd	(revision 96)
+++ 	(revision )
@@ -1,141 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    14:00:24 08/01/2013 
--- Design Name: 
--- Module Name:    Ex5_FSM - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity Ex5_FSM is
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-				
-			  SpawnOn : in  STD_LOGIC;
-           NocPortFree : in  STD_LOGIC;
-           InterCSet : in  STD_LOGIC;
-           TaskLoaded : in  STD_LOGIC;
-           TaskInit : in  STD_LOGIC;
-           TaskOn : in  STD_LOGIC;
-           TimeOut : out  STD_LOGIC;
-           DataReceived : in  STD_LOGIC_VECTOR (7 downto 0);
-           DataToSend : out  STD_LOGIC_VECTOR (7 downto 0));
-end Ex5_FSM;
-
-architecture Behavioral of Ex5_FSM is
-type Spawn_type is (Init,CheckFree,LoadTask,CountTask,StartTask,WaitTaskInit,SetGroup,SetInterCom,RetInterCom,ErrSpawn,EndSpawn); 
-   signal spawn_st, next_spawn : spawn_type; 
-begin
---Insert the following in the architecture after the begin keyword
-   SYNC_spawn: process (clk)
-   begin
-      if (clk'event and clk = '1') then
-         if (reset = '1') then
-            spawn_st <= init;
-            
-         else
-           spawn_st <= next_spawn;
-            --<output> <= <output>_i;
-         -- assign other outputs to internal signals
-         end if;        
-      end if;
-   end process;
- 
-   --MOORE State-Machine - Outputs based on state only
-   OUTPUT_DECODE: process (Spawn_st)
-   begin
-      --insert statements to decode internal output signals
-      --below is simple example
-      case (spawn_st) is
-         when init =>
-            
-         when CheckFree =>
-            
-         when LoadTask =>
-           
-			when StartTask =>
-			
-			when CountTask =>		
-			
-			 when WaitAllTaskInit =>
-			 
-			 when SetGroup =>
-			 
-			 when SetInterCom =>
-			 
-			 when RetInterCom =>
-			 
-			 when EndSpawn =>
-			 
-         when others =>
-            
-      end case;      
-   end process;
- 
-   NEXT_STATE_DECODE: process (spawn_st, spawnOn,Datareceived)
-   begin
-      --declare default state for next_state to avoid latches
-      next_spawn <= spawn_st;  --default is to stay in current state
-      --insert statements to decode next_state
-      --below is a simple example
-      case (spawn_st) is
-         when init =>
-            if spawnOn = '1' then
-               next_spawn <= Checkfree;
-            end if;
-         when CheckFree =>
-            if NoCPortFree = '1' then
-               next_spawn<= LoadTask;
-            end if;
-         when LoadTask =>
-           next_spawn <= CountTask;
-			when StartTask =>
-				 if TaskInit = '1' then
-           next_spawn <= WaitAllTaskInit;
-			  end if;
-			 when WaitAllTaskInit =>
-			 if InterComSet = '1' then
-           next_spawn <= SetGroup;
-			 end if;
-			 when SetGroup =>
-			 if InterComSet = '1' then
-           next_spawn <= SetInterCom ;
-			 end if;
-			 when SetInterCom =>
-			 if InterComSet = '1' then
-           next_spawn <= RetInterCom ;
-			 end if;
-			 when RetInterCom =>
-			 if AppAck = '1' then
-				next_spawn <= EndSpawn;
-			end if;
-         when others =>
-            next_spawn <= init;
-      end case;      
-   end process;
-
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/FIFO_64_FWFT.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/FIFO_64_FWFT.vhd	(revision 96)
+++ 	(revision )
@@ -1,223 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: KIEGAING EMMANUEL/GAMOM
--- 
--- Create Date:    19:51:54 04/19/2011 
--- Design Name: 
--- Module Name:    FIFO_64 - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---FIFO 64 Octets utisé pour les modules d'entrée 
--- ce fifo est de type fwft first word falls throught ce qui 
--- signifie que l'on a toujours la donnée au sommet de la pile en 
--- sortie du fifo. 
--- Dependencies:  RAM_64.vhd
--- 
--- Revision: 08-11-2012
--- Revision 0.01 - File Created
--- Additional Comments: suppression du signal counter_en dans les expressions 
--- 08/11/12 : prise en compte du retard de propagation des infos dans la FIFO.
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-Library NocLib;
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity FIFO_64_FWFT is
-    Port ( clk : in  STD_LOGIC;
-           din : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           rd_en : in  STD_LOGIC;
-           srst : in  STD_LOGIC;
-           wr_en : in  STD_LOGIC;
-           dout : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           empty : out  STD_LOGIC;
-           full : out  STD_LOGIC);
-end FIFO_64_FWFT;
-
-architecture Behavioral of FIFO_64_FWFT is
--- declaration de la ram 64 octets
-COMPONENT RAM_64
-	PORT(
-		clka : IN std_logic;
-		clkb : IN std_logic;
-		wea : IN std_logic;
-		ena : IN std_logic;
-		enb : IN std_logic;
-		addra : IN std_logic_vector(5 downto 0);
-		addrb : IN std_logic_vector(5 downto 0);
-		dia : IN std_logic_vector(Word-1 downto 0);          
-		--doa : OUT std_logic_vector(Word-1 downto 0);
-		dob : OUT std_logic_vector(Word-1 downto 0)
-		);
-	END COMPONENT;
-type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm
-signal fwft_fsm_state : fsm_states;
-type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0);
-	signal RAM: ram_type;
--- declaration des signeaux des compteurs
-signal push_address_counter : std_logic_vector(5 downto 0);
-signal pop_address_counter : std_logic_vector(5 downto 0);
-signal fifo_counter : std_logic_vector(5 downto 0):=(others=>'0');
---autre signaux
-signal rd_ready : std_logic:='0';
-signal empty_signal : std_logic;
-signal full_signal  : std_logic;
-signal wr_en_signal : std_logic;
-signal rd_en_signal : std_logic;
-signal clk_signal :  std_logic;
-signal dob_signal : std_logic_vector(Word-1 downto 0);
-signal dout_signal : std_logic_vector(Word-1 downto 0);
-signal doa_signal : std_logic_vector(Word-1 downto 0);
-signal counter_en : std_logic; 
-
-begin
-
--- ram instantiation de la ram 64 octets du FIFO
---fifo_RAM_64: RAM_64 PORT MAP(
---		clka => clk_signal,
---		clkb => clk_signal,
---		wea => wr_en_signal,
---		ena => wr_en_signal,
---		enb => rd_en_signal,
---		addra => push_address_counter,
---		addrb => pop_address_counter,
---		dia => din,
---		--doa => doa_signal,
---		dob => dob_signal
---	);
--- circuiterie des signaux de validation et d'etat du fifo
-wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein
-rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide
-full_signal <= '1' when fifo_counter = "111111" else
-				   '0';
-empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0  else
-					 '0';
-clk_signal <= clk;
-full <= full_signal;
-empty <= empty_signal;
-
--- sortie du fifo fwft
-dout <= dout_signal;
-
--- le processus des transistion
-fwft_fsm_nsl : process(clk)
- begin
-    if rising_edge(clk) then
-	   if srst = '1' then
-		   fwft_fsm_state  <= state0;
-		else
-		   case fwft_fsm_state  is
-					when state0 => if wr_en_signal = '1' then  --tampon vide seule l'écriture est possible
-											fwft_fsm_state  <= state1;
-										end if;
-										
-										
-					when state1 => --if rd_en_signal = '1' and wr_en_signal='1'  then  --écriture seule dans le tampon
-											
-											fwft_fsm_state  <= state2;
-										--end if;
-										
-					when state2 => if rd_en_signal = '1' and wr_en_signal='1'  then
-											fwft_fsm_state  <= state2;
-										elsif rd_en_signal='1' and wr_en_signal='0' and unsigned(fifo_counter) = 1 then --lecture avec écriture
-											fwft_fsm_state  <= state0;
-										elsif unsigned(fifo_counter) = 0 then
-											fwft_fsm_state  <= state0;
-										end if;
-					
-					when others => fwft_fsm_state <= state0;
-			end case;
-	   end if;
-	end if;
- end process;
- -- actions associées à la fsm
- -- mux qui oriente les sortie doa et dob vers out
- val_fwft:process (fwft_fsm_state,dob_signal)
- 
- begin
- case fwft_fsm_state  is
-					when state0 => 
-		
-						dout_signal <= dob_signal;
-						counter_en   <= '0';
-						rd_ready <='0';
-					when state1 => 
-		
-						dout_signal <= dob_signal;
-						counter_en   <= '1';
-						rd_ready <='0';
-					when state2 => 
-		
-						dout_signal <= dob_signal;
-						counter_en   <= '1';
-						rd_ready <='1';
-					when others =>
-	               dout_signal <= dob_signal;
-						counter_en   <= '0';
-						rd_ready <='0';
-		end case;
-end process;
-doa_latch_process : process(clk)
-begin
-  if rising_edge(clk) then
-		if wr_en_signal ='1'  then
-			doa_signal <= din;
-		end if;
-  end if;
-end process;
-	               
--- processus de comptage des adresses d'empilement
-push_process : process(clk)
- begin
- if rising_edge(clk) then
-   if srst = '1' then
-	 push_address_counter <= (others =>'0');
-	elsif wr_en_signal ='1' then
-			RAM(conv_integer(push_address_counter)) <=din;
-	   	push_address_counter <= push_address_counter +1;
-	 end if;
- end if;
-end process;
- 
- -- processus de comptage des adresses depilement du fifo
-pop_process : process(clk)
- begin
- if rising_edge(clk) then
-   if srst = '1' then
-	  pop_address_counter <= (others =>'0');
-	elsif rd_en_signal ='1' then
-		pop_address_counter <= pop_address_counter +1;
-	end if;
- end if;
- end process;
-  dob_signal<=RAM(conv_integer(pop_address_counter));
- -- processus de comptage des octets dans le fifo
- fifo_counter_process : process(clk)
- variable count : std_logic_vector(5 downto 0):= (others=>'0');
-begin
- if rising_edge(clk) then
-   if srst = '1' then
-	 fifo_counter <= (others =>'0');
-	 count:=(others =>'0');
-	else
-	 if wr_en_signal ='1'  and rd_en_signal ='0' then 
-			count:=count+1;
-	  end if;
-	 if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then
-			count:=count-1;		
-	 end if;
-	 fifo_counter<=count;
-  end if;
- end if;
-end process;
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/FIfo_mem.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/FIfo_mem.vhd	(revision 96)
+++ 	(revision )
@@ -1,91 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    04:35:05 10/15/2012 
--- Design Name: 
--- Module Name:    FIfo_mem - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-
-
-library IEEE; 
-use IEEE.std_logic_1164.all; 
-use IEEE.std_logic_unsigned.all; 
-entity FIFO is 
- generic (N: integer := 6; -- number of address bits for 2**N address locations 
-M: integer := 8);  -- number of data bits to/from FIFO 
- port (CLK, PUSH, POP, INIT: in std_logic; 
-  DIN: in std_logic_vector(N-1 downto 0); 
-DOUT: out std_logic_vector(N-1 downto 0); 
-  FULL, EMPTY, NOPUSH, NOPOP: out std_logic; 
-  clk: IN std_logic;
-	
-	rd_en: IN std_logic;
-	srst: IN std_logic;
-	wr_en: IN std_logic;
-	
-	empty: OUT std_logic;
-	full: OUT std_logic);
-end entity FIFO; 
-architecture TOP_HIER of FIFO is 
-signal WE: std_logic; 
-signal A: std_logic_vector(N-1 downto 0); 
-signal  PUSH, POP, INIT:  std_logic; 
- 
-signal NOPUSH, NOPOP:  std_logic;
-
-component FIFO_LOGIC is 
- generic (N: integer); -- number of address bits 
- port (CLK, PUSH, POP, INIT: in std_logic; 
-  ADD: out std_logic_vector(N-1 downto 0); 
-  FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); 
-end component FIFO_LOGIC; 
-
-COMPONENT RAM_256
-	PORT(
-		clka : IN std_logic;
-		clkb : IN std_logic;
-		wea : IN std_logic;
-		ena : IN std_logic;
-		enb : IN std_logic;
-		addra : IN std_logic_vector(Word-1 downto 0);
-		addrb : IN std_logic_vector(Word-1 downto 0);
-		dia : IN std_logic_vector(Word-1 downto 0);          
-		dob : OUT std_logic_vector(Word-1 downto 0)
-		);
-END COMPONENT;
-begin 
--- example of component instantiation using positional notation 
-FL: FIFO_LOGIC generic map (N) 
- port map (CLK, PUSH, POP, INIT, A, FULL, EMPTY, WE, NOPUSH, NOPOP);  
-Push<=wr_en;
-pop<=rd_en;
-nopush<=nopush;
-nopop<=nopop;
-init<=srst;
--- example of component instantiation using keyword notation 
---R: RAM generic map (W => N, K => M) 
--- port map (DIN => DIN, ADDR => A, WR => WE, DOUT => DOUT); 
-R: RAM_256 PORT MAP(
-		clka => clk,
-		clkb => clk,
-		wea => we,
-		ena => '1',
-		enb => '1',
-		addra => A,
-		addrb => A,
-		dia => din,
-		dob => dout
-	);
-end architecture TOP_HIER;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/FIfo_proc.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/FIfo_proc.vhd	(revision 96)
+++ 	(revision )
@@ -1,102 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    04:35:05 10/15/2012 
--- Design Name: 
--- Module Name:    FIfo_mem - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-
-library IEEE; 
-use IEEE.std_logic_1164.all; 
-use IEEE.std_logic_unsigned.all; 
-entity FIFO_LOGIC is 
- generic (N: integer := 3); 
- port (CLK, PUSH, POP, INIT: in std_logic; 
-  ADD: out std_logic_vector(N-1 downto 0); 
-  FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); 
-end entity FIFO_LOGIC; 
-architecture RTL of FIFO_LOGIC is 
-signal WPTR, RPTR: std_logic_vector(N-1 downto 0); 
-signal LASTOP: std_logic; 
-begin 
-SYNC: process (CLK) begin 
- if (CLK'event and CLK = '1') then 
-  if (INIT = '1') then  -- initialization -- 
-   WPTR <= (others => '0'); 
-   RPTR <= (others => '0'); 
-   LASTOP <= '0'; 
-  elsif (POP = '1' and EMPTY = '0') then  -- pop -- 
-   RPTR <= RPTR + 1; 
-   LASTOP <= '0'; 
-  elsif (PUSH = '1' and FULL = '0') then  -- push -- 
-   WPTR <= WPTR + 1; 
-   LASTOP <= '1'; 
-  end if;  -- otherwise all Fs hold their value -- 
- end if; 
-end process SYNC;
-COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY) begin 
--- full and empty flags -- 
- if (RPTR = WPTR) then 
-  if (LASTOP = '1') then 
-      FULL  <=  '1'; 
-   EMPTY <= '0'; 
-    else 
-      FULL  <=  '0'; 
-   EMPTY <= '1'; 
-  end if; 
- else 
-  FULL <= '0'; 
-  EMPTY <= '0'; 
- end if; 
--- address, write enable and nopush/nopop logic -- 
- if (POP = '0' and PUSH = '0') then -- no operation -- 
-  ADD <= RPTR; 
-  WE <= '0'; 
-  NOPUSH <= '0'; 
-  NOPOP <= '0'; 
- elsif (POP = '0' and PUSH = '1') then -- push only -- 
-  ADD <= WPTR; 
-  NOPOP <= '0'; 
-  if (FULL = '0') then -- valid write condition -- 
-   WE <= '1'; 
-   NOPUSH <= '0'; 
-  else     -- no write condition -- 
-   WE <= '0'; 
-   NOPUSH <= '1'; 
-  end if; 
- elsif (POP = '1' and PUSH = '0') then -- pop only -- 
-  ADD <= RPTR; 
-  NOPUSH <= '0'; 
-  WE <= '0'; 
-  if (EMPTY = '0') then -- valid read condition -- 
-   NOPOP <= '0'; 
-    else 
-   NOPOP <= '1';  -- no red condition -- 
-  end if; 
- else   -- push and pop at same time - 
-  if (EMPTY = '0') then -- valid pop -- 
-  ADD <= RPTR; 
-   WE <= '0'; 
-   NOPUSH <= '1'; 
-   NOPOP <= '0'; 
-    else 
-   ADD <= wptr; 
-   WE <= '1'; 
-   NOPUSH <= '0'; 
-   NOPOP <= '1'; 
-  end if; 
- end if; 
-end process COMB; 
-end architecture RTL;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/fifo_test.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/fifo_test.vhd	(revision 96)
+++ 	(revision )
@@ -1,46 +1,0 @@
--- TestBench Template 
-
-  LIBRARY ieee;
-  USE ieee.std_logic_1164.ALL;
-  USE ieee.numeric_std.ALL;
-
-  ENTITY testbench IS
-  END testbench;
-
-  ARCHITECTURE behavior OF testbench IS 
-
-  -- Component Declaration
-          COMPONENT <component name>
-          PORT(
-                  <port1> : IN std_logic;
-                  <port2> : IN std_logic_vector(3 downto 0);       
-                  <port3> : OUT std_logic_vector(3 downto 0)
-                  );
-          END COMPONENT;
-
-          SIGNAL <signal1> :  std_logic;
-          SIGNAL <signal2> :  std_logic_vector(3 downto 0);
-          
-
-  BEGIN
-
-  -- Component Instantiation
-          uut: <component name> PORT MAP(
-                  <port1> => <signal1>,
-                  <port3> => <signal2>
-          );
-
-
-  --  Test Bench Statements
-     tb : PROCESS
-     BEGIN
-
-        wait for 100 ns; -- wait until global set/reset completes
-
-        -- Add user defined stimulus here
-
-        wait; -- will wait forever
-     END PROCESS tb;
-  --  End Test Bench 
-
-  END;