Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/HT_4.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/HT_4.vhd	(revision 97)
+++ 	(revision )
@@ -1,526 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    12:04:21 04/22/2013 
--- Design Name: 
--- Module Name:    HT_process - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-library NocLib ;
-use std.textio.all;
-use NocLib.CoreTypes.all;
-use work.Packet_type.all;
-use work.MPI_RMA.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
---entity HT_process is
---		generic (Task_id : natural:=0);
---    Port ( clk : in  STD_LOGIC;
---           reset : in  STD_LOGIC;
---			  en : in std_logic; -- active la tâche
---           Interf_i : in  core_i; --signaux pour l'interface IO
---			  Interf_o : out  core_o; --signaux pour l'interface IO
---           mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire
---			  mem_i : in typ_dpram_i -- signaux pour l'accès à la mémoire
---			  );
---end HT_process;
-
-architecture A2 of HT_process is
-
-  type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart,
-  putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout);
-	signal sram : typ_dpram;
-	signal MyGroup:mpi_group;
-	signal MyWin : mpi_win;
-	signal MyRank :std_logic_vector(3 downto 0);
-	signal intercomm,array_of_errcodes : natural;
-	signal ct_state:natural:=0;
-signal Libr : Core_io;  --regroupe tous les signaux IO de la bibliothèque
-signal RunState : typ_mae;
-
-begin
-
---MAE du PE
---=======================================================================
--- Interf<=Libr;
-
-
- pPutGet:process(clk,reset,en)
- 
-	constant DATAPTR : natural :=256;
-	variable nb_rma:natural range 0 to 15:=0;
-	variable bfill,destrank,pid,mport : natural range 0 to 15;
-	variable fsrc,ret : natural range 0 to 15:=0;
-	variable timeout,ct,dlen,dcount : natural range 0 to 255;
-	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
-	variable mywin : Mpi_win;
-	variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn 
-	variable comm : natural :=0;  
-	variable Spawn_on: std_logic:='0';
-	variable  adresse,adresse_rd :natural range 0 to 65536;
-	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
-
-	--=======================================================
-	--variables pour la création du fichier de résultats
-		-- synthesis translate_off 
-		type char_file is file of character;
-        file f: text;
-        variable status :file_open_status ;
-        variable char_count: integer range 0 to 65536 := 0;
-		  variable str: string (1 to 79) ;
-		  variable L: line; 
-		  variable fopened: std_logic:='0';
-		  
-		  constant simres : time :=1 ps; --simulation resolution
-		  constant realres : real :=1.0e-3; --ramener le temps en ns
-		  -- returns real value of time parameter using pure VHDL
-	     function rt(t : time) return real is
-	       begin
-		        return real(t/simres) * realres;
-	     end;
-		 -- synthesis translate_on
---======================================================
-	begin
-	--=== Partie combinatoire du process ===================================
-			
-	--=== Fin de la partie combinatoire du process ==========================	
-		
-		    
-           
-        --end loop;
-        
-	if (clk'event and clk='1') and en='1' then 
-			
-			
-		if reset='1' then
-					RunState<=start;
-					
-		else
-			--==========================================================
-			--affectation des entrées sorties mémoires
-			sram.i.data_out<=mem_I.data_out;
-			mem_o.addr_wr<=sram.O.addr_wr;
-			mem_o.addr_rd<=sram.O.addr_rd ; 
-			mem_o.we<=sram.O.we;
-			mem_o.ena<=sram.O.ena;
-			mem_o.enb<=sram.O.enb;
-			mem_o.data_in<=sram.O.data_in;
-			--affectation des entrées sorties MPI_HCL
-			Interf_o.Instr_EN<=Libr.O.instr_en;
-			Interf_o.Membusy<=Libr.O.MemBusy;
-			Interf_o.Instruction<=Libr.O.Instruction;
-			Libr.i.Instr_ack<=Interf_i.Instr_ack;
-			Libr.i.InitOk<=Interf_i.InitOk;
-			Libr.i.Hold_Req<=Interf_i.Hold_req;
-			Libr.I.Spawned<=Interf_i.Spawned;
-			--Libr.i.Hold_Ack<=Interf_i.Hold_Ack;
-			Libr.i.RamSel<=Interf_i.RamSel;
-			--ct_state<=ct; --pour débogage
-			--============================================================
-			
-			case  RunState is
-			when start =>
-				--Dcount<=0;
-				if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
-						RunState<=InitApp;
-				 end if;
-				 --Ram_busy<='0';
-				 Libr.O.MemBusy<='0';
-				 Libr.O.Instr_En<='0';
-				
-				adresse:=10;--DATAPTR;
-				
-				adresse_rd:=0;
-				timeout:=0;
-				--dcount<=0;
-				sram.O.we<='0';
-					sram.O.ena<='0';
-					sram.O.enb<='0';
-			-- synthesis translate_off 
-			if fopened='0' then 
-			file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE);
-        --while not endfile(c_file_handle) loop
-			--end if;
-		
-				--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
-				--report l.all;
-           -- writeline (f, l) ;
-				fopened:='1';
-			end if;
-			 -- synthesis translate_on
-			 when Fillmem =>
-					sram.O.we<='1';
-					sram.O.ena<='1';
-					sram.O.enb<='0';
-				if Libr.I.Ramsel='0' then 
-					
-					sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
-					sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
-					Libr.O.Instr_En<='0';
-					dcount:=dcount+1;
-					
-					if dcount=250 then
-						 bfill:=bfill+1;
-						 
-						 if bfill=4 then
-						  RunState<=WinCreate;
-						 else
-							RunState<=nextfill;
-						end if;
-					else
-						adresse:=adresse+1;
-						RunState<=Fillmem;
-					end if;
-			else -- attente de la libéraion de la mémoire
-			        timeout:=timeout+1;
-					  if timeout=100 then
-						RunState<=st_timeout;
-					  end if;
-							
-			end if;
-		when nextfill  =>   --prépare le prochain bloc mémoire qui sera rempli
-				adresse:=250*bfill+10;
-				
-				dcount:=0;
-				ct:=0;
-				RunState<=Fillmem;
-				Libr.O.Instr_En<='0';
-					sram.O.we<='1';
-					sram.O.ena<='1';
-					sram.O.enb<='0';
-		when InitApp =>
-				--code pour Init 
-				dlen:=1;
-				if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;"& integer'image(dlen) & " ;INIT1 " &  integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
-				
-				report l.all;
-            writeline (f, l) ;
-				-- synthesis translate_on
-				end if;
-				pMPI_Init(ct,Libr,Clk,SRam);
-				
-				adresse:=to_integer(unsigned(sram.O.addr_wr));
-				adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-				
-				--if Libr.InitOk='1' then 
-				if ct=0 then 
-					RunState<=GetRank;
-					-- synthesis translate_off 
-					write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " &  integer'image(Dlen) & ";" & image(MyRank) & ";  ended at  ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ;  
-					-- synthesis translate_on
-				end if;
-				
-		
-		
-		when GetRank =>
-		if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ;  
-				-- synthesis translate_on
-			end if;
-			pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
-			adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-			
-			
-			if ct=0 then
-				RunState<=FillMem;
-				-- synthesis translate_off
-				write (l,string'("Dlen;" & integer'image(dlen) & ";Rank2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ; 
-				-- synthesis translate_on
-			end if;
-			
-		
-		when Wincreate => --par défaut la fenêtre 0 est utilisée !
-		  case MyRank is
-		    when x"0"=>
-		      Mygroup.grp<=x"0002";-- rank 1
-		      MyGroup.nb<=2;
-		      destRank:=1;
-		      DestAdr:=X"043F";
-		      nb_rma:=1;
-		    when x"1" =>
-		      		      Mygroup.grp<=x"0000";-- rank 0
-		      		      destRank:=0;
-		      		      DestAdr:=X"043F";
-		    when x"2" =>
-		      		      Mygroup.grp<=x"0000";-- rank 
-		      		      destRank:=0;
-		      		      DestAdr:=X"044F";
-		    when x"3" =>
-		      		      Mygroup.grp<=x"0000";-- rank 
-		      		      destRank:=0;
-		      		      DestAdr:=X"045F";
-		    when others =>   --cas des processus spawn
-		      		      Mygroup.grp<=x"0000";-- rank 0
-		      		      destRank:=0;
-		 end case;
-          		 RunState<=WinPost;
-		when WinPost =>
-			if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ;  
-				-- synthesis translate_on
-			end if;
-			
-				pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin);
-			
-			if ct=0 then
-			  if spawn_on='1' then
-				RunState<=WinWait;
-				else
-				  RunState<=WinStart;
-				  end if;
-				-- synthesis translate_off
-				write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ; 
-				-- synthesis translate_on
-			end if;
-			
-		when WinStart =>
-			if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ;  
-				-- synthesis translate_on
-			end if;
-				pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);
-					adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					dcount:=ct;
-			
-			if ct=0 then
-				RunState<=PutData;
-				-- synthesis translate_off
-				write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ; 
-				-- synthesis translate_on
-			end if;
-			
-		
-		when putdata => --construire le packet pour le Put
-				
-					--dlen:=251; ---
-					if ct=0 then
-					-- synthesis translate_off 
-					write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ; 
-					-- synthesis translate_on
-					end if;
-					 
-					SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
-					--DestAdr:=X"033F";
-					pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
-					
-					adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					dcount:=ct;
-					
-					if ct=0 then
-						RunState<=GetData;
-					-- synthesis translate_off 
-					report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now));
-					write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ;
-					-- synthesis translate_on
-					end if;
-					
-				
-			when getdata =>   --positionnement du mot de longueur des données
-					--dlen:=251; --- 
-					if ct=0 then
-					-- synthesis translate_off 
-					write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ; 
-					-- synthesis translate_on
-					end if;
-					
-					SrcAdr:=X"006D";
-					DestAdr:=X"1400";
-					if unsigned(MyRank) = 0 then 
-				  	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
-					else
-					  
-						--pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win);
-					end if;
-					adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					dcount:=ct;
-					
-					if ct=0 then
-					  if unsigned(MyRank)/=0 then
-						RunState<=wincompleted;
-						else
-						  nb_rma:=nb_rma+1;
-						  if nb_rma=2 then 
-						    RunState<=wincompleted;
-						    nb_rma:=0;
-						   end if;
-						end if;
-						-- synthesis translate_off 
-						assert ct/=0 report "GET_END " & integer'image(destrank)
-								severity Warning ;
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-					report l.all;
-					
-					writeline (f, l) ; 
-						-- synthesis translate_on
-					end if;
-				
-				when WinCompleted =>
-				if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on 
-					end if;	
-					 pMPI_Win_Complete(ct,Libr,sram,MyWin );
-					 adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					if ct=0 then
-						RunState<=WinWait;	
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						-- synthesis translate_on
-						
-					end if;	  
-			when WinWait =>
-				if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on 
-					end if;	
-					 pMPI_Win_wait(ct,Libr,sram,MyWin );
-					 adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					if ct=0 then
-					  if Libr.I.Spawned='1' then
-						RunState<=Finalize;	
-						elsif spawn_on='1' then
-						  RunState<=Finalize;	
-						else
-						  RunState<=MpiSpawn;	
-						end if;
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						-- synthesis translate_on
-						
-					end if;	  
-							
-			when MpiSpawn =>
-				if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on 
-					end if;	
-					--(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;  
-
-						maxprocs:=2;
-					 pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes);
-					 adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					if ct=0 then
-					  if unsigned(MyRank)=0 then
-					      Spawn_on:='1';
-					       Mygroup.grp<=x"000C";-- rank 3,4
-		      		      destRank:=0;
-					      runstate<=WinPost;
-					    else
-          						RunState<=Finalize;	
-						end if;
-					
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						-- synthesis translate_on
-						
-					end if;	  			
-			when finalize =>
-					if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on
-					end if;	
-					 sram.O.we<='0';
-					sram.O.ena<='0';
-					sram.O.enb<='0';
-					if ct=0 then
-						RunState<=start;	
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						file_close(f);	
-						-- synthesis translate_on 
-					end if;	  
-		
-			when st_timeout =>
-			  
-					sram.O.we<='0';
-					sram.O.ena<='0';
-					sram.O.enb<='0';
-		
-			  RunState<=start;
-			end case;
-			ct_state<=ct; --pour débogage
-		end if;
-	end if;
-
-  end process pPutGet;	
-
-end a2;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/HT_5.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/HT_5.vhd	(revision 97)
+++ 	(revision )
@@ -1,493 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    12:04:21 04/22/2013 
--- Design Name: 
--- Module Name:    HT_process - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-library NocLib ;
-use std.textio.all;
-use NocLib.CoreTypes.all;
-use work.Packet_type.all;
-use work.MPI_RMA.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
-
-
-architecture A_Count of HT_process is
-
-  type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart,
-  putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout);
-	signal sram : typ_dpram;
-	signal MyGroup:mpi_group;
-	signal MyWin : mpi_win;
-	signal MyRank :std_logic_vector(3 downto 0);
-	signal intercomm,array_of_errcodes : natural;
-	signal ct_state:natural:=0;
-signal Libr : Core_io;  --regroupe tous les signaux IO de la bibliothèque
-signal RunState : typ_mae;
-component count_32 is
-port (clk,reset,upDn,load,start:in std_logic;
-loadval :in std_logic_vector(31 downto 0);
-outval : out std_logic_vector(31 downto 0));
-end component count_32;
-signal rescount,updn,load,start :std_logic:='0';
-signal loadval,outval :std_logic_vector(31 downto 0):=(others=>'0');
-
-begin
-
---MAE du PE
---=======================================================================
--- Interf<=Libr;
-
-
- pPutGet:process(clk,reset,en)
- 
-	constant DATAPTR : natural :=256;
-	variable nb_rma:natural range 0 to 15:=0;
-	variable bfill,destrank,pid,mport : natural range 0 to 15;
-	variable fsrc,ret : natural range 0 to 15:=0;
-	variable timeout,ct,dlen,dcount : natural range 0 to 255;
-	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
-	variable mywin : Mpi_win;
-	variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn 
-	variable comm : natural :=0;  
-	variable Spawn_on: std_logic:='0';
-	variable  adresse,adresse_rd :natural range 0 to 65536;
-	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
-
-	--=======================================================
-	--variables pour la création du fichier de résultats
-		-- synthesis translate_off 
-		type char_file is file of character;
-        file f: text;
-        variable status :file_open_status ;
-        variable char_count: integer range 0 to 65536 := 0;
-		  variable str: string (1 to 79) ;
-		  variable L: line; 
-		  variable fopened: std_logic:='0';
-		  
-		  constant simres : time :=1 ps; --simulation resolution
-		  constant realres : real :=1.0e-3; --ramener le temps en ns
-		  -- returns real value of time parameter using pure VHDL
-	     function rt(t : time) return real is
-	       begin
-		        return real(t/simres) * realres;
-	     end;
-		 -- synthesis translate_on
---======================================================
-	begin
-	--=== Partie combinatoire du process ===================================
-			
-	--=== Fin de la partie combinatoire du process ==========================	
-		
-		    
-           
-        --end loop;
-        
-	if (clk'event and clk='1') and en='1' then 
-			
-			
-		if reset='1' then
-					RunState<=start;
-					
-		else
-			--==========================================================
-			--affectation des entrées sorties mémoires
-			sram.i.data_out<=mem_I.data_out;
-			mem_o.addr_wr<=sram.O.addr_wr;
-			mem_o.addr_rd<=sram.O.addr_rd ; 
-			mem_o.we<=sram.O.we;
-			mem_o.ena<=sram.O.ena;
-			mem_o.enb<=sram.O.enb;
-			mem_o.data_in<=sram.O.data_in;
-			--affectation des entrées sorties MPI_HCL
-			Interf_o.Instr_EN<=Libr.O.instr_en;
-			Interf_o.Membusy<=Libr.O.MemBusy;
-			Interf_o.Instruction<=Libr.O.Instruction;
-			Libr.i.Instr_ack<=Interf_i.Instr_ack;
-			Libr.i.InitOk<=Interf_i.InitOk;
-			Libr.i.Hold_Req<=Interf_i.Hold_req;
-			Libr.I.Spawned<=Interf_i.Spawned;
-			--Libr.i.Hold_Ack<=Interf_i.Hold_Ack;
-			Libr.i.RamSel<=Interf_i.RamSel;
-			--ct_state<=ct; --pour débogage
-			--============================================================
-			
-			case  RunState is
-			when start =>
-				--Dcount<=0;
-				if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
-						RunState<=InitApp;
-				 end if;
-				 --Ram_busy<='0';
-				 Libr.O.MemBusy<='0';
-				 Libr.O.Instr_En<='0';
-				
-				adresse:=10;--DATAPTR;
-				
-				adresse_rd:=0;
-				timeout:=0;
-				--dcount<=0;
-				sram.O.we<='0';
-					sram.O.ena<='0';
-					sram.O.enb<='0';
-			-- synthesis translate_off 
-			if fopened='0' then 
-			file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE);
-        --while not endfile(c_file_handle) loop
-			--end if;
-		
-				--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
-				--report l.all;
-           -- writeline (f, l) ;
-				fopened:='1';
-			end if;
-			 -- synthesis translate_on
-			 when ReadData1 =>
-				readmem(ct,libr,sram,x"0010",V);
-				if ct=0 then 
-				  reset_count<=v(0);
-				  UpDn<=v(1);
-				  Load<=v(2);
-					RunState<=ReadData2
-				end if;
-			when readData2 =>
-					readmem(ct,libr,sram,x"0011",loadval);
-					if ct=0  then
-						  RunState<=WinCreate;
-						 
-						end if;
-					
-		when InitApp =>
-				--code pour Init 
-				dlen:=1;
-				if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;"& integer'image(dlen) & " ;INIT1 " &  integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
-				
-				report l.all;
-            writeline (f, l) ;
-				-- synthesis translate_on
-				end if;
-				pMPI_Init(ct,Libr,Clk,SRam);
-				
-				adresse:=to_integer(unsigned(sram.O.addr_wr));
-				adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-				
-				--if Libr.InitOk='1' then 
-				if ct=0 then 
-					RunState<=GetRank;
-					-- synthesis translate_off 
-					write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " &  integer'image(Dlen) & ";" & image(MyRank) & ";  ended at  ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ;  
-					-- synthesis translate_on
-				end if;
-				
-		
-		
-		when GetRank =>
-		if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ;  
-				-- synthesis translate_on
-			end if;
-			pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
-			adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-			
-			
-			if ct=0 then
-				RunState<=FillMem;
-				-- synthesis translate_off
-				write (l,string'("Dlen;" & integer'image(dlen) & ";Rank2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ; 
-				-- synthesis translate_on
-			end if;
-			
-		
-		when Wincreate => --par défaut la fenêtre 0 est utilisée !
-		  case MyRank is
-		    when x"0"=>
-		      Mygroup.grp<=x"0002";-- rank 1
-		      MyGroup.nb<=2;
-		      destRank:=1;
-		      DestAdr:=X"043F";
-		      nb_rma:=1;
-		    when x"1" =>
-		      		      Mygroup.grp<=x"0000";-- rank 0
-		      		      destRank:=0;
-		      		      DestAdr:=X"043F";
-		    when x"2" =>
-		      		      Mygroup.grp<=x"0000";-- rank 
-		      		      destRank:=0;
-		      		      DestAdr:=X"044F";
-		    when x"3" =>
-		      		      Mygroup.grp<=x"0000";-- rank 
-		      		      destRank:=0;
-		      		      DestAdr:=X"045F";
-		    when others =>   --cas des processus spawn
-		      		      Mygroup.grp<=x"0000";-- rank 0
-		      		      destRank:=0;
-		 end case;
-          		 RunState<=WinPost;
-		when WinPost =>
-			if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ;  
-				-- synthesis translate_on
-			end if;
-			
-				pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin);
-			
-			if ct=0 then
-			  if spawn_on='1' then
-				RunState<=WinWait;
-				else
-				  RunState<=WinStart;
-				  end if;
-				-- synthesis translate_off
-				write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ; 
-				-- synthesis translate_on
-			end if;
-			
-		when WinStart =>
-			if ct=0 then
-				-- synthesis translate_off 
-				write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " &  integer'image(Dlen) & "; ; started  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ;  
-				-- synthesis translate_on
-			end if;
-				pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);
-					adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					dcount:=ct;
-			
-			if ct=0 then
-				RunState<=PutData;
-				-- synthesis translate_off
-				write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " &  integer'image(Dlen) & ";" & image(MyRank) & "; ended at  ; " & real'image(rt(now))));
-				report l.all;
-            writeline (f, l) ; 
-				-- synthesis translate_on
-			end if;
-			
-		
-		when putdata => --construire le packet pour le Put
-				
-					--dlen:=251; ---
-					if ct=0 then
-					-- synthesis translate_off 
-					write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ; 
-					-- synthesis translate_on
-					end if;
-					 
-					SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
-					--DestAdr:=X"033F";
-					pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
-					
-					adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					dcount:=ct;
-					
-					if ct=0 then
-						RunState<=GetData;
-					-- synthesis translate_off 
-					report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now));
-					write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ;
-					-- synthesis translate_on
-					end if;
-					
-				
-			when getdata =>   --positionnement du mot de longueur des données
-					--dlen:=251; --- 
-					if ct=0 then
-					-- synthesis translate_off 
-					write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
-					report l.all;
-					writeline (f, l) ; 
-					-- synthesis translate_on
-					end if;
-					
-					SrcAdr:=X"006D";
-					DestAdr:=X"1400";
-					if unsigned(MyRank) = 0 then 
-				  	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
-					else
-					  
-						--pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win);
-					end if;
-					adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					dcount:=ct;
-					
-					if ct=0 then
-					  if unsigned(MyRank)/=0 then
-						RunState<=wincompleted;
-						else
-						  nb_rma:=nb_rma+1;
-						  if nb_rma=2 then 
-						    RunState<=wincompleted;
-						    nb_rma:=0;
-						   end if;
-						end if;
-						-- synthesis translate_off 
-						assert ct/=0 report "GET_END " & integer'image(destrank)
-								severity Warning ;
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-					report l.all;
-					
-					writeline (f, l) ; 
-						-- synthesis translate_on
-					end if;
-				
-				when WinCompleted =>
-				if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on 
-					end if;	
-					 pMPI_Win_Complete(ct,Libr,sram,MyWin );
-					 adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					if ct=0 then
-						RunState<=WinWait;	
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						-- synthesis translate_on
-						
-					end if;	  
-			when WinWait =>
-				if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on 
-					end if;	
-					 pMPI_Win_wait(ct,Libr,sram,MyWin );
-					 adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					if ct=0 then
-					  if Libr.I.Spawned='1' then
-						RunState<=Finalize;	
-						elsif spawn_on='1' then
-						  RunState<=Finalize;	
-						else
-						  RunState<=MpiSpawn;	
-						end if;
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						-- synthesis translate_on
-						
-					end if;	  
-							
-			when MpiSpawn =>
-				if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on 
-					end if;	
-					--(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;  
-
-						maxprocs:=2;
-					 pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes);
-					 adresse:=to_integer(unsigned(sram.O.addr_wr));
-					adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
-					
-					if ct=0 then
-					  if unsigned(MyRank)=0 then
-					      Spawn_on:='1';
-					       Mygroup.grp<=x"000C";-- rank 3,4
-		      		      destRank:=0;
-					      runstate<=WinPost;
-					    else
-          						RunState<=Finalize;	
-						end if;
-					
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						-- synthesis translate_on
-						
-					end if;	  			
-			when finalize =>
-					if ct=0 then
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ; 
-						-- synthesis translate_on
-					end if;	
-					 sram.O.we<='0';
-					sram.O.ena<='0';
-					sram.O.enb<='0';
-					if ct=0 then
-						RunState<=start;	
-						-- synthesis translate_off 
-						write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
-						report l.all;
-						writeline (f, l) ;
-						file_close(f);	
-						-- synthesis translate_on 
-					end if;	  
-		
-			when st_timeout =>
-			  
-					sram.O.we<='0';
-					sram.O.ena<='0';
-					sram.O.enb<='0';
-		
-			  RunState<=start;
-			end case;
-			ct_state<=ct; --pour débogage
-		end if;
-	end if;
-
-  end process pPutGet;	
-
-end a_count;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MPICORETEST.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MPICORETEST.vhd	(revision 97)
+++ 	(revision )
@@ -1,702 +1,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   01:27:32 04/20/2012
--- Design Name:   
--- Module Name:   C:/Core MPI/CORE_MPI/MPICORETEST.vhd
--- Project Name:  MPI_CORE_COMPONENTS
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: MPI_NOC
--- 
--- Dependencies:
--- 
--- Revision: 11 Juillet 2012
--- Revision 0.01 - File Created
--- Additional Comments:Permet de tester le composant MPI
--- en simulant deux PE qui s'échangent des données.
--- Notes: 
--- 
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-library NocLib ;
---use IEEE.STD_LOGIC_ARITH.ALL;
---use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use NocLib.CoreTypes.all;
-use work.Packet_type.all;
-use work.MPI_RMA.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-USE ieee.numeric_std.ALL;
- 
-ENTITY MPICORETEST IS
---port (clkm : in std_logic;
---reset : in std_logic;
---result : out std_logic_vector(Word-1 downto 0));
-END MPICORETEST;
- 
-ARCHITECTURE behavior OF MPICORETEST IS 
---constant WORD :positive:=8;
-constant MEMSIZE:positive:=65535;
- -- Components declaration
- COMPONENT RAM_v
-  generic (width : positive;size :positive);
-	PORT(
-		clka : IN std_logic;
-		clkb : IN std_logic;
-		wea : IN std_logic;
-		ena : IN std_logic;
-		enb : IN std_logic;
-		addra : IN std_logic_vector;
-		addrb : IN std_logic_vector;
-		dia : IN std_logic_vector;          
-		dob : OUT std_logic_vector
-		);
-	END COMPONENT;
-
-	
-    -- Component Declaration for the Unit Under Test (UUT)
- 
-    COMPONENT MPI_NOC
-	 generic (NPROC : positive:=2);
-    PORT(
-         MPI_Node_in : IN  Ar_MPIPort_in(1 to 2);
-         MPI_Node_Out : OUT  Ar_MPIPort_out(1 to 2)
-        );
-    END COMPONENT;
-   
-	constant clk_period : time := 10 ns;
-
---===================signaux pour l'horloge ==============================
-signal reset,clkm : std_logic := '0';
---========================================================================
-	   --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0');
-	signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0';
-	signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic;
-	signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
-	signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0');
-	signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
-	signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0);
-	signal PE_Instr_en : std_logic:='0';
-	signal sram : typ_dpram;
-   signal pe_hold_ack,pe_hold_req : std_logic;
-	--signal pe_putadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour Put
-	--signal pe_getadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour get
-	signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée
-	signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO
-	signal Lib_Init : std_logic; -- l'initialisation est terminée
-	
-	--données du programme PE
-	signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0);
-	signal dpid,dpid_i : natural range 0 to 15:=1;
-	--Inputs
-   signal MPI_Node_in : Ar_MPIPort_in(1 to 2) ;
--- Port details
---			instruction :   STD_LOGIC_VECTOR (Word -1 downto 0);
---           instruction_en :  STD_LOGIC;
---           packet_ack : std_logic;
---           ram_data_in :  STD_LOGIC_VECTOR (Word-1 downto 0);
---			  clk :  STD_LOGIC;
---           reset :  STD_LOGIC;
- 	--Outputs
-   signal MPI_Node_Out : Ar_MPIPort_out(1 to 2);
---	détails des champs de Typ_MPIPORT_Out		  
---          
---			  
---         ram_we :  STD_LOGIC;
---			  ram_en :  STD_LOGIC;
---			  packet_received : STD_LOGIC;
---			  barrier_completed : STD_LOGIC;
---         instruction_fifo_full : STD_LOGIC;
---			  PushOut :  STD_LOGIC_VECTOR (WORD-1 downto 0);
---			  ram_data_out : STD_LOGIC_VECTOR (WORD-1 downto 0);
---           ram_address :  STD_LOGIC_VECTOR (ADRLEN-1 downto 0); 
---           		  
---end record;
-   -- 
-   -- a
- 
-   
- --signaux pour la gestion de la MAE
- type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, 
- putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout);
-signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
-signal count,count_i : natural range 0 to 15:=0;
-
---signal adresse,adresse_rd :natural range 0 to 65536;
-
-		signal etPutGet : typ_mae;
-		signal Ram_busy :std_logic:='0';
-		
-BEGIN
- 
-	-- Instantiate the Unit Under Test (UUT)
-   uut: MPI_NOC GENERIC MAP (NPROC=>2)
-		PORT MAP (
-          MPI_Node_in => MPI_Node_in,
-          MPI_Node_Out => MPI_Node_Out
-        );
-Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN)
-	PORT MAP(
-		clka =>clkm,
-		clkb => clkm,
-		wea => ram_we,
-		ena => ram_ena,
-		enb => ram_enb,
-		addra => ram_addra,
-		addrb =>ram_addrb,
-		dia => ram_din,
-		dob => ram_do 
-	);
-	
-	--MUX de la RAM
-                             	
-  ram_addrb <= MPI_Node_out(1).ram_address_rd WHEN ramsel ='1' ELSE 
-            pe_ram_addrb; 
- ram_addra <= MPI_Node_out(1).ram_address_wr WHEN ramsel ='1' ELSE 
-            pe_ram_addra; 
-
-
-ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE 
-            pe_ram_ena; 
-ram_enb <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE 
-            pe_ram_enb; 
-ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE 
-            pe_ram_ena; 
-		
-ram_we<= MPI_Node_out(1).ram_we WHEN ramsel ='1' ELSE 
-            pe_ram_we; 
-
-ram_din <= MPI_Node_out(1).ram_data_in WHEN ramsel ='1' ELSE 
-            pe_ram_din;
-				
-
-MPI_Node_in(1).ram_data_out<=ram_do when ramsel='1' else (others=>'Z');
-pe_ram_do<=ram_do when ramsel='0' else (others=>'Z');
-
-
-pe_hold_req<=MPI_Node_out(1).hold_req;
-MPI_Node_in(1).hold_ack<=pe_hold_ack;
-MPI_Node_in(1).reset<=reset;	
-MPI_Node_in(1).clk<=clkm;
-MPI_Node_in(1).instruction_en<=PE_instr_en;
-MPI_Node_in(1).instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8));
-
-Lib_Instr_ack<=MPI_Node_out(1).Pushout(0); --l'instruction a été copié
-Lib_init<=MPI_Node_out(1).Pushout(4); -- Initialized
---=============================================================
-   -- Clock process definitions
---=============================================================
-   clk_process :process
-   begin
-		clkm <= '0' ;
-		wait for 10 ns;--clk_period/2;
-		clkm <= '1' ;
-		wait for 10 ns;--clk_period/2;
-   end process;
- stim_proc: process 
-   begin		
-      -- hold reset state for 100 ns.
-      reset<='0';
-		wait for 1 ns;	
-		reset<='1';
-      wait for clk_period*10;
-		reset<='0';
-		wait;
-     
-	
-	end process;
---================================================================
-dpid<=dpid_i;
- pPutGet:process(clkm)
-	
-	variable bfill,destrank,pid,mport : natural range 0 to 15;
-	variable fsrc,ret : natural range 0 to 15:=0;
-	variable timeout,dlen,ct : natural range 0 to 255;
-	variable adrToset : std_logic_vector(ADRLEN-1 downto 0);
-	variable iack : std_logic:='0';
-	variable  adresse,adresse_rd :natural range 0 to 65536;
-	
-	begin
-	
-	if (clkm'event and clkm='1') then 
-		if reset='1' then
-					etputget<=start;
-					
-					
-					dcount<=0;
-			
-		else
-	
-			case  etputget is
-			when start =>
-				if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
-						etputget<=Fillmem;
-				 end if;
-				 Ram_busy<='0';
-				 PE_Instr_En<='0';
-				iack:='0';
-				adresse:=256;
-				adresse_rd:=0;
-				timeout:=0;
-				dcount<=0;
-			 when Fillmem =>
-				if mpi_node_out(1).hold_req='0' then 
-					
-					
-					
-					PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
-					PE_Instr_En<='0';
-					dcount<=dcount+1;
-					
-					if dcount=50 then
-						 bfill:=bfill+1;
-						 
-						 if bfill=4 then
-						  etputget<=InitApp;
-						 else
-							etputget<=nextfill;
-						end if;
-					else
-						adresse:=adresse+1;
-						etputget<=Fillmem;
-					end if;
-			else -- attente de la libéraion de la mémoire
-			        timeout:=timeout+1;
-					  if timeout=100 then
-						etputget<=st_timeout;
-					  end if;
-							
-			end if;
-		when nextfill  =>   --prépare le prochain bloc mémoire qui sera rempli
-				adresse:=100*bfill;
-				dcount<=0;
-				etputget<=Fillmem;
-				PE_Instr_En<='0';
-		when InitApp =>
-				--code pour Init ici
-				--mettre mpi_init à l'adresse mpi 
-				
-				PE_Ram_din<=MPI_INIT & x"0" ;
-				adresse:=core_init_adr;
-				
-				PE_Instr_En<='0';
-				fsrc:=1;
-				adrToSet:=std_logic_vector(to_unsigned(core_init_adr,ADRLEN));
-				if ret/=fsrc then
-				dcount<=0;
-					etputget<=writeptr;
-					adresse:=core_base_adr+2;
-					PE_Instr_En<='0';
-				else
-				if Lib_instr_ack='1' then  -- attente de la prise en compte de l'instruction
-					etputget<=InitCompleted;
-					PE_instr_en<='0';
-				
-				else
-					PE_Instr_en<='1';
-				end if;
-				   
-				end if;
-		
-		when writeptr =>
-				PE_Instr_En<='0';
-				if PE_Hold_req = '0' then --s'assurer que le bus est disponible
-					
-					if dcount=0 then 
-						PE_RAM_Din<=AdrToSet(Word-1 downto 0);
-						dcount <=dcount+1;
-						--adresse:=adresse+1; --prépare la prochaine écriture
-					elsif dcount=1 then
-						dcount <=dcount+1;
-						adresse:=adresse+1; --prépare la prochaine écriture
-						PE_RAM_Din<=AdrToSet(15 downto 8);
-					elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						ret:=fsrc;
-						dcount<=0;
-						timeout:=0;
-						
-								if fsrc=1 then
-								etputget <= InitApp;
-								elsif fsrc=2 then
-								etputget <= putdata;
-								elsif fsrc=3 then
-								etputget <= getdata;
-								else
-								etputget <= start;
-								end if;
-							
-					end if;
-					
-				end if;
-		When InstrCopy =>
-				if Lib_instr_ack='1' then
-					etputget<=Writeptr;
-					PE_instr_en<='0';
-					iack:='1';
-					
-				else
-					PE_Instr_en<='1';
-				end if;
-		
-		when InitCompleted =>
-				
-				if Lib_Init='1' then
-					etputget<=putdata;
-					PE_Instr_En<='0';
-				else
-					PE_Instr_En<='0';
-				end if;
-		when putdata => --construire le packet pour le Put
-				DestRank:=1;
-				adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank;
-				
-				PE_Instr_En<='0';
-				timeout:=0;
-				dcount<=0;
-				fsrc:=2;
-				adrToSet:=std_logic_vector(to_unsigned(core_put_adr,ADRLEN));
-				if ret/=fsrc then
-				  adresse:=core_base_adr+2;
-					etputget<=writeptr;
-					ret:=0;
-				else
-					if Lib_instr_ack/='1' then 
-						etputget<= putdata2;
-					end if;
-				end if;
-				
-		when putdata2 =>
-		
-			if ramsel = '0' then  --si le PE a accès à la RAM
-					dlen:=to_integer(unsigned(datalen));
-					pMPI_put(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct);
-					adresse:=to_integer(unsigned(sram.addr_wr));
-					PE_ram_din<=sram.data_in;
-					dcount<=ct;
-					if dcount<=6 then
---						   
---							PE_Instr_En<='0';
---							if dcount=0 then 
---							adresse:=core_put_adr;
---							PE_Ram_din<=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4));
---							elsif dcount=1 then 
---							adresse:=core_put_adr+dcount;
---							PE_Ram_din<=Datalen ;
---							elsif dcount=2 then
---							adresse:=core_put_adr+dcount;
---							PE_Ram_din<=SrcAdr1 ;
---							elsif dcount=3 then
---							adresse:=core_put_adr+dcount;
---							PE_Ram_din<=SrcAdr0 ;
---							elsif dcount=4 then
---							adresse:=core_put_adr+dcount;
---							PE_Ram_din<=DestAdr1 ;
---							elsif dcount=5 then
---							adresse:=core_put_adr+dcount;
---							PE_Ram_din<=DestAdr0 ;
-							elsif dcount=7 then  --juste après la valeur 6 en fait
---							adresse:=core_base_adr+1;
---							adresse_rd:=core_base_adr;
---							PE_Ram_din<=x"01"; --instruction pulse enable;
-							PE_Instr_En<='1';
---							
-							end if;
---						dcount<=dcount+1;
---					end if;
-			elsif PE_instr_En='0' then
-					timeout:=timeout+1;
-					if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire
-						ram_busy<='1';
-						timeout:=0;
-						PE_Instr_En<='0';
-					end if;
-			end if;
-				if dcount >=6 then
-						Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI
-						if Lib_instr_ack='1' then -- Instruction ack
-						  PE_Instr_En<='0'; 
-							if Ramsel='0' then
-								adresse:=core_base_adr+1;
-								PE_Ram_din<=x"00"; --ramener le IPulse à 0;
-								Ram_busy<='0';
-								etPutGet<=putcompleted;
-							else
-								
-								Ram_busy<='1';  --force la prise du bus
-							end if;
-						else
-						
-						  timeout:=timeout+1; 
-						  if timeout=150 then 
-								etputget<=st_timeout;
-							end if;
-						end if;
-				end if;
-			
-			
-			when putcompleted =>
-				adresse_rd:=core_put_adr+6;
-				if PE_Ram_do(0)='1' then  --Put completed
-					etPutGet<=GetData;
-				end if;
-				PE_Instr_En<='0';
-			when getdata =>   --positionnement du mot de longueur des données
-			   
-				DestRank:=1;
-				timeout:=0;
-				dcount<=0;
-					fsrc:=3;
-				adrToSet:=std_logic_vector(to_unsigned(core_get_adr,ADRLEN));
-				if ret/=fsrc then
-					adresse:=core_base_adr+2;
-					etputget<=writeptr;
-					ret:=0;
-				else
-					adresse:=core_get_adr;
-					etputget<= getdata2;
-				end if;
-			    PE_Instr_En<='0';
-				when getdata2 =>
-					
-					if ramsel='0' then
-						
-						pMPI_get(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct);
-					   adresse:=to_integer(unsigned(sram.addr_wr));
-						PE_ram_din<=sram.data_in;
-						dcount<=ct;
-						if dcount<=6 then
-							
---							if dcount<=0 then 
---								adresse:=core_get_adr;
---							PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(Dpid,4));
---							elsif dcount=1 then
---							adresse:=core_get_adr+dcount;
---							PE_Ram_din<=Datalen ;
---							elsif dcount=2 then
---							adresse:=core_get_adr+dcount;
---							PE_Ram_din<=SrcAdr1 ;
---							elsif dcount=3 then
---							adresse:=core_get_adr+dcount;
---							PE_Ram_din<=SrcAdr0 ;
---							elsif dcount=4 then
---							adresse:=core_get_adr+dcount;
---							PE_Ram_din<=DestAdr1 ;
---							elsif dcount=5 then
---							adresse:=core_get_adr+dcount;
---							PE_Ram_din<=DestAdr0 ;
-							
-							elsif dcount=7 then
---							adresse:=core_base_adr+1;
-							adresse_rd:=core_base_adr;
-							PE_Instr_En<='1';
---							PE_Ram_din<=x"01"; --instruction pulse enable;
-							timeout:=0;
-							end if;
---							dcount<=dcount+1;
---					end if;
-					elsif  PE_Instr_En='0'then
-						timeout:=timeout+1;
-						if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire
-							ram_busy<='1';
-							timeout:=0;
-							PE_Instr_En<='0';
-						end if;
-					end if;
-			
-				  if dcount >=6 then
-						  Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI
-								if Lib_instr_ack='1' then -- Instruction ack
-								  PE_Instr_En<='0'; 
-									if Ramsel='0' then
-										adresse:=core_base_adr+1;
-										PE_Ram_din<=x"00"; --ramener le IPulse à 0;
-										Ram_busy<='0';
-										etPutGet<=getcompleted;
-									else
-										
-										Ram_busy<='1';  --force la prise du bus
-									end if;
-								else
-								
-									  timeout:=timeout+1; 
-									  if timeout=150 then 
-											etputget<=st_timeout;
-										end if;
-								end if;
-								
-								
-						end if;
-						
-				
-					
-				when getcompleted =>
-				adresse_rd:=core_get_adr+6;
-				PE_Instr_En<='0';
-				if PE_Ram_do(0)='1' then  --Put completed
-				   if Ramsel='0' then
-					adresse:=core_base_adr+1;
-					PE_Ram_din<=x"00"; --ramener le IPulse à 0;
-					etPutGet<=Terminate;
-					else
-						timeout:=timeout+1;
-					end if;
-				end if;	
-					
-						
-			when terminate =>
-			
-		
-					etputget<=start;
-					
-			when st_timeout =>
-			  
-			  --if ram_busy='1' then
-				 etputget<=start;
-			  --end if
-		
-			  etputget<=start;
-			end case;
-			pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,ADRLEN));
-			pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,ADRLEN));
-		end if;   --reset='1'
-	end if;
-  end process pPutGet;	
-
-majPutGet:process (etputget)
-
-	begin
-			case  etputget is
-			when start =>
-			
-				   PE_Ram_we<='0';
-					PE_Ram_ena<='0';
-					PE_Ram_enb<='0';
-					--PE_Instr_En<='0';
-
-		 when fillmem =>
-				   PE_Ram_we<='1';
-					PE_Ram_ena<='1';
-					
-					PE_Ram_enb<='0';
-					--PE_Instr_En<='0';
-		 when nextfill =>
-					PE_Ram_we<='1';
-					PE_Ram_ena<='1';
-					PE_Ram_enb<='0';
-					--PE_Instr_En<='0';
-	    when InitApp =>
-				   PE_Ram_we<='1';
-					PE_Ram_ena<='1';
-					PE_Ram_enb<='0';
-					--PE_Instr_En<='0';
-		 when Initcompleted =>
-			      --PE_Instr_En<='1';
-		 when writeptr =>
-					PE_Ram_we  <='1';   --écriture dans la RAM
-					PE_Ram_ena <='1';
-					
-					PE_Ram_enb <='0';
-			--		dcount<=dcount+1;
-					
-					--PE_Instr_En<='0';
-		when InstrCopy =>  --instruction copy
-				   PE_Ram_we<='0';
-					PE_Ram_ena<='0';
-					PE_Ram_enb<='0';
-
-		
-		when putdata =>   --positionnement du mot de longueur des données
-				--dcount<=0;
-				srcadr0<=X"00";
-				srcadr1<=X"01";
-				destadr0<=X"00";
-				destadr1<=X"02";
-				   PE_Ram_we<='0';
-					PE_Ram_ena<='0';
-					   --lecture du n° de port de destination
-					PE_Ram_enb<='1';
-				datalen<=std_logic_vector(to_unsigned(50,8));
-				dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible
-				--PE_Instr_En<='0';
-			when putdata2 =>
-					PE_Ram_we  <='1';   --écriture dans la RAM
-					PE_Ram_ena <='1';
-					
-					PE_Ram_enb <='0';
-			--		dcount<=dcount+1;
-					if dcount>=5 then
-					--PE_Instr_En<='1';
-					else
-					--PE_Instr_En<='0';
-					end if;
-			when putcompleted =>			
-					PE_Ram_we  <='1';
-					PE_Ram_ena <='1';
-					  -- lecture du résultat
-					PE_Ram_enb  <='1';
-					--PE_Instr_En<='1';
-			when getdata =>
-				--dcount<=0;
-				srcadr0<=X"00";
-				srcadr1<=X"02";
-				destadr0<=X"00";
-				destadr1<=X"03";
-				datalen<=std_logic_vector(to_unsigned(50,8));
-				--PE_Instr_En<='0';	
-			when getdata2 =>
-				   PE_Ram_we  <='1';   --écriture dans la RAM
-					PE_Ram_ena <='1';
-					
-					PE_Ram_enb <='0';
-				--dcount<=dcount+1;
-				   if dcount=5 then
-						--PE_Instr_En<='1';
-					else
-						--PE_Instr_En<='0';
-					end if;
-			when getcompleted =>				
-					PE_Ram_we  <='1';
-					PE_Ram_ena <='1';
-					  -- lecture du résultat
-					PE_Ram_enb  <='1';
-					--PE_Instr_En<='1';
-			when terminate =>
-			
-				   PE_Ram_we<='0';
-					PE_Ram_ena<='0';
-					PE_Ram_enb<='0';
-					--PE_Instr_En<='0';
-			
-			when st_timeout =>
-				  PE_Ram_we<='0';
-					PE_Ram_ena<='0';
-					PE_Ram_enb<='0';
-					--PE_Instr_En<='0';
-			  
-			end case;
-		
-end process majPutGet ;  
-
- hold:process (pe_hold_req,clkm,reset)
- begin
- if rising_edge(clkm) then
-	if reset='1' then
-		pe_hold_ack<='0';
-	else
-		if pe_hold_req='1' then
-			ramsel<=not(ram_busy);
-			pe_hold_ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération
-		else
-			pe_hold_ack<='0';
-			ramsel<='0';
-		end if;
-	end if;
- end if;
- end process hold;
-END;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_CORE_SCHEDULER.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_CORE_SCHEDULER.vhd	(revision 97)
+++ 	(revision )
@@ -1,135 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    12:16:03 06/13/2011 
--- Design Name: 
--- Module Name:    MPI_CORE_SCHEDULER - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity MPI_CORE_SCHEDULER is
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           priority_rotation : in  STD_LOGIC;
-           instruction_fifo_empty : in  STD_LOGIC;
-           instruction_fifo_data : in  STD_LOGIC_VECTOR (7 downto 0);
-           instruction_available : out  STD_LOGIC;
-			  
-			  get_request_fifo_data : in  STD_LOGIC_VECTOR (7 downto 0);
-			  get_request_fifo_empty : in  STD_LOGIC;
-           instruction_fifo_rd_en : out  STD_LOGIC;
-           get_request_fifo_rd_en : out  STD_LOGIC;
-           			  
-           fifo_selected : out  STD_LOGIC;
-           fifo_empty : out  STD_LOGIC;
-           fifo_rd_en : in  STD_LOGIC;
-           data_out : out  STD_LOGIC_VECTOR (7 downto 0)
-			  );
-end MPI_CORE_SCHEDULER;
-
-architecture Behavioral of MPI_CORE_SCHEDULER is
-
-signal sel_signal : std_logic;
--- declaration des composants du scheduler
-COMPONENT CDEMUX1
-	PORT(
-		di : IN std_logic;
-		sel : IN std_logic;          
-		do1 : OUT std_logic;
-		do2 : OUT std_logic
-		);
-	END COMPONENT;
-	
-COMPONENT CMUXP1
-	PORT(
-		di1 : IN std_logic;
-		di2 : IN std_logic;
-		sel : IN std_logic;          
-		do : OUT std_logic
-		);
-	END COMPONENT;
-
-COMPONENT CMUX8
-	PORT(
-		di1 : IN std_logic_vector(7 downto 0);
-		di2 : IN std_logic_vector(7 downto 0);
-		sel : IN std_logic;          
-		do : OUT std_logic_vector(7 downto 0)
-		);
-	END COMPONENT;
-	
-COMPONENT round_robbin_machine
-	PORT(
-		get_request_fifo_empty : IN std_logic;
-		instruction_fifo_empty : IN std_logic;
-		priority_rotation : IN std_logic;
-		clk : IN std_logic;
-		reset : IN std_logic;          
-		fifo_selected : OUT std_logic;
-		instruction_available : OUT std_logic;
-		mux_sel : OUT std_logic
-		);
-END COMPONENT;
-begin
--- instances des composants
-
-
-mpi_core_rr_machine: round_robbin_machine PORT MAP(
-		get_request_fifo_empty => get_request_fifo_empty,
-		instruction_fifo_empty => instruction_fifo_empty,
-		priority_rotation => priority_rotation ,
-		clk => clk,
-		fifo_selected => fifo_selected,
-		instruction_available => instruction_available ,
-		reset => reset,
-		mux_sel => sel_signal
-	);
-
-
-Fifo_empty_MUX: CMUXP1 PORT MAP(
-		di1 => instruction_fifo_empty ,
-		di2 => get_request_fifo_empty,
-		do => fifo_empty,
-		sel => sel_signal 
-	);
-	
-	
-
-rd_en_demux: CDEMUX1 PORT MAP(
-		di => fifo_rd_en ,
-		sel => sel_signal,
-		do1 => instruction_fifo_rd_en,
-		do2 => get_request_fifo_rd_en
-	);
-	
-data_MUX8: CMUX8 PORT MAP(
-		di1 => instruction_fifo_data ,
-		di2 => get_request_fifo_data,
-		sel => sel_signal,
-		do => data_out
-	);
-
-
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_NOC.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_NOC.vhd	(revision 97)
+++ 	(revision )
@@ -1,172 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    20:05:07 11/19/2011 
--- Design Name: 
--- Module Name:    MPI_NOC - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library NocLib ;
-
-use NocLib.CoreTypes.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity MPI_NOC is
-generic (NPROC : positive:=4);
- port(
- 
- MPI_Node_in : in Ar_MPIPort_in(1 to NPROC);
- MPI_Node_Out : out Ar_MPIPort_out(1 to NPROC)
- );
-end MPI_NOC;
-
-architecture structural of MPI_NOC is
--- Declare signals for interconnections
- 
---constant NPROC : positive :=8 ;
-   --Inputs
-   signal noc_portOut :typ_portio(1 to NPROC);
-   signal noc_portIn  :typ_portio(1 to NPROC);
-	   
-   signal noc_fifo_in_full :  std_logic_vector(NPROC downto 1):= (others => '0');
-   signal noc_data_available :   std_logic_vector(NPROC downto 1):= (others => '0');
-   signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0');
-	signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0');
-	signal noc_cmd_in_en : std_logic_vector(NPROC downto 1) := (others => '0');
-   signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0');
-  -- signal noc_clk : std_logic := '0';
-   --signal noc_reset : std_logic := '0';
-	
--- Declare components
-COMPONENT SWITCH_GEN
-	 GENERIC (number_of_ports : positive := NPROC);
-    PORT(
-         Port_in : IN  typ_PortIO(1 to number_of_ports);
-         Port_out : OUT    typ_PortIO(1 to number_of_ports);
-         data_in_en : IN  std_logic_vector(NPROC downto 1);
-			cmd_in_en : IN  std_logic_vector(NPROC downto 1);
-         data_out_en : IN  std_logic_vector(NPROC downto 1);
-         fifo_in_full : OUT  std_logic_vector(NPROC downto 1);
-         fifo_in_empty : OUT  std_logic_vector(NPROC downto 1);
-         data_available : OUT  std_logic_vector(NPROC downto 1);
-         clk : IN  std_logic;
-         reset : IN  std_logic
-        );
-    END COMPONENT;
-	COMPONENT CORE_MPI is
-    Port ( instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           instruction_en : in  STD_LOGIC;
-           
-           barrier_completed : out  STD_LOGIC;
-           packet_received : out  STD_LOGIC;
-			  packet_ack : in std_logic;
-           PushOut : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           ram_we : out  STD_LOGIC;
-			  hold_req       : out STD_Logic;  --requete vers application
-			  hold_ack       : in  STD_Logic;  --autorisation par l'application
-           ram_address_rd : out  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-			  ram_address_wr : out  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           ram_data_out : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  ram_data_in : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           switch_port_in_wr_en : out  STD_LOGIC;   -- OK (au switch) pour lire les données 
-           switch_port_in_empty : in STD_LOGIC;
-			  switch_port_in_cmd_en : out STD_LOGIC;
-			  switch_port_in_full : in  STD_LOGIC;  -- port d'entréendu switch saturé
-           switch_port_in_data : out  STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée
-           switch_port_out_rd_en : out  STD_LOGIC;    -- OK (au switch) pour écrire les données
-           switch_port_out_data_vailaible : in  STD_LOGIC; -- Donnée disponible à la sortie (du switch)
-			  clk : in  STD_LOGIC;
-			  clkout : out std_logic;
-           reset : in  STD_LOGIC;
-           ram_en : out  STD_LOGIC;
-           instruction_fifo_full : out  STD_LOGIC;
-           switch_port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0));
-	end COMPONENT;
--- cette fonction met en place l'architecture d'exécution de l'environnement
--- elle permet de construire le Noc et de connecter les différents core MPI
--- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank
--- faut il créer une petite mémoire chargée de stocker les IDs ?
--- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer
--- un communicateur au MPI Core
-
-
-
-  begin
-Socsyst: if nproc >  1   generate  --nproc
-      -- instancier le switch et connecter les différents ports
-				 
-sw_gen1: SWITCH_GEN generic map (NPROC)
-		 PORT MAP (
-          Port_in => Noc_PortIn,
-
-          Port_out => noc_Portout,
-
-          --signaux de contrôle de la lecture des ports
-			 data_in_en => noc_data_in_en,
-			 cmd_in_en => noc_cmd_in_en,
-          data_out_en => noc_data_out_en,
-          fifo_in_full => noc_fifo_in_full,
-          fifo_in_empty => noc_fifo_in_empty,
-          data_available => noc_data_available,
-          clk => MPI_Node_in(1).clk,
-          reset => MPI_Node_in(1).reset
-			 );
-		end generate;
-HCL_c:		for i in 1 to nproc generate  -- nproc
-		hardmpi:core_mpi port map (
-		
-			 
-			  PushOut=>MPI_Node_out(i).PushOut, 
-           ram_we=> MPI_Node_out(i).ram_we,
-			  ram_en=>MPI_Node_out(i).ram_en ,
-			  hold_req=>MPI_NODE_out(i).hold_req,
-			  packet_received=>MPI_Node_out(i).packet_received ,
-			  packet_ack=>MPI_Node_in(i).packet_ack,
-			  hold_ack=>MPI_NODE_in(i).hold_ack,
-           ram_address_rd => MPI_Node_out(i).ram_address_rd ,
-			  ram_address_wr => MPI_Node_out(i).ram_address_wr ,
-           ram_data_in=>MPI_Node_out(i).ram_data_in ,
-			  ram_data_out=>MPI_Node_in(i).ram_data_out,
-			  barrier_completed =>MPI_Node_out(i).barrier_completed, 			 
-			  instruction => MPI_Node_in(i).instruction,
-			  instruction_en => MPI_Node_in(i).instruction_en,
-			  instruction_fifo_full =>MPI_Node_Out(i).instruction_fifo_full,
-			  switch_port_in_wr_en => noc_data_in_en(i),
-			  switch_port_in_cmd_en=>noc_cmd_in_en(i),
-           switch_port_in_full => noc_fifo_in_full(i),
-			  switch_port_in_empty => noc_fifo_in_empty(i),
-           switch_port_in_data => noc_PortIn(i),
-           switch_port_out_rd_en => noc_data_out_en(i),
-           switch_port_out_data_vailaible => noc_data_available(i),
-			  switch_port_out_data => noc_PortOut(i),
-			  clk =>MPI_Node_in(1).clk,
-           reset =>MPI_Node_in(1).reset
-           
-			  );
-		end generate;
-	
-	
-
-
-end Structural;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_PKG.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_PKG.vhd	(revision 97)
+++ 	(revision )
@@ -1,127 +1,0 @@
---	Package File Template
---
---	Purpose: This package defines supplemental types, subtypes, 
---		 constants, and functions 
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-Library NocLib;
-use NocLib.CoreTypes.all;
-package mpi_pkg is
--- Declare constants
-
---  constant <constant_name>		: time := <time_unit> ns;
-  constant NPROC		: positive:= 8;
-
--- type declaration
-type portio is array(1 to NPROC) of std_logic_vector (Word-1 downto 0);  
---  type <new_type> is
---    record
---        <type_name>        : std_logic_vector( Word-1 downto 0);
---        <type_name>        : std_logic;
---    end record;
-
-
--- Declare signals for interconnections
- 
-
-   --Inputs
-   signal noc_portOut :portio;
-   signal noc_portIn  :portio;
-	   
-   signal noc_fifo_in_full :  std_logic_vector(NPROC downto 1):= (others => '0');
-   signal noc_data_available :   std_logic_vector(NPROC downto 1):= (others => '0');
-   signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0');
-	signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0');
-   signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0');
-   signal noc_clk : std_logic := '0';
-   signal noc_reset : std_logic := '0';
-	
--- Declare components
-COMPONENT SWITCH_GENERIQUE
-	 GENERIC (number_of_ports : positive := 8);
-    PORT(
-         Port1_in : IN  std_logic_vector(Word-1 downto 0);
-         Port2_in : IN  std_logic_vector(Word-1 downto 0);
-         Port3_in : IN  std_logic_vector(Word-1 downto 0);
-         Port4_in : IN  std_logic_vector(Word-1 downto 0);
-         Port5_in : IN  std_logic_vector(Word-1 downto 0);
-         Port6_in : IN  std_logic_vector(Word-1 downto 0);
-         Port7_in : IN  std_logic_vector(Word-1 downto 0);
-         Port8_in : IN  std_logic_vector(Word-1 downto 0);
-         Port9_in : IN  std_logic_vector(Word-1 downto 0);
-         Port10_in : IN  std_logic_vector(Word-1 downto 0);
-         Port11_in : IN  std_logic_vector(Word-1 downto 0);
-         Port12_in : IN  std_logic_vector(Word-1 downto 0);
-         Port13_in : IN  std_logic_vector(Word-1 downto 0);
-         Port14_in : IN  std_logic_vector(Word-1 downto 0);
-         Port15_in : IN  std_logic_vector(Word-1 downto 0);
-         Port16_in : IN  std_logic_vector(Word-1 downto 0);
-         Port1_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port2_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port3_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port4_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port5_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port6_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port7_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port8_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port9_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port10_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port11_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port12_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port13_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port14_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port15_out : OUT  std_logic_vector(Word-1 downto 0);
-         Port16_out : OUT  std_logic_vector(Word-1 downto 0);
-         data_in_en : IN  std_logic_vector(8 downto 1);
-         data_out_en : IN  std_logic_vector(8 downto 1);
-         fifo_in_full : OUT  std_logic_vector(8 downto 1);
-         fifo_in_empty : OUT  std_logic_vector(8 downto 1);
-         data_available : OUT  std_logic_vector(8 downto 1);
-         clk : IN  std_logic;
-         reset : IN  std_logic
-        );
-    END COMPONENT;
-	COMPONENT CORE_MPI is
-    Port ( instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           instruction_en : in  STD_LOGIC;
-           ram_data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           barrier_completed : out  STD_LOGIC;
-           packet_received : out  STD_LOGIC;
-			  packet_ack : in std_logic;
-           PushOut : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           ram_we : out  STD_LOGIC;
-           ram_address : out  STD_LOGIC_VECTOR (15 downto 0);
-           ram_data_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           switch_port_in_wr_en : out  STD_LOGIC;   -- OK (au switch) pour lire les données 
-           switch_port_in_full : in  STD_LOGIC;  -- port d'entréendu switch saturé
-           switch_port_in_data : out  STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée
-           switch_port_out_rd_en : out  STD_LOGIC;    -- OK (au switch) pour écrire les données
-           switch_port_out_data_vailaible : in  STD_LOGIC; -- Donnée disponible à la sortie (du switch)
-			  clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           ram_en : out  STD_LOGIC;
-           instruction_fifo_full : out  STD_LOGIC;
-           switch_port_out_data : in  STD_LOGIC_VECTOR (Word-1 downto 0));
-	end COMPONENT;
--- declare functions and procedure	 
-  
-end MPI_PKG;
-
-
-package body MPI_PKG is
-
--- Example 1
-   
-
-
--- cette fonction met en place l'architecture d'exécution de l'environnement
--- elle permet de construire le Noc et de connecter les différents core MPI
--- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank
--- faut il créer une petite mémoire chargée de stocker les IDs ?
--- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer
--- un communicateur au MPI Core
-  
-   
-end MPI_PKG;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_RMA.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_RMA.vhd	(revision 97)
+++ 	(revision )
@@ -1,1778 +1,0 @@
---	Package File Template
---
---	Purpose: This package defines supplemental types, subtypes, 
---		 constants, and functions 
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-Library NocLib;
-use NocLib.CoreTypes.all;
-use work.PACKET_TYPE.all;
-
-package Mpi_Rma is
-procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram);
-procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram);
-procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural);
-
-procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural);
-procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector );
-
-procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-									base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; 
-									info:natural; comm:Mpi_Comm; Win: inout MPI_Win );
-procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win);
-procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win);
-procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win);
-procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win);
-procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;  
-command : natural;  argv :natural; maxprocs : natural;  info : natural; root : natural;   comm : natural;  
-signal intercomm :out natural; signal  array_of_errcodes : out natural);
--- declare functions and procedure	 
- procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; data: out std_logic_vector);
-procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; Data:in std_logic_vector);						
-
-procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-				variable	AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic);
-
-end MPI_Rma;
-
-
-package body MPI_Rma is
-----int MPI_Put(
---  void *origin_addr,
---  int origin_count,
---  MPI_Datatype origin_datatype,
---  int target_rank,
---  MPI_Aint target_disp,
---  int target_count,
---  MPI_Datatype target_datatype,
---  MPI_Win win
---);
--- Example 1
-procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural) is
-variable i,dcount,wr_state : natural:=0;
-variable adresse :natural;
-variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr;
-variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp;
-variable put_adr : std_logic_vector (ADRLEN-1 downto 0);
-variable config_reg: std_logic_vector (Word-1 downto 0);
-constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');
-	begin   
-				put_adr:=conv_Std_logic_vector(Core_put_adr,ADRLEN);
-				
-				addr1:=Orig_Addr;
-				addr2:=Target_Disp;
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-				dcount:=NextCtx;
-				end if;
---					
-					
-				if rising_edge(clkin) then		
-				  if dcount= 0 then
-				      dcount:=dcount+1;
-				      Interf.S.Intstate1<=0;
-					elsif dcount>=1 and dcount <=3 then 
-									if interf.I.ramsel='0' then
-											Interf.O.membusy<='0';
-											--SysRam.O.we<='1';
-											--SysRam.O.ena<='1';
-											SysRam.O.enb<='1';
-											wr_state:=interf.S.Intstate1;
-											WritePtr (put_adr,wr_state,SysRam);
-											interf.S.Intstate1<=wr_state;
-											if wr_state =0 then 
-												-- fin de l'écriture du pointeur en mémoire 
-											dcount:=4;
-											end if;								
-									end if;
-							
-							elsif dcount=4 then
-							if interf.I.ramsel='0' then
-								SysRam.O.we<='1';
-								SysRam.O.ena<='1';
-								SysRam.O.enb<='0';
-								Interf.O.membusy<='1';
-								if target_rank <=15 then --limitation de cete version à 16 rang
-								Interf.S.Gstart(Target_rank)<='1';
-								end if;
-								adresse:=core_put_adr;
-								SysRam.O.Data_in<=MPI_PUT & conv_std_logic_vector(Target_Rank,4); --code fonction
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-							end if;
-							elsif dcount=5 then 
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+1;
-								SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								Interf.O.Instruction<=x"06"; -- nombre de mots de l'instruction
-								end if;
-							elsif dcount=6 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+2;
-								SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=7 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+3;
-								SysRam.O.Data_in<=Addr1(Word-1 downto 0);  --source Bas
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=8 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+4;
-								SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=9 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+5;
-								SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=10 then
-								
-								SysRam.O.we<='1';
-								SysRam.O.ena<='1';
-								SysRam.O.enb<='1';
-								if interf.I.ramsel='0' then
-								adresse:=core_base_adr+1;
-								SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire;
-								Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction
-								Interf.O.membusy<='0';
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=11 then
-								if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ?
-									Interf.O.Instr_En<='0';   --désactiver la prise en compte de l'instruction
-									dcount:=dcount+1;
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-								else
-								  Interf.O.Instr_En<='1'; 
-								end if;
-									adresse:=core_base_adr+1;
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-									SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									--SysRam.O.Ram_busy<='0'; --??
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';  -- préparer la lecture du résultat du Put
-									SysRam.O.enb<='1';						
-							elsif dcount=12 then
-									adresse:=core_base_adr+1;
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';  -- préparer l'écriture du résultat du Put
-									SysRam.O.enb<='1';
-									if interf.I.ramsel='0' then
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-									dcount:=dcount+1;
-									Interf.O.membusy<='1';
-									end if;
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-							elsif dcount=13 then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';  -- préparer l'écriture du résultat du Put
-									SysRam.O.enb<='0';
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-									dcount:=dcount+1;
-									adresse:=core_base_adr+1;
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-							elsif dcount=14 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen));
-										if SysRam.I.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie !
-											dcount:=dcount+1;
-											SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-										  Interf.S.Intstate2<=255; --timer pour la réception
-										  interf.s.tmem(0)<=x"02";
-										  report "MPV pMPI_PUT():Ex1 de HCL a répondu concernant l'envoi";
-										end if;
-									end if;
-							elsif dcount=15 or dcount=16 or dcount=17 then
-							  SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-							  SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-							   -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse
-						 
-						   if interf.I.ramsel='0' then 
-							  dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse
-							  
-						    elsif Interf.S.Intstate2>0  then 
-						      dcount:=15;
-										  Interf.S.Intstate2<=Interf.S.Intstate2-1;
-								elsif interf.s.tmem(0)>0 then
-										    interf.s.tmem(0)<=interf.s.tmem(0)-1;
-										    Interf.S.Intstate2<=255;
-										    dcount:=15;
-								else
-										   dcount:=1;--recommencer l'envoi
- 								end if;
-							elsif dcount=18 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-										if SysRam.I.Data_out(5)='1' then --Message  du MPI PUT bien reçu !
-											dcount:=dcount+1;
-											report "MPV pMPI_PUT():Ex2 de HCL a reçu un acquittement concernant l'envoi";
-											SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-										elsif Interf.S.Intstate2>0  then 
-										  Interf.S.Intstate2<=Interf.S.Intstate2-1;
-										 elsif interf.s.tmem(0)>0 then
-										    interf.s.tmem(0)<=interf.s.tmem(0)-1;
-										    Interf.S.Intstate2<=255;
-										  else
-										   dcount:=1;--recommencer l'envoi
-										   report "MPV pMPI_PUT():Timeout EX2 n'a pas reçu d'acquitement concernant l'envoi. reémission en cours...";
- 										end if;
- 									else
- 									  dcount:=15;
-									end if;
-							elsif dcount=19 then	
-									dcount:=0; --fin normale de la fonction
-									Interf.O.membusy<='0';
-									report "MPV pMPI_PUT():fin normale de la fonction";
-							end if;
-							
-							
-						  NExtCtx:=dcount;
-				end if;
-	end procedure;
-
-procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural) is
-variable i,wcount,dcount : natural range 0 to 255:=0;
-variable adresse :natural;
-variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0');
-variable bitval : std_logic:='0';
-variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr;
-variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp;
-variable get_adr : std_logic_vector (ADRLEN-1 downto 0);
-variable config_reg,win_reg: std_logic_vector (Word-1 downto 0);
-constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');
-	begin   
-				get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN));
-				
-				addr1:=Orig_Addr;
-				addr2:=Target_Disp;
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-				dcount:=NextCtx;
-				end if;
---					
-					
-				if rising_edge(clkin) then		
-							
-						if dcount =0 then	
-							dcount:=dcount+1;
-							Interf.S.IntState1<=0;
-						elsif dcount>=1 and dcount <=3 then 
-									if interf.I.ramsel='0' then
-											SysRam.O.we<='1';
-											SysRam.O.ena<='1';
-											SysRam.O.enb<='0';
-											wcount:=Interf.S.IntState1;
-											WritePtr (get_adr,wcount,SysRam);
-											Interf.S.IntState1<=wcount;
-											Interf.O.membusy<='1';
-											if wcount =0 then 
-												dcount:=4;
-												Interf.S.Intstate1<=1;
-											end if;	
-										else 
-										  Interf.S.IntState1<=0;
-																	
-									end if;
-							
-							elsif dcount=4 then
-							if interf.I.ramsel='0' then 
-								SysRam.O.we<='1';
-								SysRam.O.ena<='1';
-								SysRam.O.enb<='0';
-								if target_rank <=15 then --limitation de cete version à 16 rang
-								Interf.S.Gstart(Target_rank)<='1';
-								end if;
-								adresse:=core_get_adr;
-								SysRam.O.Data_in<=MPI_GET & conv_Std_logic_vector(Target_Rank,4); --code fonction
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								Interf.O.membusy<='1';
-								dcount:=dcount+1;
-							end if;
-							elsif dcount=5 then 
-								if interf.I.ramsel='0' then	 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+1;
-									SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								  interf.O.Instruction<=x"06"; --le nbre de mots de l'intstruction
-									dcount:=dcount+1;
-								end if; 
-							elsif dcount=6 then
-								if interf.I.ramsel='0' then 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+2;
-									SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									
-									dcount:=dcount+1;
-
-								end if;
-							elsif dcount=7 then
-								if interf.I.ramsel='0' then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+3;
-									SysRam.O.Data_in<=Addr1(Word-1 downto 0);  --source Bas
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									
-									dcount:=dcount+1;
-								end if;
-							elsif dcount=8 then
-								if interf.I.ramsel='0' then 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';					
-									adresse:=core_get_adr+4;
-									SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									Interf.O.membusy<='1';
-									dcount:=dcount+1;
-								end if;
-							elsif dcount=9 then
-								if interf.I.ramsel='0' then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+5;
-									SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									Interf.O.membusy<='1';
-									dcount:=dcount+1;
-								end if;
-								elsif dcount=10 then
-								if interf.I.ramsel='0' then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+7;
-									SysRam.O.Data_in<=x"00"; -- résultat du GET
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									Interf.O.membusy<='1';
-									Interf.S.IntState2<=0;
-									dcount:=dcount+1;
-								end if;
-							elsif dcount=11 then
-								 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									SysRam.O.enb<='1';
-									addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-									wcount:=Interf.S.IntState2;
-									wdata:=x"01";bitval:='1';
-									setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval);
-									Interf.S.IntState2<=wcount;
-									if wcount=0 then
-									  dcount:=dcount+1;
-									  Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction
-									 end if;
-
-							elsif dcount=12 then
-								if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ?
-									Interf.O.Instr_En<='0';   --désactiver la prise en compte de l'instruction
-									dcount:=dcount+1;
-									config_reg:=SysRam.I.Data_out and x"f6";
-									--SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-								end if;
-									adresse:=core_base_adr+1;
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN));
-									SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									--SysRam.O.Ram_busy<='0'; --??
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';  -- préparer la lecture du résultat du get
-									SysRam.O.enb<='1';	
-									Interf.O.membusy<='0';
-							elsif dcount=13 then
-								
-									adresse:=core_base_adr+1;
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';  -- préparer l'écriture du résultat du get
-									SysRam.O.enb<='1';
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN));
-									SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-
-								if interf.I.ramsel='0' then 	
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-									dcount:=dcount+1;
-									Interf.O.membusy<='1';
-								end if;
-										Interf.s.IntState2<=255;
-										Interf.s.tmem(0)<=x"08"; --tempo pour l'attente du résultat de Get							
-							elsif dcount=14 then
-									 
-										SysRam.O.we<='1';
-										SysRam.O.ena<='1';  -- préparer l'écriture du résultat du GET
-										SysRam.O.enb<='0';
-										adresse:=core_base_adr+1;
-										SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out and x"f6";
-										SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-										dcount:=18;--dcount+1;
-										Interf.O.membusy<='1';
-						
-									end if;
-							elsif dcount=15 then
-									 
-										SysRam.O.we<='0';
-										SysRam.O.ena<='0';  -- préparer l'écriture du WBusy
-										SysRam.O.enb<='1';
-										adresse:=core_base_adr+5;
-										SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-										SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy
-										SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy
-										dcount:=dcount+1;
-										Interf.O.membusy<='1';
-									end if;
-							elsif dcount=16 then
-									 
-										SysRam.O.we<='0';
-										SysRam.O.ena<='0';  -- préparer l'écriture du WBusy
-										SysRam.O.enb<='1';
-										adresse:=core_base_adr+5;
-										SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy
-										SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy
-										dcount:=dcount+1;
-										Interf.O.membusy<='1';
-								
-									end if;
-							elsif dcount=17 then
-									 
-										SysRam.O.we<='1';
-										SysRam.O.ena<='1';  -- préparer l'écriture du résultat du GET
-										SysRam.O.enb<='1';
-										adresse:=core_base_adr+5;
-										SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out or x"40";
-										SysRam.O.Data_in<=config_reg ; --;
-										dcount:=dcount+1;
-										Interf.O.membusy<='1';
-									end if;
-							elsif dcount>=18 and dcount <=21 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen));
-										if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie !
-											dcount:=dcount+1;
-										end if;
-									end if;
-	         elsif dcount>=22 and dcount <=24 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen);
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen);
-										if SysRam.I.Data_out(5)='1' then --Message  du MPI Get bien reçu !
-											dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème !
-											SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen);
-										elsif Interf.S.Intstate2>0 then 
-										  Interf.S.Intstate2<=Interf.S.Intstate2-1;
-										 elsif interf.s.tmem(0)>0 then
-                          interf.s.tmem(0)<=interf.s.tmem(0)-1;
-                          Interf.S.Intstate2<=255;
-										  else
-										   dcount:=1;--recommencer l'envoi
- 										end if;
-									end if;
-							
-							elsif dcount=25 then	
-									dcount:=0; --fin normale de la fonction
-									Interf.O.membusy<='0';
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='0';
-							end if;
-
-						  NExtCtx:=dcount;
-			end if; 
-	end procedure; 
-Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is 
-Begin
---cette procédure permet de récupérer le groupe qui est associé à un communicateur
---dans notre cas c'est la récupération du groupe associé à COMM_WORLD
-end procedure;
---int MPI_Group_incl(MPI_Group group, int n, int *ranks,
---    MPI_Group *newgroup)
-Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram;
-									GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is
-Begin
--- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks
--- et d'activer l'un des  bits de position de newgroup. 
--- 
---
-end procedure;
-								
-procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is
-variable adresse_rd : natural range 0 to 2**ADRLEN-1;	
-
-begin
-
-		if NextCtx =0 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			
-				NextCtx:=1;
-		
-		elsif NextCtx=1 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				NextCtx:=2;
-				Interf.O.membusy<='1';
-			end if;	
-		elsif NextCtx=2 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0));
-				NextCtx:=3;
-				Interf.O.membusy<='1';
-			end if;	
-		elsif NextCtx=3 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0));
-				NextCtx:=4;
-				Interf.O.membusy<='1';
-			end if;	
-		elsif NextCtx=4 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0));
-				NextCtx:=0;
-				Interf.O.membusy<='0';
-			end if;	
-		end if;
-end procedure;
-
---int MPI_Win_create(
---  void *base,
---  MPI_Aint size,
---  int disp_unit,
---  MPI_Info info,
---  MPI_Comm comm,
---  MPI_Win *win
---);
-procedure pMPI_Win_create(NextCtx : inout natural ;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-									base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; 
-									info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is
- -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre
- -- si fenêtre libre trouvée, et 
- -- mise à 1 du Bit WCreate du registre status
- type wtype is array (1 to 4 ) of natural range 0 to 255;
- variable AdrWin: std_logic_vector(ADRLEN-1 downto 0);
- variable adresse : std_logic_vector(ADRLEN-1 downto 0);
- variable clkin : std_logic:='1';
- variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN));
- variable w0 : std_logic_vector(Word-1 downto 0);
- variable adrnat : natural;
- variable sizewin : std_logic_vector(Word-1 downto 0);
- variable count : natural range 0 to 255;
- variable wdisp  :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre
-begin
--- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner 
--- le pointeur qui permet de le décrire 
-
-
-If NextCtx=0 then 
-	NExtCtx:=NextCtx+1;
-	count:=0;
-	Interf.O.membusy<='0';
-	Interf.S.IntState1<=count;
-elsif NextCtx>=1 and NextCtx <= 4 then
-	count:=Interf.S.IntState1;
-	AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16));
-	 readmem(count,interf,sysRam,AdrWin,w0);
-		if count=0 then
-			if w0(0)/='1' then -- cette fenêtre est libre
-				NextCtx:=6; --étape de la création de la fenêtre
-				Win.addr:=base; --l'adresse de la fenêtre
-				Win.id:=NextCtx; -- la référence provisoire de la fenêtre
-				Win.size:=Size; -- la taille de la fenêtre
-				
-			else
-				NextCtx:=NextCtx+1;
-			end if;
-		end if;
-		Interf.S.IntState1<=count;--sauvegarde du statut de la sous-procédure
-		
-elsif NextCtx=5 then
-	-- Plus de fenêtre disponible erreur
-		NextCtx:=1; -- boucle sans fin :)
-		Win.id:=0;
-		Win.addr:=x"0000";
-elsif NextCtx=6 then
-		--Affectation de l'objet Windows car une place est disponible
-		count:=Interf.S.IntState1;
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-		
-elsif NextCtx=8 then
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		interf.S.winid<=interf.S.winid+1;
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,AdrWin+1,stdlv(interf.S.winid,8)); --win id de la fenêtre
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=9 then
-
-		adrnat:=Core_base_adr+Wdisp(Win.id);
-		
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		count:=Interf.S.IntState1;
-		
-		
-		Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=10 then
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=11 then
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		sizewin:=std_logic_vector(to_unsigned(size,8));
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=12 then	
-	--cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer
-	-- les informations donnant le numéro de la fenêtre
-		W0:=MPI_WIN_CREATE & std_logic_vector(to_unsigned(0,4)); --code fonction
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,wcreate_adr,w0);
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-		
-	elsif NextCtx=13 then 
-		w0:=std_logic_vector(to_unsigned(Win.Id,8));							-- id proposé pour la fenêtre en création
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,wcreate_adr+1,w0);
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-	elsif NextCtx=14 then
-		SysRam.O.we<='1';
-		SysRam.O.ena<='1';
-		SysRam.O.enb<='0';
-		count:=Interf.S.IntState1;
-		if interf.I.ramsel='0' then
-			WritePtr (wcreate_adr,count,SysRam); --écriture du pointeur d'instruction
-			Interf.S.IntState1<=count;
-			if count=0 then
-				NextCtx:=NextCtx+1;
-			end if;
-		end if;
-	elsif NextCtx=15 then
-									-- il faut mettre instruction_en à 1
-				SysRam.O.we<='0';
-				SysRam.O.ena<='0';
-				SysRam.O.enb<='1';
-				SysRam.O.we<='1';
-				SysRam.O.ena<='1';
-				SysRam.O.enb<='1';
-				adresse:=stdlv(core_base_adr+1);
-								SysRam.O.addr_rd<=adresse;
-								SysRam.O.Addr_wr<=adresse;
-								SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire;
-		Writemem(count,interf,SysRam,adresse,x"01");
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-				Interf.O.Instr_En<='1';
-				adresse:=stdlv(core_base_adr);
-				SysRam.O.Addr_rd<=adresse;
-				NextCtx:=NextCtx+1;
-	elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib
-				if Interf.I.Instr_ack='1' then
-					Interf.O.Instr_En<='0';
-					NextCtx:=NextCtx+1;
-				end if;
-				SysRam.O.we<='0';
-				SysRam.O.ena<='0';
-				SysRam.O.enb<='1';
-	elsif NextCtx=17 then
-			-- lecture du résultat de l'instruction
-			
-	
-else
-	
-end if;
-end procedure;
---int MPI_Win_start(
---  MPI_Group group,
---  int assert,
---  MPI_Win win
---);
-procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is
---cette fonction active les bits WStart pour chaque processus avec lequel 
--- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à
---chacune de ces cibles
- variable dcount : natural range 0 to 255:=0;
- variable cstatus : std_logic_vector(Word-1 downto 0);
- begin
-
- -- retour de l'adresse de de la fenêtre dans la structure Win
- -- initialisation des bits concernant 
- 
- if NextCtx =0 then 
-			NextCtx:=NextCtx+1;
-		elsif NextCtx=1 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-					SysRam.O.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits	
-							
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';		
-					Interf.S.GStart<=(others=>'0');				
-			end if;
-	elsif NextCtx=2 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-					SysRam.O.Data_in<=x"01";
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-		elsif NextCtx=3 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-					SysRam.O.Data_in<=x"01";
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-	elsif NextCtx=4 then
-		NextCtx:=0;
-		Interf.O.membusy<='0';
-		SysRam.O.we<='0';
-		SysRam.O.ena<='0';
-	end if;
-
- 
- end procedure;
-procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is
-variable adresse :natural;
-variable wcount: natural range 0 to 255:=0;
-variable LRam : typ_dpRam;
-variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation
-variable W0 :std_logic_vector(Word-1 downto 0);
-variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN));
-
-begin
-  --
-  				wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN));
-				LRam:=SysRam; -- nécessaire pour le débogage
-				if NextCtx =0 then
-					
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='0';
-					Interf.O.MemBusy<='1'; --occuper la mémoire
-					Interf.S.IntState1<=0;
-					NextCtx:=1;
-					adresse:=core_wcompl_adr;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					
-				elsif NextCtx=1 then --écriture du ptr d'intruction
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					if interf.I.ramsel='0' then
-					
-					adresse:=core_wcompl_adr;
-				
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					Interf.O.membusy<='1';
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-				  wcount:=Interf.S.IntState1;
-          WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir
-          Interf.S.IntState1<=wcount;
-          
-            if wcount =0 then 
-                  NextCtx:=2;
-                  Interf.S.IntState1<=0;
-                  Interf.S.IntState2<=0;
-                  Interf.S.tmem(0)<=Interf.S.GStart(7 downto 0); --cibles impactées
-                  Interf.S.tmem(1)<=Interf.S.GStart(15 downto 8); --cibles impactées
-                  adresse:=core_wcompl_adr;
-                  SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-            end if;	
-      else
-        Interf.S.IntState1<=0; --recommencer l'écriture du pointeur	
-         end if;       
-				elsif NextCtx=2 then 
-					if 	Interf.I.Ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_wcompl_adr;
-				  NextCtx:=10; --aller à la fin de la fonction
-				  i:=0;
-				  l1:for i in 0 to 7 loop
-				  --  i:=i+1;
-				  if i>=interf.s.intState2 then 				  
-				  if interf.s.gstart(i)='1' then
-					SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4));
-					Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4));
-
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.S.tmem(0)(i)<='0'; --ce dest a été traité !
-					NextCtx:=4;
-					Interf.S.IntState2<=i+1;
-					exit l1;
-					end if;
-					end if;
-					exit l1 when i=7;
-					end loop l1;
-					end if;
-				elsif NextCtx=3 then 
-					if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';	
-				  adresse:=core_wcompl_adr;
-				  wcount:=Interf.S.IntState1;
-          WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir
-          Interf.S.IntState1<=wcount;
-					SysRam.O.Data_in<= Interf.S.tmem(2);
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					if wcount=0 then 
-					 NextCtx:=NextCtx+1;
-					 end if;
-					end if;
-				elsif NextCtx=4 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';	
-				  adresse:=core_wcompl_adr+1;
-					SysRam.O.Data_in<= x"04" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-				elsif NextCtx=5 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-					adresse:=core_wcompl_adr+2;
-				  Interf.O.Instruction<=x"04";--longueur de l'instruction
-					SysRam.O.Data_in<=x"00" ;--
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=6;
-				elsif NextCtx=6 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_wcompl_adr+3;
-					SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4));
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=7;
-				elsif NextCtx=7 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-				  adresse:=core_wcompl_adr+3;
-					SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4));
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-
-				elsif NextCtx=8 then --fin de la fonction
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							--dcount:=0;
-							Interf.O.membusy<='0';
-							Interf.O.Instr_En<='1';
-							SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen));
-							NextCtx:=NextCtx+1;
-				elsif NextCtx=9 then --acquittement de la copie des données dans le tampon
-							if Interf.I.Instr_ack='1' then
-								Interf.O.Instr_En<='0';
-								NextCtx:=10;
-							end if;
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							
-				elsif NextCtx=10 then --lecture de la fin de WComplete
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							Interf.O.membusy<='0';
-							if interf.S.IntState2=0 then --aucune instruction MPI exécutée ?
-							  NextCtx:=12;
-							elsif Interf.S.tmem(0)/=0 then --plus de message compl à envoyer
-							   NextCtx:=2;
-							 elsif Interf.S.tmem(0)=0 then
-							   if interf.I.ramsel='0' then
-							       NextCtx:=NextCtx+1;
-          							   SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-							   end if;
-							 end if; 
-				elsif NextCtx=11 then --test de la fin des transferts
-					if interf.I.ramsel='0' then
-        					SysRam.O.we<='0';
-        					SysRam.O.ena<='0';
-        					SysRam.O.enb<='1';
-        					SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-        							if SysRam.I.Data_out(0)='1' and  SysRam.I.Data_out(6)='0' then --si WStart=1 et Wbusy=0
-        							  --il faut un DSent=1 pour Put ou un DSending pour Get
-										if SysRam.I.Data_out(5)='1' or  (SysRam.I.Data_out(4)='1' and SysRam.I.Data_out(1)='1')  then 
-												NextCtx:=NextCtx+1;
-										end if;	
-									end if;									
-				
-					end if;	
-				elsif NextCtx=12 then
-									Interf.S.IntState1<=0; -- initialisation du compteur d'état
-								Interf.S.IntState2<=0;
-									SysRam.O.enb<='0';
-								NextCtx:=0; --fin de la fonction			
-      end if;
-
-end procedure;
-procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is
---cette fonction active les bits WStart pour chaque processus avec lequel 
--- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à
---chacune de ces cibles
- variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire 
- variable dcount : natural range 0 to 255:=0;
- variable cstatus : std_logic_vector(Word-1 downto 0);
- begin
-
- -- retour de l'adresse de de la fenêtre dans la structure Win
- -- initialisation des bits concernant 
- if Win.id =0 then
-   W_ptr:=Core_Base_Adr+4;
- end if;
- if NextCtx =0 then 
-			
-			if pgroup.grp=0 then --rien à faire
-			  nextCtx:=5;
-			  Interf.S.GPost<=(others=>'0');
-			 else
-			   NextCtx:=NextCtx+1;
-			end if;
-		elsif NextCtx=1 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-					SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits	
-							
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';		
-									
-			end if;
-			 --limitation de cete version à 16 rang
-				Interf.S.GPost<=pgroup.grp;
-	elsif NextCtx=2 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-					SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits	
-							
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';		
-									
-			end if;						
-	elsif NextCtx=3 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_Ptr+W_Gpost,Adrlen));
-					SysRam.O.Data_in<=pgroup.grp(7 downto 0);
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-elsif NextCtx=4 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen));
-					SysRam.O.Data_in<=pgroup.grp(15 downto 8);
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-elsif NextCtx=6 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen));
-					SysRam.O.Data_in<=pgroup.grp(15 downto 8);
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-	elsif NextCtx=5 then
-	         SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='0';
-		NextCtx:=0;
-		Interf.O.membusy<='0';
-	end if;
-
- 
- end procedure;
- 
- procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is
---permet de synchroniser la fin des opérations sur une fenêtre
-variable dcount : natural range 0 to 255:=0;
-variable cstatus : std_logic_vector(Word-1 downto 0);
-variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire
-begin
-	W_Ptr:=Core_base_adr+4;--adresse du reg status de la première fenêtre
-		if NextCtx =0 then 
-			NextCtx:=NextCtx+1;
-		elsif NextCtx=1 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='1';
-					NextCtx:=NextCtx+1;
-			end if;
-			     SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen));
-            If Interf.S.Gpost=0 then
-             NextCtx:=5; --rien à synchroniser
-          end if;
-  elsif (NextCtx>=2) and (NextCtx <=3) then
-    SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-    if interf.I.ramsel='0' then
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='1';
-					NextCtx:=NextCtx+1;
-		else
-		    NextCtx:=1;
-		   end if;
-		elsif NextCtx=4 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='1';
-					SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-						
-							if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0
-							  --il faut un DSent=1 pour Put ou un DSending pour Get
-  							   if SysRam.I.Data_out(4)='1' or  (SysRam.I.Data_out(5)='1' and SysRam.I.Data_out(2)='1')  then 
-  									   NextCtx:=NextCtx+1;
-  									   Interf.S.GPost<=(others=>'0');
-  							   end if;	
-							elsif SysRam.I.Data_out(3)='0' then 
-              							  NextCtx:=NextCtx; --pas d'opérations en attente
-							else
-							  NextCtx:=NextCtx; --on attend
-							end if;	
-			else
-			 NextCtx:=2;		--retour à l'atente du Bit !
-			end if;	
-	
-	elsif NextCtx=5 then
-		      SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='0';
-		      NextCtx:=0;
-	end if;
-
-
-end procedure;
-
-
- Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is
-  begin
- 
- end procedure;
- 
- procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;  
-command : natural;  argv :natural; maxprocs : natural;  info : natural; root : natural;   comm : natural;  
-signal intercomm :out natural; signal  array_of_errcodes : out natural) is
-
-variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable spawn_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN));
-begin
- spawn_adr:=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN));
-				if NextCtx =0 then
-					
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					NextCtx:=1;
-				elsif NextCtx=1 then 
-					if interf.I.ramsel='0' then
-					NextCtx:=2;
-					adresse:=core_spawn_adr;
-					SysRam.O.Data_in<=MPI_SPAWN & x"0" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.membusy<='1';
-					Interf.O.Instr_En<='0';
-					Interf.S.IntState2<=1; -- préparation de la destination du spawn
-					end if;
-				elsif NextCtx=2 then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					if interf.I.ramsel='0' then
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';
-					adresse:=core_spawn_adr;
-					if interf.I.ismain='1' then ---déclanche l'éxécution de la commande
-						SysRam.O.Data_in<=MPI_spawn & x"0";--Std_logic_vector(to_unsigned(Interf.S.IntState2+2,4)) ;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-						
-					else -- envoie d'une commande spawn à la main lib
-						SysRam.O.Data_in<=MPI_spawn & x"0" ;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-						Interf.O.Instr_En<='0';
-						Interf.O.membusy<='1';
-						
-						end if;
-					end if;
-				
-				elsif NextCtx=3 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					adresse:=core_spawn_adr;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-				elsif NextCtx=4 then	
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+1;
-								SysRam.O.Data_in<=std_logic_vector(to_unsigned(4,8)) ;--la longueur
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								Interf.O.Instruction<=x"04";
-								NextCtx:=NextCtx+1;
-					end if;
-				elsif NextCtx=5 then
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+2;
-								SysRam.O.Data_in<=std_logic_vector(to_unsigned(maxprocs,8)) ;--le nombre de processus
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								NextCtx:=NextCtx+1;
-					end if;
-				elsif NextCtx=6 then
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+3;
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction
-								NextCtx:=NextCtx+1;
-
-					end if;
-				elsif NextCtx=7 then
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+3;
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction
-								NextCtx:=NextCtx+1;
-                report "MPV SPAWN activé " & integer'image(interf.I.Rank);
-					end if;
-				elsif NextCtx=8 then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					dcount:=Interf.S.IntState1;
-					if interf.I.ramsel='0' then
-						SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN));
-						WritePtr (spawn_adr,dcount,SysRam);
-						Interf.O.Instr_En<='0';
-						Interf.O.membusy<='1';
-						Interf.S.IntState1<=dcount;
-						if dcount =0 then 
-								NextCtx:=NextCtx+1;
-						end if;
-					end if;
-				elsif NextCtx=9 then
-			
-				 --fin de la fonction
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							dcount:=0;
-							Interf.O.membusy<='0';
-							Interf.O.Instr_En<='1';
-							SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen));
-							NextCtx:=NextCtx+1;
-				elsif NextCtx=10 then --acquittement de la copie des données dans le tampon
-							if Interf.I.Instr_ack='1' then
-								Interf.O.Instr_En<='0';
-								NextCtx:=NextCtx+1;
-							end if;
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-				elsif NextCtx=11 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+7; 
-							SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-							if interf.I.ramsel='0' then 	
-									NextCtx:=NextCtx+1;
-							end if;
-			
-				elsif NextCtx=12 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+7;
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-								if SysRam.I.Data_out(5)='1' then  --spawned
-									NextCtx:=NextCtx+1;
-									intercomm<=1;
-								end if;
-								Interf.O.membusy<='0';
-						  else
-						    NextCtx:=11;
-							end if;	
-				elsif NextCtx=13 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+8;
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-								Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils
-								NextCtx:=NextCtx+1;
-									
-							end if;
-								Interf.O.membusy<='0';
-								
-				elsif NextCtx=14 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+8;
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-								Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils									
-								NextCtx:=NextCtx+1;
-								
-								end if;
-								Interf.O.membusy<='0';
-															
-				elsif NextCtx =15 then
-							Interf.O.Instr_En<='0';
-							Interf.O.membusy<='0';
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='0';
-							NextCtx:=0;
-							--array_of_errcodes<=0;
-				end if;
-				array_of_errcodes<=NextCtx;
- end procedure;
- 
-procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is
-variable i,dcount,wcount : natural range 0 to 255:=0;	
-variable adresse :natural;
-variable LRam : typ_dpRam;
-variable W0 :std_logic_vector(Word-1 downto 0);
-variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN));
-begin
-				init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN));
-				LRam:=SysRam; -- nécessaire pour le débogage
-				if NextCtx =0 then
-					
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.S.IntState1<=0;
-					NextCtx:=1;
-					adresse:=core_init_adr;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					
-				elsif NextCtx=1 then --écriture du ptr d'intruction
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					if interf.I.ramsel='0' then
-					
-					adresse:=core_init_adr;
-				
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					Interf.O.membusy<='1';
-					
-				  wcount:=Interf.S.IntState1;
-          WritePtr (Init_adr,wcount,SysRam);
-          Interf.S.IntState1<=wcount;
-          
-            if wcount =0 then 
-                  NextCtx:=2;
-                  Interf.S.IntState1<=0;
-                  adresse:=core_init_adr;
-                  SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-            end if;		
-         end if;       
-				elsif NextCtx=2 then 
-				  if interf.I.ramsel='0' then
-					   SysRam.O.we<='1';
-					   SysRam.O.ena<='1';
-					   SysRam.O.enb<='0';
-				      adresse:=core_init_adr;
-					   SysRam.O.Data_in<=MPI_INIT & x"0" ;
-					   SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					   NextCtx:=3;
-					   Interf.O.membusy<='1';
-					end if;
-				elsif NextCtx=3 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_init_adr+1;
-					SysRam.O.Data_in<= x"04" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-					end if;
-				elsif NextCtx=4 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					Interf.O.membusy<='1';
-					SysRam.O.enb<='0';
-					adresse:=core_init_adr+1;
-				  Interf.O.Instruction<=x"04";
-					SysRam.O.Data_in<=x"04" ;--longueur de l'instruction
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=5;
-					end if;
-				elsif NextCtx=5 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					Interf.O.membusy<='1';
-					SysRam.O.enb<='0';
-				  adresse:=core_init_adr+2;
-					SysRam.O.Data_in<= x"00" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=6;
-					end if;
-				elsif NextCtx=6 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_init_adr+3;
-					SysRam.O.Data_in<=x"00" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=7;
-        end if;
-				elsif NextCtx=7 then --fin de la fonction
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							Interf.O.membusy<='0';
-							dcount:=0;
-							Interf.O.membusy<='0';
-							Interf.O.Instruction(6)<=Interf.I.Spawned; --- préciser que la HT est dynamique
-							Interf.O.Instr_En<='1';
-							SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen));
-							NextCtx:=8;
-				elsif NextCtx=8 then --acquittement de la copie des données dans le tampon
-							if Interf.I.Instr_ack='1' then
-								Interf.O.Instr_En<='0';
-								NextCtx:=9;
-							end if;
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							
-				elsif NextCtx=9 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen));
-								if SysRam.I.Data_out(4)='1' then 
-									NextCtx:=10;
-									Interf.S.IntState1<=0; -- initialisation du compteur d'état
-								end if;
-								Interf.O.membusy<='0';
-							end if;								
-				elsif NextCtx =10 then
-							dcount:=Interf.S.IntState1; --permet de sauvegarder l'état interne du compteur
-							readmem(dcount,interf,sysRam,init_Adr,w0);
-							Interf.S.IntState1<=dcount;
-							w0:=SysRam.I.Data_out;
-							if dcount=0 then
-								Interf.I.ismain<=all_zeros(SysRam.I.Data_out(3 downto 0));--Rank=0 -> MainLib
-								NextCtx:=NextCtx+1;
-							end if;								
-				elsif NextCtx =11 then
-							Interf.O.Instr_En<='0';
-							Interf.O.membusy<='0';
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='0';
-							NextCtx:=0;
-				end if;
-							
-				
-end procedure;
-
-
-procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; Data:in std_logic_vector) is
---cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle)
---en ayant vérifié que le bus est bien disponible pour l'écriture
- variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect;
-
-begin
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-					dcount:=NextCtx;
-				else
-					
-					
-				end if;
-				
-							
-				if dcount=0 then
-					if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						Interf.O.membusy<='1';
-					end if;
-						SysRam.O.Data_in<=AdrToSet(Word-1 downto 0);					
-						SysRam.O.Addr_wr<=adrToSet;
-				elsif dcount=1 then
-						if interf.I.ramsel='0' then 
-							Interf.O.membusy<='1';
-							dcount :=dcount+1;
-						end if;
-						SysRam.O.Data_in<=data;
-						SysRam.O.Addr_wr<=adrToSet;
-				elsif dcount=2 then
-						SysRam.O.Data_in<=data;
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=AdrToSet;
-				elsif dcount=3 then
-						Interf.O.membusy<='1';
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=adrToSet;
-						SysRam.O.Data_in<=data;
-				elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						Interf.O.membusy<='0';
-						SysRam.O.Addr_wr<=AdrToSet;		
-				end if;
-					
-					NextCtx:=dcount;
-end procedure;
-
--- écriture dans la mémoire
-procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; data: out std_logic_vector) is
---cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle)
---en ayant vérifié que le bus est bien disponible pour l'écriture
- variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect;
-
-begin
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-					dcount:=NextCtx;
-				else
-					
-					
-				end if;
-							
-				if dcount=0 then
-					if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						Interf.O.membusy<='1';
-					end if;
-											
-						SysRam.O.Addr_rd<=adrToSet;
-				elsif dcount=1 then
-						data:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrToSet;
-				elsif dcount=2 then
-						data:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrToSet;
-				elsif dcount=3 then
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrToSet;
-						data:=SysRam.I.Data_out;
-						Interf.O.membusy<='0';
-						end if;
-				elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						Interf.O.membusy<='0';
-						data:=SysRam.I.Data_out;
-				end if;
-					data:=SysRam.I.Data_out;
-					NextCtx:=dcount;
-end procedure;
-
-procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-		variable				AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is
---cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle)
---en ayant vérifié que le bus est bien disponible pour l'écriture
- variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable tempdata:std_logic_vector(Word-1 downto 0);
-
-
-begin
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-					dcount:=NextCtx;
-				else
-					
-					
-				end if;
-							
-				if dcount=0 then
-					if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						Interf.O.membusy<='1';
-					end if;
-											
-						SysRam.O.Addr_rd<=adrVect;
-						SysRam.O.Addr_Wr<=adrVect;
-				elsif dcount=1 then
-				  	if interf.I.ramsel='0' then
-						tempdata:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrVect;
-						end if;
-						SysRam.O.enb<='1';
-						SySRam.O.ena<='0';
-						SysRam.O.we<='0';
-				elsif dcount=2 then
-						tempdata:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrVect;
-						SysRam.O.enb<='1';
-						SySRam.O.ena<='0';
-						SysRam.O.we<='0';
-				elsif dcount=3 then
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_Wr<=adrVect;
-						SysRam.O.We<='0';
-						SysRam.O.ena<='0';
-						SysRam.O.enb<='1';
-						tempdata:=SysRam.I.Data_out;
-						Interf.O.membusy<='1';
-						end if;
-				elsif dcount=4 then
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_Wr<=adrVect;
-						SysRam.O.We<='1';
-						SysRam.O.ena<='1';
-						SysRam.O.enb<='1';
-						tempdata:=SysRam.I.Data_out;
-						if BitVal='1' then
-						  TempData:=Tempdata or BitMask;
-						else
-						 TempData:=TempData and not (BitMAsk);
-						end if;
-						SysRam.O.Data_in<=TempData;
-						Interf.O.membusy<='1';
-						end if;
-				elsif dcount=5 then --attente d'écriture
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrVect;
-						SysRam.O.We<='1';
-						SysRam.O.ena<='1';
-						--SysRam.O.Data_in<=TempData;
-						Interf.O.membusy<='1';
-						end if;
-				elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						Interf.O.membusy<='0';
-						SysRam.O.We<='0';
-						SysRam.O.ena<='0';
-						
-				end if;
-					
-					NextCtx:=dcount;
-end procedure;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram) is
---cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle)
---les données de l'appel de la procédure
-variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect;
-begin
-				if count /=0 then --préserver la valeur de count entre les appels
-					dcount:=count;
-				else
-					
-					
-				end if;
-				adresse:=Core_base_adr+2;
-				AdrToSet:=AdrVect;	
-				if dcount=0 then
-						SysRam.O.Data_in<=AdrToSet(Word-1 downto 0);
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-				elsif dcount=1 then
-				 
-				    SysRam.O.Data_in<=AdrToSet(Word-1 downto 0);
-				    SysRam.O.We<='1';SysRam.O.Ena<='1';
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-						
-				elsif dcount=2 then
-				    SysRam.O.We<='1';SysRam.O.Ena<='1';
-				    SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word);
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN));
-						SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word);
-				elsif dcount=3 then
-						dcount :=dcount+1;
-						SysRam.O.We<='1';SysRam.O.Ena<='1';
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN));
-						SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word);
-				elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						SysRam.O.We<='0';SysRam.O.Ena<='0';
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN));		
-				end if;
-					
-					count:=dcount;
-end procedure;
-end MPI_Rma;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_RMA.vhd.bak
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MPI_RMA.vhd.bak	(revision 97)
+++ 	(revision )
@@ -1,1774 +1,0 @@
---	Package File Template
---
---	Purpose: This package defines supplemental types, subtypes, 
---		 constants, and functions 
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-Library NocLib;
-use NocLib.CoreTypes.all;
-use work.PACKET_TYPE.all;
-
-package Mpi_Rma is
-procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram);
-procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram);
-procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural);
-
-procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural);
-procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector );
-
-procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-									base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; 
-									info:natural; comm:Mpi_Comm; Win: inout MPI_Win );
-procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win);
-procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win);
-procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win);
-procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win);
-procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;  
-command : natural;  argv :natural; maxprocs : natural;  info : natural; root : natural;   comm : natural;  
-signal intercomm :out natural; signal  array_of_errcodes : out natural);
--- declare functions and procedure	 
- procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; data: out std_logic_vector);
-procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; Data:in std_logic_vector);						
-
-procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-				variable	AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic);
-
-end MPI_Rma;
-
-
-package body MPI_Rma is
-----int MPI_Put(
---  void *origin_addr,
---  int origin_count,
---  MPI_Datatype origin_datatype,
---  int target_rank,
---  MPI_Aint target_disp,
---  int target_count,
---  MPI_Datatype target_datatype,
---  MPI_Win win
---);
--- Example 1
-procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural) is
-variable i,dcount,wr_state : natural:=0;
-variable adresse :natural;
-variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr;
-variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp;
-variable put_adr : std_logic_vector (ADRLEN-1 downto 0);
-variable config_reg: std_logic_vector (Word-1 downto 0);
-constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');
-	begin   
-				put_adr:=conv_Std_logic_vector(Core_put_adr,ADRLEN);
-				
-				addr1:=Orig_Addr;
-				addr2:=Target_Disp;
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-				dcount:=NextCtx;
-				end if;
---					
-					
-				if rising_edge(clkin) then		
-				  if dcount= 0 then
-				      dcount:=dcount+1;
-				      Interf.S.Intstate1<=0;
-					elsif dcount>=1 and dcount <=3 then 
-									if interf.I.ramsel='0' then
-											Interf.O.membusy<='0';
-											--SysRam.O.we<='1';
-											--SysRam.O.ena<='1';
-											SysRam.O.enb<='1';
-											wr_state:=interf.S.Intstate1;
-											WritePtr (put_adr,wr_state,SysRam);
-											interf.S.Intstate1<=wr_state;
-											if wr_state =0 then 
-												-- fin de l'écriture du pointeur en mémoire 
-											dcount:=4;
-											end if;								
-									end if;
-							
-							elsif dcount=4 then
-							if interf.I.ramsel='0' then
-								SysRam.O.we<='1';
-								SysRam.O.ena<='1';
-								SysRam.O.enb<='0';
-								Interf.O.membusy<='1';
-								if target_rank <=15 then --limitation de cete version à 16 rang
-								Interf.S.Gstart(Target_rank)<='1';
-								end if;
-								adresse:=core_put_adr;
-								SysRam.O.Data_in<=MPI_PUT & conv_std_logic_vector(Target_Rank,4); --code fonction
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-							end if;
-							elsif dcount=5 then 
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+1;
-								SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								Interf.O.Instruction<=x"06"; -- nombre de mots de l'instruction
-								end if;
-							elsif dcount=6 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+2;
-								SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=7 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+3;
-								SysRam.O.Data_in<=Addr1(Word-1 downto 0);  --source Bas
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=8 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+4;
-								SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=9 then
-								if interf.I.ramsel='0' then
-								adresse:=core_put_adr+5;
-								SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=10 then
-								
-								SysRam.O.we<='1';
-								SysRam.O.ena<='1';
-								SysRam.O.enb<='1';
-								if interf.I.ramsel='0' then
-								adresse:=core_base_adr+1;
-								SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire;
-								Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction
-								Interf.O.membusy<='0';
-								dcount:=dcount+1;
-								end if;
-							elsif dcount=11 then
-								if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ?
-									Interf.O.Instr_En<='0';   --désactiver la prise en compte de l'instruction
-									dcount:=dcount+1;
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-								else
-								  Interf.O.Instr_En<='1'; 
-								end if;
-									adresse:=core_base_adr+1;
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-									SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									--SysRam.O.Ram_busy<='0'; --??
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';  -- préparer la lecture du résultat du Put
-									SysRam.O.enb<='1';						
-							elsif dcount=12 then
-									adresse:=core_base_adr+1;
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';  -- préparer l'écriture du résultat du Put
-									SysRam.O.enb<='1';
-									if interf.I.ramsel='0' then
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-									dcount:=dcount+1;
-									Interf.O.membusy<='1';
-									end if;
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-							elsif dcount=13 then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';  -- préparer l'écriture du résultat du Put
-									SysRam.O.enb<='0';
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-									dcount:=dcount+1;
-									adresse:=core_base_adr+1;
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-							elsif dcount=14 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen));
-										if SysRam.I.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie !
-											dcount:=dcount+1;
-											SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-										  Interf.S.Intstate2<=255; --timer pour la réception
-										  interf.s.tmem(0)<=x"02";
-										end if;
-									end if;
-							elsif dcount=15 or dcount=16 or dcount=17 then
-							  SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-							  SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-							   -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse
-						 
-						   if interf.I.ramsel='0' then 
-							  dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse
-							  
-						    elsif Interf.S.Intstate2>0  then 
-						      dcount:=15;
-										  Interf.S.Intstate2<=Interf.S.Intstate2-1;
-								elsif interf.s.tmem(0)>0 then
-										    interf.s.tmem(0)<=interf.s.tmem(0)-1;
-										    Interf.S.Intstate2<=255;
-										    dcount:=15;
-								else
-										   dcount:=1;--recommencer l'envoi
- 								end if;
-							elsif dcount=18 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-										if SysRam.I.Data_out(5)='1' then --Message  du MPI PUT bien reçu !
-											dcount:=dcount+1;
-											SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen);
-										elsif Interf.S.Intstate2>0  then 
-										  Interf.S.Intstate2<=Interf.S.Intstate2-1;
-										 elsif interf.s.tmem(0)>0 then
-										    interf.s.tmem(0)<=interf.s.tmem(0)-1;
-										    Interf.S.Intstate2<=255;
-										  else
-										   dcount:=1;--recommencer l'envoi
- 										end if;
- 									else
- 									  dcount:=15;
-									end if;
-							elsif dcount=19 then	
-									dcount:=0; --fin normale de la fonction
-									Interf.O.membusy<='0';
-							end if;
-							
-							
-						  NExtCtx:=dcount;
-				end if;
-	end procedure;
-
-procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram;
- Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural;
-  Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural;
-  Target_Datatype :natural; Win : natural) is
-variable i,wcount,dcount : natural range 0 to 255:=0;
-variable adresse :natural;
-variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0');
-variable bitval : std_logic:='0';
-variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr;
-variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp;
-variable get_adr : std_logic_vector (ADRLEN-1 downto 0);
-variable config_reg,win_reg: std_logic_vector (Word-1 downto 0);
-constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');
-	begin   
-				get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN));
-				
-				addr1:=Orig_Addr;
-				addr2:=Target_Disp;
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-				dcount:=NextCtx;
-				end if;
---					
-					
-				if rising_edge(clkin) then		
-							
-						if dcount =0 then	
-							dcount:=dcount+1;
-							Interf.S.IntState1<=0;
-						elsif dcount>=1 and dcount <=3 then 
-									if interf.I.ramsel='0' then
-											SysRam.O.we<='1';
-											SysRam.O.ena<='1';
-											SysRam.O.enb<='0';
-											wcount:=Interf.S.IntState1;
-											WritePtr (get_adr,wcount,SysRam);
-											Interf.S.IntState1<=wcount;
-											Interf.O.membusy<='1';
-											if wcount =0 then 
-												dcount:=4;
-												Interf.S.Intstate1<=1;
-											end if;	
-										else 
-										  Interf.S.IntState1<=0;
-																	
-									end if;
-							
-							elsif dcount=4 then
-							if interf.I.ramsel='0' then 
-								SysRam.O.we<='1';
-								SysRam.O.ena<='1';
-								SysRam.O.enb<='0';
-								if target_rank <=15 then --limitation de cete version à 16 rang
-								Interf.S.Gstart(Target_rank)<='1';
-								end if;
-								adresse:=core_get_adr;
-								SysRam.O.Data_in<=MPI_GET & conv_Std_logic_vector(Target_Rank,4); --code fonction
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								Interf.O.membusy<='1';
-								dcount:=dcount+1;
-							end if;
-							elsif dcount=5 then 
-								if interf.I.ramsel='0' then	 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+1;
-									SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								  interf.O.Instruction<=x"06"; --le nbre de mots de l'intstruction
-									dcount:=dcount+1;
-								end if; 
-							elsif dcount=6 then
-								if interf.I.ramsel='0' then 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+2;
-									SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									
-									dcount:=dcount+1;
-
-								end if;
-							elsif dcount=7 then
-								if interf.I.ramsel='0' then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+3;
-									SysRam.O.Data_in<=Addr1(Word-1 downto 0);  --source Bas
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									
-									dcount:=dcount+1;
-								end if;
-							elsif dcount=8 then
-								if interf.I.ramsel='0' then 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';					
-									adresse:=core_get_adr+4;
-									SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									Interf.O.membusy<='1';
-									dcount:=dcount+1;
-								end if;
-							elsif dcount=9 then
-								if interf.I.ramsel='0' then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+5;
-									SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									Interf.O.membusy<='1';
-									dcount:=dcount+1;
-								end if;
-								elsif dcount=10 then
-								if interf.I.ramsel='0' then
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									adresse:=core_get_adr+7;
-									SysRam.O.Data_in<=x"00"; -- résultat du GET
-									SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									Interf.O.membusy<='1';
-									Interf.S.IntState2<=0;
-									dcount:=dcount+1;
-								end if;
-							elsif dcount=11 then
-								 
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';
-									SysRam.O.enb<='1';
-									addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN));
-									wcount:=Interf.S.IntState2;
-									wdata:=x"01";bitval:='1';
-									setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval);
-									Interf.S.IntState2<=wcount;
-									if wcount=0 then
-									  dcount:=dcount+1;
-									  Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction
-									 end if;
-
-							elsif dcount=12 then
-								if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ?
-									Interf.O.Instr_En<='0';   --désactiver la prise en compte de l'instruction
-									dcount:=dcount+1;
-									config_reg:=SysRam.I.Data_out and x"f6";
-									--SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-								end if;
-									adresse:=core_base_adr+1;
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN));
-									SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									--SysRam.O.Ram_busy<='0'; --??
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';  -- préparer la lecture du résultat du get
-									SysRam.O.enb<='1';	
-									Interf.O.membusy<='0';
-							elsif dcount=13 then
-								
-									adresse:=core_base_adr+1;
-									SysRam.O.we<='1';
-									SysRam.O.ena<='1';  -- préparer l'écriture du résultat du get
-									SysRam.O.enb<='1';
-									SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN));
-									SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-
-								if interf.I.ramsel='0' then 	
-									config_reg:=SysRam.I.Data_out and x"f6";
-									SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-									dcount:=dcount+1;
-									Interf.O.membusy<='1';
-								end if;
-										Interf.s.IntState2<=255;
-										Interf.s.tmem(0)<=x"08"; --tempo pour l'attente du résultat de Get							
-							elsif dcount=14 then
-									 
-										SysRam.O.we<='1';
-										SysRam.O.ena<='1';  -- préparer l'écriture du résultat du GET
-										SysRam.O.enb<='0';
-										adresse:=core_base_adr+1;
-										SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out and x"f6";
-										SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0;
-										dcount:=18;--dcount+1;
-										Interf.O.membusy<='1';
-						
-									end if;
-							elsif dcount=15 then
-									 
-										SysRam.O.we<='0';
-										SysRam.O.ena<='0';  -- préparer l'écriture du WBusy
-										SysRam.O.enb<='1';
-										adresse:=core_base_adr+5;
-										SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-										SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy
-										SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy
-										dcount:=dcount+1;
-										Interf.O.membusy<='1';
-									end if;
-							elsif dcount=16 then
-									 
-										SysRam.O.we<='0';
-										SysRam.O.ena<='0';  -- préparer l'écriture du WBusy
-										SysRam.O.enb<='1';
-										adresse:=core_base_adr+5;
-										SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy
-										SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy
-										dcount:=dcount+1;
-										Interf.O.membusy<='1';
-								
-									end if;
-							elsif dcount=17 then
-									 
-										SysRam.O.we<='1';
-										SysRam.O.ena<='1';  -- préparer l'écriture du résultat du GET
-										SysRam.O.enb<='1';
-										adresse:=core_base_adr+5;
-										SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-									if interf.I.ramsel='0' then
-										config_reg:=SysRam.I.Data_out or x"40";
-										SysRam.O.Data_in<=config_reg ; --;
-										dcount:=dcount+1;
-										Interf.O.membusy<='1';
-									end if;
-							elsif dcount>=18 and dcount <=21 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen));
-										if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie !
-											dcount:=dcount+1;
-										end if;
-									end if;
-	         elsif dcount>=22 and dcount <=24 then	
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='1';
-									Interf.O.membusy<='0';
-									SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen);
-									if interf.I.ramsel='0' then 
-										SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen);
-										if SysRam.I.Data_out(5)='1' then --Message  du MPI Get bien reçu !
-											dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème !
-											SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen);
-										elsif Interf.S.Intstate2>0 then 
-										  Interf.S.Intstate2<=Interf.S.Intstate2-1;
-										 elsif interf.s.tmem(0)>0 then
-                          interf.s.tmem(0)<=interf.s.tmem(0)-1;
-                          Interf.S.Intstate2<=255;
-										  else
-										   dcount:=1;--recommencer l'envoi
- 										end if;
-									end if;
-							
-							elsif dcount=25 then	
-									dcount:=0; --fin normale de la fonction
-									Interf.O.membusy<='0';
-									SysRam.O.we<='0';
-									SysRam.O.ena<='0';
-									SysRam.O.enb<='0';
-							end if;
-
-						  NExtCtx:=dcount;
-			end if; 
-	end procedure; 
-Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is 
-Begin
---cette procédure permet de récupérer le groupe qui est associé à un communicateur
---dans notre cas c'est la récupération du groupe associé à COMM_WORLD
-end procedure;
---int MPI_Group_incl(MPI_Group group, int n, int *ranks,
---    MPI_Group *newgroup)
-Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram;
-									GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is
-Begin
--- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks
--- et d'activer l'un des  bits de position de newgroup. 
--- 
---
-end procedure;
-								
-procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is
-variable adresse_rd : natural range 0 to 2**ADRLEN-1;	
-
-begin
-
-		if NextCtx =0 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			
-				NextCtx:=1;
-		
-		elsif NextCtx=1 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				NextCtx:=2;
-				Interf.O.membusy<='1';
-			end if;	
-		elsif NextCtx=2 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0));
-				NextCtx:=3;
-				Interf.O.membusy<='1';
-			end if;	
-		elsif NextCtx=3 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0));
-				NextCtx:=4;
-				Interf.O.membusy<='1';
-			end if;	
-		elsif NextCtx=4 then
-			SysRam.O.we<='0';
-			SysRam.O.ena<='0';
-			SysRam.O.enb<='1';
-			adresse_rd:=CORE_INIT_ADR+1;
-			SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN));
-			if interf.I.ramsel='0' then
-				Rank<=SysRam.I.Data_out(3 downto 0);
-				Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0));
-				NextCtx:=0;
-				Interf.O.membusy<='0';
-			end if;	
-		end if;
-end procedure;
-
---int MPI_Win_create(
---  void *base,
---  MPI_Aint size,
---  int disp_unit,
---  MPI_Info info,
---  MPI_Comm comm,
---  MPI_Win *win
---);
-procedure pMPI_Win_create(NextCtx : inout natural ;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-									base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; 
-									info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is
- -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre
- -- si fenêtre libre trouvée, et 
- -- mise à 1 du Bit WCreate du registre status
- type wtype is array (1 to 4 ) of natural range 0 to 255;
- variable AdrWin: std_logic_vector(ADRLEN-1 downto 0);
- variable adresse : std_logic_vector(ADRLEN-1 downto 0);
- variable clkin : std_logic:='1';
- variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN));
- variable w0 : std_logic_vector(Word-1 downto 0);
- variable adrnat : natural;
- variable sizewin : std_logic_vector(Word-1 downto 0);
- variable count : natural range 0 to 255;
- variable wdisp  :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre
-begin
--- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner 
--- le pointeur qui permet de le décrire 
-
-
-If NextCtx=0 then 
-	NExtCtx:=NextCtx+1;
-	count:=0;
-	Interf.O.membusy<='0';
-	Interf.S.IntState1<=count;
-elsif NextCtx>=1 and NextCtx <= 4 then
-	count:=Interf.S.IntState1;
-	AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16));
-	 readmem(count,interf,sysRam,AdrWin,w0);
-		if count=0 then
-			if w0(0)/='1' then -- cette fenêtre est libre
-				NextCtx:=6; --étape de la création de la fenêtre
-				Win.addr:=base; --l'adresse de la fenêtre
-				Win.id:=NextCtx; -- la référence provisoire de la fenêtre
-				Win.size:=Size; -- la taille de la fenêtre
-				
-			else
-				NextCtx:=NextCtx+1;
-			end if;
-		end if;
-		Interf.S.IntState1<=count;--sauvegarde du statut de la sous-procédure
-		
-elsif NextCtx=5 then
-	-- Plus de fenêtre disponible erreur
-		NextCtx:=1; -- boucle sans fin :)
-		Win.id:=0;
-		Win.addr:=x"0000";
-elsif NextCtx=6 then
-		--Affectation de l'objet Windows car une place est disponible
-		count:=Interf.S.IntState1;
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-		
-elsif NextCtx=8 then
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		interf.S.winid<=interf.S.winid+1;
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,AdrWin+1,stdlv(interf.S.winid,8)); --win id de la fenêtre
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=9 then
-
-		adrnat:=Core_base_adr+Wdisp(Win.id);
-		
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		count:=Interf.S.IntState1;
-		
-		
-		Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=10 then
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=11 then
-		AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16));
-		sizewin:=std_logic_vector(to_unsigned(size,8));
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-elsif NextCtx=12 then	
-	--cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer
-	-- les informations donnant le numéro de la fenêtre
-		W0:=MPI_WIN_CREATE & std_logic_vector(to_unsigned(0,4)); --code fonction
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,wcreate_adr,w0);
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-		
-	elsif NextCtx=13 then 
-		w0:=std_logic_vector(to_unsigned(Win.Id,8));							-- id proposé pour la fenêtre en création
-		count:=Interf.S.IntState1;
-		Writemem(count,interf,SysRam,wcreate_adr+1,w0);
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-	elsif NextCtx=14 then
-		SysRam.O.we<='1';
-		SysRam.O.ena<='1';
-		SysRam.O.enb<='0';
-		count:=Interf.S.IntState1;
-		if interf.I.ramsel='0' then
-			WritePtr (wcreate_adr,count,SysRam); --écriture du pointeur d'instruction
-			Interf.S.IntState1<=count;
-			if count=0 then
-				NextCtx:=NextCtx+1;
-			end if;
-		end if;
-	elsif NextCtx=15 then
-									-- il faut mettre instruction_en à 1
-				SysRam.O.we<='0';
-				SysRam.O.ena<='0';
-				SysRam.O.enb<='1';
-				SysRam.O.we<='1';
-				SysRam.O.ena<='1';
-				SysRam.O.enb<='1';
-				adresse:=stdlv(core_base_adr+1);
-								SysRam.O.addr_rd<=adresse;
-								SysRam.O.Addr_wr<=adresse;
-								SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire;
-		Writemem(count,interf,SysRam,adresse,x"01");
-		Interf.S.IntState1<=count;
-		if count=0 then
-			NextCtx:=NextCtx+1;
-		end if;
-				Interf.O.Instr_En<='1';
-				adresse:=stdlv(core_base_adr);
-				SysRam.O.Addr_rd<=adresse;
-				NextCtx:=NextCtx+1;
-	elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib
-				if Interf.I.Instr_ack='1' then
-					Interf.O.Instr_En<='0';
-					NextCtx:=NextCtx+1;
-				end if;
-				SysRam.O.we<='0';
-				SysRam.O.ena<='0';
-				SysRam.O.enb<='1';
-	elsif NextCtx=17 then
-			-- lecture du résultat de l'instruction
-			
-	
-else
-	
-end if;
-end procedure;
---int MPI_Win_start(
---  MPI_Group group,
---  int assert,
---  MPI_Win win
---);
-procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is
---cette fonction active les bits WStart pour chaque processus avec lequel 
--- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à
---chacune de ces cibles
- variable dcount : natural range 0 to 255:=0;
- variable cstatus : std_logic_vector(Word-1 downto 0);
- begin
-
- -- retour de l'adresse de de la fenêtre dans la structure Win
- -- initialisation des bits concernant 
- 
- if NextCtx =0 then 
-			NextCtx:=NextCtx+1;
-		elsif NextCtx=1 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-					SysRam.O.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits	
-							
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';		
-					Interf.S.GStart<=(others=>'0');				
-			end if;
-	elsif NextCtx=2 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-					SysRam.O.Data_in<=x"01";
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-		elsif NextCtx=3 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-					SysRam.O.Data_in<=x"01";
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-	elsif NextCtx=4 then
-		NextCtx:=0;
-		Interf.O.membusy<='0';
-		SysRam.O.we<='0';
-		SysRam.O.ena<='0';
-	end if;
-
- 
- end procedure;
-procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is
-variable adresse :natural;
-variable wcount: natural range 0 to 255:=0;
-variable LRam : typ_dpRam;
-variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation
-variable W0 :std_logic_vector(Word-1 downto 0);
-variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN));
-
-begin
-  --
-  				wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN));
-				LRam:=SysRam; -- nécessaire pour le débogage
-				if NextCtx =0 then
-					
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='0';
-					Interf.O.MemBusy<='1'; --occuper la mémoire
-					Interf.S.IntState1<=0;
-					NextCtx:=1;
-					adresse:=core_wcompl_adr;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					
-				elsif NextCtx=1 then --écriture du ptr d'intruction
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					if interf.I.ramsel='0' then
-					
-					adresse:=core_wcompl_adr;
-				
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					Interf.O.membusy<='1';
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-				  wcount:=Interf.S.IntState1;
-          WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir
-          Interf.S.IntState1<=wcount;
-          
-            if wcount =0 then 
-                  NextCtx:=2;
-                  Interf.S.IntState1<=0;
-                  Interf.S.IntState2<=0;
-                  Interf.S.tmem(0)<=Interf.S.GStart(7 downto 0); --cibles impactées
-                  Interf.S.tmem(1)<=Interf.S.GStart(15 downto 8); --cibles impactées
-                  adresse:=core_wcompl_adr;
-                  SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-            end if;	
-      else
-        Interf.S.IntState1<=0; --recommencer l'écriture du pointeur	
-         end if;       
-				elsif NextCtx=2 then 
-					if 	Interf.I.Ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_wcompl_adr;
-				  NextCtx:=10; --aller à la fin de la fonction
-				  i:=0;
-				  l1:for i in 0 to 7 loop
-				  --  i:=i+1;
-				  if i>=interf.s.intState2 then 				  
-				  if interf.s.gstart(i)='1' then
-					SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4));
-					Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4));
-
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.S.tmem(0)(i)<='0'; --ce dest a été traité !
-					NextCtx:=4;
-					Interf.S.IntState2<=i+1;
-					exit l1;
-					end if;
-					end if;
-					exit l1 when i=7;
-					end loop l1;
-					end if;
-				elsif NextCtx=3 then 
-					if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';	
-				  adresse:=core_wcompl_adr;
-				  wcount:=Interf.S.IntState1;
-          WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir
-          Interf.S.IntState1<=wcount;
-					SysRam.O.Data_in<= Interf.S.tmem(2);
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					if wcount=0 then 
-					 NextCtx:=NextCtx+1;
-					 end if;
-					end if;
-				elsif NextCtx=4 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';	
-				  adresse:=core_wcompl_adr+1;
-					SysRam.O.Data_in<= x"04" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-				elsif NextCtx=5 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-					adresse:=core_wcompl_adr+2;
-				  Interf.O.Instruction<=x"04";--longueur de l'instruction
-					SysRam.O.Data_in<=x"00" ;--
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=6;
-				elsif NextCtx=6 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_wcompl_adr+3;
-					SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4));
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=7;
-				elsif NextCtx=7 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-				  adresse:=core_wcompl_adr+3;
-					SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4));
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-
-				elsif NextCtx=8 then --fin de la fonction
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							--dcount:=0;
-							Interf.O.membusy<='0';
-							Interf.O.Instr_En<='1';
-							SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen));
-							NextCtx:=NextCtx+1;
-				elsif NextCtx=9 then --acquittement de la copie des données dans le tampon
-							if Interf.I.Instr_ack='1' then
-								Interf.O.Instr_En<='0';
-								NextCtx:=10;
-							end if;
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							
-				elsif NextCtx=10 then --lecture de la fin de WComplete
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							Interf.O.membusy<='0';
-							if interf.S.IntState2=0 then --aucune instruction MPI exécutée ?
-							  NextCtx:=12;
-							elsif Interf.S.tmem(0)/=0 then --plus de message compl à envoyer
-							   NextCtx:=2;
-							 elsif Interf.S.tmem(0)=0 then
-							   if interf.I.ramsel='0' then
-							       NextCtx:=NextCtx+1;
-          							   SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-							   end if;
-							 end if; 
-				elsif NextCtx=11 then --test de la fin des transferts
-					if interf.I.ramsel='0' then
-        					SysRam.O.we<='0';
-        					SysRam.O.ena<='0';
-        					SysRam.O.enb<='1';
-        					SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen));
-        							if SysRam.I.Data_out(0)='1' and  SysRam.I.Data_out(6)='0' then --si WStart=1 et Wbusy=0
-        							  --il faut un DSent=1 pour Put ou un DSending pour Get
-										if SysRam.I.Data_out(5)='1' or  (SysRam.I.Data_out(4)='1' and SysRam.I.Data_out(1)='1')  then 
-												NextCtx:=NextCtx+1;
-										end if;	
-									end if;									
-				
-					end if;	
-				elsif NextCtx=12 then
-									Interf.S.IntState1<=0; -- initialisation du compteur d'état
-								Interf.S.IntState2<=0;
-									SysRam.O.enb<='0';
-								NextCtx:=0; --fin de la fonction			
-      end if;
-
-end procedure;
-procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is
---cette fonction active les bits WStart pour chaque processus avec lequel 
--- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à
---chacune de ces cibles
- variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire 
- variable dcount : natural range 0 to 255:=0;
- variable cstatus : std_logic_vector(Word-1 downto 0);
- begin
-
- -- retour de l'adresse de de la fenêtre dans la structure Win
- -- initialisation des bits concernant 
- if Win.id =0 then
-   W_ptr:=Core_Base_Adr+4;
- end if;
- if NextCtx =0 then 
-			
-			if pgroup.grp=0 then --rien à faire
-			  nextCtx:=5;
-			  Interf.S.GPost<=(others=>'0');
-			 else
-			   NextCtx:=NextCtx+1;
-			end if;
-		elsif NextCtx=1 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-					SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits	
-							
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';		
-									
-			end if;
-			 --limitation de cete version à 16 rang
-				Interf.S.GPost<=pgroup.grp;
-	elsif NextCtx=2 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-					SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits	
-							
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';		
-									
-			end if;						
-	elsif NextCtx=3 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_Ptr+W_Gpost,Adrlen));
-					SysRam.O.Data_in<=pgroup.grp(7 downto 0);
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-elsif NextCtx=4 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen));
-					SysRam.O.Data_in<=pgroup.grp(15 downto 8);
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-elsif NextCtx=6 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen));
-					SysRam.O.Data_in<=pgroup.grp(15 downto 8);
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';	
-			end if;
-	elsif NextCtx=5 then
-	         SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='0';
-		NextCtx:=0;
-		Interf.O.membusy<='0';
-	end if;
-
- 
- end procedure;
- 
- procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is
---permet de synchroniser la fin des opérations sur une fenêtre
-variable dcount : natural range 0 to 255:=0;
-variable cstatus : std_logic_vector(Word-1 downto 0);
-variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire
-begin
-	W_Ptr:=Core_base_adr+4;--adresse du reg status de la première fenêtre
-		if NextCtx =0 then 
-			NextCtx:=NextCtx+1;
-		elsif NextCtx=1 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='1';
-					NextCtx:=NextCtx+1;
-			end if;
-			     SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen));
-            If Interf.S.Gpost=0 then
-             NextCtx:=5; --rien à synchroniser
-          end if;
-  elsif (NextCtx>=2) and (NextCtx <=3) then
-    SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-    if interf.I.ramsel='0' then
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='1';
-					NextCtx:=NextCtx+1;
-		else
-		    NextCtx:=1;
-		   end if;
-		elsif NextCtx=4 then
-			if interf.I.ramsel='0' then
-					SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='1';
-					SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen));
-						
-							if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0
-							  --il faut un DSent=1 pour Put ou un DSending pour Get
-  							   if SysRam.I.Data_out(4)='1' or  (SysRam.I.Data_out(5)='1' and SysRam.I.Data_out(2)='1')  then 
-  									   NextCtx:=NextCtx+1;
-  									   Interf.S.GPost<=(others=>'0');
-  							   end if;	
-							elsif SysRam.I.Data_out(3)='0' then 
-              							  NextCtx:=NextCtx; --pas d'opérations en attente
-							else
-							  NextCtx:=NextCtx; --on attend
-							end if;	
-			else
-			 NextCtx:=2;		--retour à l'atente du Bit !
-			end if;	
-	
-	elsif NextCtx=5 then
-		      SysRam.O.we<='0';
-					SysRam.O.ena<='0';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='0';
-		      NextCtx:=0;
-	end if;
-
-
-end procedure;
-
-
- Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is
-  begin
- 
- end procedure;
- 
- procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;  
-command : natural;  argv :natural; maxprocs : natural;  info : natural; root : natural;   comm : natural;  
-signal intercomm :out natural; signal  array_of_errcodes : out natural) is
-
-variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable spawn_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN));
-begin
- spawn_adr:=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN));
-				if NextCtx =0 then
-					
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					NextCtx:=1;
-				elsif NextCtx=1 then 
-					if interf.I.ramsel='0' then
-					NextCtx:=2;
-					adresse:=core_spawn_adr;
-					SysRam.O.Data_in<=MPI_SPAWN & x"0" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.membusy<='1';
-					Interf.O.Instr_En<='0';
-					Interf.S.IntState2<=1; -- préparation de la destination du spawn
-					end if;
-				elsif NextCtx=2 then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					if interf.I.ramsel='0' then
-					NextCtx:=NextCtx+1;
-					Interf.O.membusy<='1';
-					adresse:=core_spawn_adr;
-					if interf.I.ismain='1' then ---déclanche l'éxécution de la commande
-						SysRam.O.Data_in<=MPI_spawn & x"0";--Std_logic_vector(to_unsigned(Interf.S.IntState2+2,4)) ;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-						
-					else -- envoie d'une commande spawn à la main lib
-						SysRam.O.Data_in<=MPI_spawn & x"0" ;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-						Interf.O.Instr_En<='0';
-						Interf.O.membusy<='1';
-						
-						end if;
-					end if;
-				
-				elsif NextCtx=3 then 
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					adresse:=core_spawn_adr;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-				elsif NextCtx=4 then	
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+1;
-								SysRam.O.Data_in<=std_logic_vector(to_unsigned(4,8)) ;--la longueur
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								Interf.O.Instruction<=x"04";
-								NextCtx:=NextCtx+1;
-					end if;
-				elsif NextCtx=5 then
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+2;
-								SysRam.O.Data_in<=std_logic_vector(to_unsigned(maxprocs,8)) ;--le nombre de processus
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								NextCtx:=NextCtx+1;
-					end if;
-				elsif NextCtx=6 then
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+3;
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction
-								NextCtx:=NextCtx+1;
-
-					end if;
-				elsif NextCtx=7 then
-					if interf.I.ramsel='0' then
-								adresse:=core_spawn_adr+3;
-								SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-								SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction
-								NextCtx:=NextCtx+1;
-                report "MPV SPAWN activé " & integer'image(interf.I.Rank);
-					end if;
-				elsif NextCtx=8 then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					dcount:=Interf.S.IntState1;
-					if interf.I.ramsel='0' then
-						SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN));
-						WritePtr (spawn_adr,dcount,SysRam);
-						Interf.O.Instr_En<='0';
-						Interf.O.membusy<='1';
-						Interf.S.IntState1<=dcount;
-						if dcount =0 then 
-								NextCtx:=NextCtx+1;
-						end if;
-					end if;
-				elsif NextCtx=9 then
-			
-				 --fin de la fonction
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							dcount:=0;
-							Interf.O.membusy<='0';
-							Interf.O.Instr_En<='1';
-							SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen));
-							NextCtx:=NextCtx+1;
-				elsif NextCtx=10 then --acquittement de la copie des données dans le tampon
-							if Interf.I.Instr_ack='1' then
-								Interf.O.Instr_En<='0';
-								NextCtx:=NextCtx+1;
-							end if;
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-				elsif NextCtx=11 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+7; 
-							SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-							if interf.I.ramsel='0' then 	
-									NextCtx:=NextCtx+1;
-							end if;
-			
-				elsif NextCtx=12 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+7;
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-								if SysRam.I.Data_out(5)='1' then  --spawned
-									NextCtx:=NextCtx+1;
-									intercomm<=1;
-								end if;
-								Interf.O.membusy<='0';
-						  else
-						    NextCtx:=11;
-							end if;	
-				elsif NextCtx=13 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+8;
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-								Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils
-								NextCtx:=NextCtx+1;
-									
-							end if;
-								Interf.O.membusy<='0';
-								
-				elsif NextCtx=14 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							adresse:=core_spawn_adr+8;
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen));
-								Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils									
-								NextCtx:=NextCtx+1;
-								
-								end if;
-								Interf.O.membusy<='0';
-															
-				elsif NextCtx =15 then
-							Interf.O.Instr_En<='0';
-							Interf.O.membusy<='0';
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='0';
-							NextCtx:=0;
-							--array_of_errcodes<=0;
-				end if;
-				array_of_errcodes<=NextCtx;
- end procedure;
- 
-procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is
-variable i,dcount,wcount : natural range 0 to 255:=0;	
-variable adresse :natural;
-variable LRam : typ_dpRam;
-variable W0 :std_logic_vector(Word-1 downto 0);
-variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN));
-begin
-				init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN));
-				LRam:=SysRam; -- nécessaire pour le débogage
-				if NextCtx =0 then
-					
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.S.IntState1<=0;
-					NextCtx:=1;
-					adresse:=core_init_adr;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					
-				elsif NextCtx=1 then --écriture du ptr d'intruction
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					if interf.I.ramsel='0' then
-					
-					adresse:=core_init_adr;
-				
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					Interf.O.Instr_En<='0';
-					Interf.O.membusy<='1';
-					
-				  wcount:=Interf.S.IntState1;
-          WritePtr (Init_adr,wcount,SysRam);
-          Interf.S.IntState1<=wcount;
-          
-            if wcount =0 then 
-                  NextCtx:=2;
-                  Interf.S.IntState1<=0;
-                  adresse:=core_init_adr;
-                  SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-            end if;		
-         end if;       
-				elsif NextCtx=2 then 
-				  if interf.I.ramsel='0' then
-					   SysRam.O.we<='1';
-					   SysRam.O.ena<='1';
-					   SysRam.O.enb<='0';
-				      adresse:=core_init_adr;
-					   SysRam.O.Data_in<=MPI_INIT & x"0" ;
-					   SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					   NextCtx:=3;
-					   Interf.O.membusy<='1';
-					end if;
-				elsif NextCtx=3 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_init_adr+1;
-					SysRam.O.Data_in<= x"04" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=NextCtx+1;
-					end if;
-				elsif NextCtx=4 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					Interf.O.membusy<='1';
-					SysRam.O.enb<='0';
-					adresse:=core_init_adr+1;
-				  Interf.O.Instruction<=x"04";
-					SysRam.O.Data_in<=x"04" ;--longueur de l'instruction
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=5;
-					end if;
-				elsif NextCtx=5 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					Interf.O.membusy<='1';
-					SysRam.O.enb<='0';
-				  adresse:=core_init_adr+2;
-					SysRam.O.Data_in<= x"00" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=6;
-					end if;
-				elsif NextCtx=6 then 
-				  if Interf.I.ramSel='0' then
-					SysRam.O.we<='1';
-					SysRam.O.ena<='1';
-					SysRam.O.enb<='0';
-					Interf.O.membusy<='1';
-				  adresse:=core_init_adr+3;
-					SysRam.O.Data_in<=x"00" ;
-					SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-					NextCtx:=7;
-        end if;
-				elsif NextCtx=7 then --fin de la fonction
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							Interf.O.membusy<='0';
-							dcount:=0;
-							Interf.O.membusy<='0';
-							Interf.O.Instruction(6)<=Interf.I.Spawned; --- préciser que la HT est dynamique
-							Interf.O.Instr_En<='1';
-							SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen));
-							NextCtx:=8;
-				elsif NextCtx=8 then --acquittement de la copie des données dans le tampon
-							if Interf.I.Instr_ack='1' then
-								Interf.O.Instr_En<='0';
-								NextCtx:=9;
-							end if;
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							
-				elsif NextCtx=9 then --lecture de la fin de l'initialisation
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='1';
-							if interf.I.ramsel='0' then 
-								SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen));
-								if SysRam.I.Data_out(4)='1' then 
-									NextCtx:=10;
-									Interf.S.IntState1<=0; -- initialisation du compteur d'état
-								end if;
-								Interf.O.membusy<='0';
-							end if;								
-				elsif NextCtx =10 then
-							dcount:=Interf.S.IntState1; --permet de sauvegarder l'état interne du compteur
-							readmem(dcount,interf,sysRam,init_Adr,w0);
-							Interf.S.IntState1<=dcount;
-							w0:=SysRam.I.Data_out;
-							if dcount=0 then
-								Interf.I.ismain<=all_zeros(SysRam.I.Data_out(3 downto 0));--Rank=0 -> MainLib
-								NextCtx:=NextCtx+1;
-							end if;								
-				elsif NextCtx =11 then
-							Interf.O.Instr_En<='0';
-							Interf.O.membusy<='0';
-							SysRam.O.we<='0';
-							SysRam.O.ena<='0';
-							SysRam.O.enb<='0';
-							NextCtx:=0;
-				end if;
-							
-				
-end procedure;
-
-
-procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; Data:in std_logic_vector) is
---cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle)
---en ayant vérifié que le bus est bien disponible pour l'écriture
- variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect;
-
-begin
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-					dcount:=NextCtx;
-				else
-					
-					
-				end if;
-				
-							
-				if dcount=0 then
-					if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						Interf.O.membusy<='1';
-					end if;
-						SysRam.O.Data_in<=AdrToSet(Word-1 downto 0);					
-						SysRam.O.Addr_wr<=adrToSet;
-				elsif dcount=1 then
-						if interf.I.ramsel='0' then 
-							Interf.O.membusy<='1';
-							dcount :=dcount+1;
-						end if;
-						SysRam.O.Data_in<=data;
-						SysRam.O.Addr_wr<=adrToSet;
-				elsif dcount=2 then
-						SysRam.O.Data_in<=data;
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=AdrToSet;
-				elsif dcount=3 then
-						Interf.O.membusy<='1';
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=adrToSet;
-						SysRam.O.Data_in<=data;
-				elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						Interf.O.membusy<='0';
-						SysRam.O.Addr_wr<=AdrToSet;		
-				end if;
-					
-					NextCtx:=dcount;
-end procedure;
-
--- écriture dans la mémoire
-procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-						AdrVect:in std_logic_vector; data: out std_logic_vector) is
---cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle)
---en ayant vérifié que le bus est bien disponible pour l'écriture
- variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect;
-
-begin
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-					dcount:=NextCtx;
-				else
-					
-					
-				end if;
-							
-				if dcount=0 then
-					if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						Interf.O.membusy<='1';
-					end if;
-											
-						SysRam.O.Addr_rd<=adrToSet;
-				elsif dcount=1 then
-						data:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrToSet;
-				elsif dcount=2 then
-						data:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrToSet;
-				elsif dcount=3 then
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrToSet;
-						data:=SysRam.I.Data_out;
-						Interf.O.membusy<='0';
-						end if;
-				elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						Interf.O.membusy<='0';
-						data:=SysRam.I.Data_out;
-				end if;
-					data:=SysRam.I.Data_out;
-					NextCtx:=dcount;
-end procedure;
-
-procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
-		variable				AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is
---cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle)
---en ayant vérifié que le bus est bien disponible pour l'écriture
- variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable tempdata:std_logic_vector(Word-1 downto 0);
-
-
-begin
-				if NextCtx /=0 then --préserver la valeur de count entre les appels
-					dcount:=NextCtx;
-				else
-					
-					
-				end if;
-							
-				if dcount=0 then
-					if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						Interf.O.membusy<='1';
-					end if;
-											
-						SysRam.O.Addr_rd<=adrVect;
-						SysRam.O.Addr_Wr<=adrVect;
-				elsif dcount=1 then
-				  	if interf.I.ramsel='0' then
-						tempdata:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrVect;
-						end if;
-						SysRam.O.enb<='1';
-						SySRam.O.ena<='0';
-						SysRam.O.we<='0';
-				elsif dcount=2 then
-						tempdata:=SysRam.I.Data_out;
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrVect;
-						SysRam.O.enb<='1';
-						SySRam.O.ena<='0';
-						SysRam.O.we<='0';
-				elsif dcount=3 then
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_Wr<=adrVect;
-						SysRam.O.We<='0';
-						SysRam.O.ena<='0';
-						SysRam.O.enb<='1';
-						tempdata:=SysRam.I.Data_out;
-						Interf.O.membusy<='1';
-						end if;
-				elsif dcount=4 then
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_Wr<=adrVect;
-						SysRam.O.We<='1';
-						SysRam.O.ena<='1';
-						SysRam.O.enb<='1';
-						tempdata:=SysRam.I.Data_out;
-						if BitVal='1' then
-						  TempData:=Tempdata or BitMask;
-						else
-						 TempData:=TempData and not (BitMAsk);
-						end if;
-						SysRam.O.Data_in<=TempData;
-						Interf.O.membusy<='1';
-						end if;
-				elsif dcount=5 then --attente d'écriture
-						if interf.I.ramsel='0' then 
-						dcount :=dcount+1;
-						SysRam.O.Addr_rd<=adrVect;
-						SysRam.O.We<='1';
-						SysRam.O.ena<='1';
-						--SysRam.O.Data_in<=TempData;
-						Interf.O.membusy<='1';
-						end if;
-				elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						Interf.O.membusy<='0';
-						SysRam.O.We<='0';
-						SysRam.O.ena<='0';
-						
-				end if;
-					
-					NextCtx:=dcount;
-end procedure;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram) is
---cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle)
---les données de l'appel de la procédure
-variable i,dcount : natural:=0;	
-variable adresse :natural;
-variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect;
-begin
-				if count /=0 then --préserver la valeur de count entre les appels
-					dcount:=count;
-				else
-					
-					
-				end if;
-				adresse:=Core_base_adr+2;
-				AdrToSet:=AdrVect;	
-				if dcount=0 then
-						SysRam.O.Data_in<=AdrToSet(Word-1 downto 0);
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-				elsif dcount=1 then
-				 
-				    SysRam.O.Data_in<=AdrToSet(Word-1 downto 0);
-				    SysRam.O.We<='1';SysRam.O.Ena<='1';
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN));
-						
-				elsif dcount=2 then
-				    SysRam.O.We<='1';SysRam.O.Ena<='1';
-				    SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word);
-						dcount :=dcount+1;
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN));
-						SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word);
-				elsif dcount=3 then
-						dcount :=dcount+1;
-						SysRam.O.We<='1';SysRam.O.Ena<='1';
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN));
-						SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word);
-				elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						dcount:=0;
-						SysRam.O.We<='0';SysRam.O.Ena<='0';
-						SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN));		
-				end if;
-					
-					count:=dcount;
-end procedure;
-end MPI_Rma;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MUX1.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MUX1.vhd	(revision 97)
+++ 	(revision )
@@ -1,46 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    09:18:52 06/13/2011 
--- Design Name: 
--- Module Name:    MUX1 - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity CMUXP1 is
-    Port ( di1 : in  STD_LOGIC;
-           di2 : in  STD_LOGIC;
-           do : out  STD_LOGIC;
-           sel : in  STD_LOGIC);
-end CMUXP1;
-
-architecture Behavioral of CMUXP1 is
-
-begin
- --modelisation d'un multiplexeur 1 bit
- with sel select
-		do <= di1 when '0',
-				di2 when '1',
-				di1 when others;
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MUX8.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MUX8.vhd	(revision 97)
+++ 	(revision )
@@ -1,45 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    09:30:26 06/13/2011 
--- Design Name: 
--- Module Name:    MUX8 - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity CMUX8 is
-    Port ( di1 : in  STD_LOGIC_VECTOR (7 downto 0);
-           di2 : in  STD_LOGIC_VECTOR (7 downto 0);
-           sel : in  STD_LOGIC;
-           do : out  STD_LOGIC_VECTOR (7 downto 0));
-end CMUX8;
-
-architecture Behavioral of CMUX8 is
-
-begin
- with sel select
-		do <= di1 when '0',
-				di2 when '1',
-				di1 when others;
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MultiMPITest.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MultiMPITest.vhd	(revision 97)
+++ 	(revision )
@@ -1,228 +1,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer: GAMOM Roland Christian
---
--- Create Date:   16:44:13 08/01/2012
--- Design Name:   
--- Module Name:   C:/Core MPI/CORE_MPI/MultiMPITest.vhd
--- Project Name:  MPI_CORE_COMPONENTS
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: MPI_NOC
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- 
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
- 
-library NocLib ;
-
-use NocLib.CoreTypes.all;
-LIbrary MPI_HCL;
-use MPI_HCL.Packet_type.all;
-use work.Hcl_Arch_conf.all;
-USE ieee.numeric_std.ALL;
- 
-ENTITY MultiMPITest IS
---simulation translate_off
-port (clkm : in std_logic;
-reset : in std_logic;
-result : out std_logic_vector(Word-1 downto 0));
---simulation translate_on
-END MultiMPITest;
- 
-ARCHITECTURE behavior OF MultiMPITest IS 
- 
-    -- Component Declaration for the Unit Under Test (UUT)
- 
-    COMPONENT MPI_NOC
-	 generic (NPROC: natural:=2);
-    PORT(
-         MPI_Node_in : IN   Ar_MPIPort_in(1 to NPROC);
-         MPI_Node_Out : OUT   Ar_MPIPort_out(1 to NPROC)
-        );
-    END COMPONENT;
-  Component PE
-  generic(destid : natural);
-  Port ( Instruction : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Instruction_en : out  STD_LOGIC;
-			  Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0);
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-			  CE : in  STD_LOGIC;
-           Core_RAM_Data_Out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Core_RAM_Data_In : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Core_RAM_WE : in  STD_LOGIC;
-           Core_RAM_EN : in  STD_LOGIC;
-           --Core_RAM_ENB : in  STD_LOGIC;
-           Core_RAM_ADDRESS_WR : in  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           Core_RAM_ADDRESS_RD : in  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           Core_Hold_req : in  STD_LOGIC;
-           Core_Hold_Ack : out  STD_LOGIC);
-end Component;  
- 
- 	constant clk_period : time := 15 ns;
-   constant PROC : positive :=NOC_SIZE; --4
--- synthesis translate_off
---===================signaux pour l'horloge ==============================
---signal reset,clkm : std_logic := '0';
---========================================================================
--- synthesis translate_on
- --signaux pour la gestion de la MAE
- type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, 
- putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout);
-signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
-signal count,count_i : natural range 0 to 15:=0;
-
-signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ;
-signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC);
-
-
-
- 
-BEGIN
- Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE)
-		PORT MAP (
-          MPI_Node_in => MPI_Node_in,
-          MPI_Node_Out => MPI_Node_Out
-        );
-
---PE1: PE generic map (DestId=>0)
---Port Map (
---Instruction => MPi_Node_in(1).Instruction,
---           Instruction_en => MPi_Node_in(1).Instruction_en,
---			  Core_PushOut => MPi_Node_out(1).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(1).ram_we,
---           Core_RAM_EN => MPI_Node_out(1).ram_en,
---          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(1).hold_req,
---           Core_Hold_Ack => MPI_Node_in(1).hold_ack
---);
---
---PE2: PE 	Generic map (DestId=>1)
---			Port Map (
---				Instruction => MPi_Node_in(2).Instruction,
---           Instruction_en => MPi_Node_in(2).Instruction_en,
---			  Core_PushOut => MPi_Node_out(2).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(2).ram_we,
---           Core_RAM_EN => MPI_Node_out(2).ram_en,
---           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(2).hold_req,
---           Core_Hold_Ack => MPI_Node_in(2).hold_ack
---);
---PE3: PE generic map (DestId=>2)
---Port Map (
---Instruction => MPi_Node_in(3).Instruction,
---           Instruction_en => MPi_Node_in(3).Instruction_en,
---			  Core_PushOut => MPi_Node_out(3).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(3).ram_we,
---           Core_RAM_EN => MPI_Node_out(3).ram_en,
---          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(3).hold_req,
---           Core_Hold_Ack => MPI_Node_in(3).hold_ack
---);
---
---PE4: PE 	Generic map (DestId=>3)
---			Port Map (
---				Instruction => MPi_Node_in(4).Instruction,
---           Instruction_en => MPi_Node_in(4).Instruction_en,
---			  Core_PushOut => MPi_Node_out(4).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(4).ram_we,
---           Core_RAM_EN => MPI_Node_out(4).ram_en,
---           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(4).hold_req,
---           Core_Hold_Ack => MPI_Node_in(4).hold_ack
---);
---MPI_Node_in(1).reset<=reset;	
---MPI_Node_in(1).clk<=clkm;
---MPI_Node_in(2).reset<=reset;	
---MPI_Node_in(2).clk<=clkm;
---MPI_Node_in(3).reset<=reset;	
---MPI_Node_in(3).clk<=clkm;
---MPI_Node_in(4).reset<=reset;	
---MPI_Node_in(4).clk<=clkm;
-Result<=MPi_Node_out(1).PushOut;
-PE_s:for i in 1 to STATIC_HT generate
-S: PE 	Generic map (DestId=>i-1)
-			Port Map (
-				Instruction => MPi_Node_in(i).Instruction,
-           Instruction_en => MPi_Node_in(i).Instruction_en,
-			  Core_PushOut => MPi_Node_out(i).PushOut,
-           clk =>clkm,
-           reset =>reset,
-			  CE => '1',
-           Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out,
-           Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in,
-           Core_RAM_WE => MPI_Node_out(i).ram_we,
-           Core_RAM_EN => MPI_Node_out(i).ram_en,
-           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
-           Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr,
-           Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd,
-           Core_Hold_req => MPI_Node_out(i).hold_req,
-           Core_Hold_Ack => MPI_Node_in(i).hold_ack
-);
-MPI_Node_in(i).reset<=reset;	
-MPI_Node_in(i).clk<=clkm;
-end generate PE_s;
-dyn_HT: if dyn_allowed='1' generate
-PE_D:for i in STATIC_HT+1 to NOC_SIZE generate
-D: PE 	Generic map (DestId=>i-1)
-			Port Map (
-				Instruction => MPi_Node_in(i).Instruction,
-           Instruction_en => MPi_Node_in(i).Instruction_en,
-			  Core_PushOut => MPi_Node_out(i).PushOut,
-           clk =>clkm,
-           reset =>reset,
-			  CE => '0',
-           Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out,
-           Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in,
-           Core_RAM_WE => MPI_Node_out(i).ram_we,
-           Core_RAM_EN => MPI_Node_out(i).ram_en,
-           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
-           Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr,
-           Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd,
-           Core_Hold_req => MPI_Node_out(i).hold_req,
-           Core_Hold_Ack => MPI_Node_in(i).hold_ack
-);
-MPI_Node_in(i).reset<=reset;	
-MPI_Node_in(i).clk<=clkm;
-end generate PE_D;
-end generate dyn_HT;
-END;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/MultiMPITest.vhd.bak
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/MultiMPITest.vhd.bak	(revision 97)
+++ 	(revision )
@@ -1,228 +1,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer: GAMOM Roland Christian
---
--- Create Date:   16:44:13 08/01/2012
--- Design Name:   
--- Module Name:   C:/Core MPI/CORE_MPI/MultiMPITest.vhd
--- Project Name:  MPI_CORE_COMPONENTS
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: MPI_NOC
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- 
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
- 
-library NocLib ;
-
-use NocLib.CoreTypes.all;
-LIbrary MPI_HCL;
-use MPI_HCL.Packet_type.all;
-use work.Hcl_Arch_conf.all;
-USE ieee.numeric_std.ALL;
- 
-ENTITY MultiMPITest IS
---simulation translate_off
-port (clkm : in std_logic;
-reset : in std_logic;
-result : out std_logic_vector(Word-1 downto 0));
---simulation translate_on
-END MultiMPITest;
- 
-ARCHITECTURE behavior OF MultiMPITest IS 
- 
-    -- Component Declaration for the Unit Under Test (UUT)
- 
-    COMPONENT MPI_NOC
-	 generic (NPROC: natural:=2);
-    PORT(
-         MPI_Node_in : IN   Ar_MPIPort_in(1 to NPROC);
-         MPI_Node_Out : OUT   Ar_MPIPort_out(1 to NPROC)
-        );
-    END COMPONENT;
-  Component PE
-  generic(destid : natural);
-  Port ( Instruction : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Instruction_en : out  STD_LOGIC;
-			  Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0);
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-			  CE : in  STD_LOGIC;
-           Core_RAM_Data_Out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Core_RAM_Data_In : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Core_RAM_WE : in  STD_LOGIC;
-           Core_RAM_EN : in  STD_LOGIC;
-           --Core_RAM_ENB : in  STD_LOGIC;
-           Core_RAM_ADDRESS_WR : in  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           Core_RAM_ADDRESS_RD : in  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           Core_Hold_req : in  STD_LOGIC;
-           Core_Hold_Ack : out  STD_LOGIC);
-end Component;  
- 
- 	constant clk_period : time := 15 ns;
-   constant PROC : positive :=4;
--- synthesis translate_off
---===================signaux pour l'horloge ==============================
---signal reset,clkm : std_logic := '0';
---========================================================================
--- synthesis translate_on
- --signaux pour la gestion de la MAE
- type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, 
- putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout);
-signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées
-signal count,count_i : natural range 0 to 15:=0;
-
-signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ;
-signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC);
-
-
-
- 
-BEGIN
- Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE)
-		PORT MAP (
-          MPI_Node_in => MPI_Node_in,
-          MPI_Node_Out => MPI_Node_Out
-        );
-
---PE1: PE generic map (DestId=>0)
---Port Map (
---Instruction => MPi_Node_in(1).Instruction,
---           Instruction_en => MPi_Node_in(1).Instruction_en,
---			  Core_PushOut => MPi_Node_out(1).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(1).ram_we,
---           Core_RAM_EN => MPI_Node_out(1).ram_en,
---          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(1).hold_req,
---           Core_Hold_Ack => MPI_Node_in(1).hold_ack
---);
---
---PE2: PE 	Generic map (DestId=>1)
---			Port Map (
---				Instruction => MPi_Node_in(2).Instruction,
---           Instruction_en => MPi_Node_in(2).Instruction_en,
---			  Core_PushOut => MPi_Node_out(2).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(2).ram_we,
---           Core_RAM_EN => MPI_Node_out(2).ram_en,
---           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(2).hold_req,
---           Core_Hold_Ack => MPI_Node_in(2).hold_ack
---);
---PE3: PE generic map (DestId=>2)
---Port Map (
---Instruction => MPi_Node_in(3).Instruction,
---           Instruction_en => MPi_Node_in(3).Instruction_en,
---			  Core_PushOut => MPi_Node_out(3).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(3).ram_we,
---           Core_RAM_EN => MPI_Node_out(3).ram_en,
---          -- Core_RAM_ENB => MPI_Node_out(1).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(3).hold_req,
---           Core_Hold_Ack => MPI_Node_in(3).hold_ack
---);
---
---PE4: PE 	Generic map (DestId=>3)
---			Port Map (
---				Instruction => MPi_Node_in(4).Instruction,
---           Instruction_en => MPi_Node_in(4).Instruction_en,
---			  Core_PushOut => MPi_Node_out(4).PushOut,
---           clk =>clkm,
---           reset =>reset,
---			  CE => '1',
---           Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out,
---           Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in,
---           Core_RAM_WE => MPI_Node_out(4).ram_we,
---           Core_RAM_EN => MPI_Node_out(4).ram_en,
---           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
---           Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr,
---           Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd,
---           Core_Hold_req => MPI_Node_out(4).hold_req,
---           Core_Hold_Ack => MPI_Node_in(4).hold_ack
---);
---MPI_Node_in(1).reset<=reset;	
---MPI_Node_in(1).clk<=clkm;
---MPI_Node_in(2).reset<=reset;	
---MPI_Node_in(2).clk<=clkm;
---MPI_Node_in(3).reset<=reset;	
---MPI_Node_in(3).clk<=clkm;
---MPI_Node_in(4).reset<=reset;	
---MPI_Node_in(4).clk<=clkm;
-Result<=MPi_Node_out(1).PushOut;
-PE_s:for i in 1 to STATIC_HT generate
-S: PE 	Generic map (DestId=>i-1)
-			Port Map (
-				Instruction => MPi_Node_in(i).Instruction,
-           Instruction_en => MPi_Node_in(i).Instruction_en,
-			  Core_PushOut => MPi_Node_out(i).PushOut,
-           clk =>clkm,
-           reset =>reset,
-			  CE => '1',
-           Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out,
-           Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in,
-           Core_RAM_WE => MPI_Node_out(i).ram_we,
-           Core_RAM_EN => MPI_Node_out(i).ram_en,
-           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
-           Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr,
-           Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd,
-           Core_Hold_req => MPI_Node_out(i).hold_req,
-           Core_Hold_Ack => MPI_Node_in(i).hold_ack
-);
-MPI_Node_in(i).reset<=reset;	
-MPI_Node_in(i).clk<=clkm;
-end generate PE_s;
-dyn_HT: if dyn_allowed='1' generate
-PE_D:for i in STATIC_HT+1 to NOC_SIZE generate
-D: PE 	Generic map (DestId=>i-1)
-			Port Map (
-				Instruction => MPi_Node_in(i).Instruction,
-           Instruction_en => MPi_Node_in(i).Instruction_en,
-			  Core_PushOut => MPi_Node_out(i).PushOut,
-           clk =>clkm,
-           reset =>reset,
-			  CE => '0',
-           Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out,
-           Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in,
-           Core_RAM_WE => MPI_Node_out(i).ram_we,
-           Core_RAM_EN => MPI_Node_out(i).ram_en,
-           --Core_RAM_ENB => MPI_Node_out(2).ram_en,
-           Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr,
-           Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd,
-           Core_Hold_req => MPI_Node_out(i).hold_req,
-           Core_Hold_Ack => MPI_Node_in(i).hold_ack
-);
-MPI_Node_in(i).reset<=reset;	
-MPI_Node_in(i).clk<=clkm;
-end generate PE_D;
-end generate dyn_HT;
-END;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Packet_type.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Packet_type.vhd	(revision 97)
+++ 	(revision )
@@ -1,104 +1,0 @@
---	Package File Template
---
---	Purpose: This package defines supplemental types, subtypes, 
---		 constants, and functions
--- package definissant le codage des fonctions MPI 
--- dans le champs packet type des instructions MPI 
-
--- Ce fichier définit les trames des instruction MPI qui sont utilisables
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package Packet_type is
-	
- constant ADRLEN1										:natural:=16;
- constant MPI_COMM_WORLD							:natural:=1;
- constant MPI_DEFAULT								:natural:=0;
- constant MPI_INT										:natural:=1;
- constant MPI_INFO_NULL								:natural:=0;
- constant Default_Win								:natural:=1;
- constant MPI_GET_RANK								: std_logic_vector(3 downto 0) := "0000";
- constant MPI_GET_SIZE								: std_logic_vector(3 downto 0) := "0001";
- constant MPI_BARRIER								: std_logic_vector(3 downto 0) := "0010";
- constant MPI_BARRIER_REACHED						: std_logic_vector(3 downto 0) := "0011";
- constant MPI_BARRIER_COMPLETED					: std_logic_vector(3 downto 0) := "1110";
- constant MPI_ACK  	                : std_logic_vector(3 downto 0) := "0100"; 
- constant MPI_PUT   									: std_logic_vector(3 downto 0) := "0101";
- constant MPI_GET  									: std_logic_vector(3 downto 0) := "0110";
- constant MPI_BROADCAST								: std_logic_vector(3 downto 0) := "0111";
- constant MPI_INIT     								: std_logic_vector(3 downto 0) := "1000";
- constant MPI_SPAWN									: std_logic_vector(3 downto 0) := "1001";
- 
- constant MPI_WIN_CREATE								: std_logic_vector(3 downto 0) := "1010";
- constant MPI_WIN_SYNC       :std_logic_vector(3 downto 0):="1011";
- constant MPI_WIN_COMPLETE							: std_logic_vector(3 downto 0) := "1100";
- constant MPI_WIN_POST								: std_logic_vector(3 downto 0) := "1101";
- constant MPI_WIN_WAIT								: std_logic_vector(3 downto 0) := "1110";
- 
- 
- 
- constant MPI_WTIME									: std_logic_vector(3 downto 0) := "1110";
- constant MPI_WTICK 									: std_logic_vector(3 downto 0) := "1111";
- constant MPI_CONFIG								   : std_logic_vector(3 downto 0) := "1101";
- --paramètres des commandes
- Constant INIT_SEEKMAIN								: std_logic_vector(3 downto 0) := "0001";
- Constant INIT_SETRANK								: std_logic_vector(3 downto 0) := "0011";
- Constant INIT_REGISTER								: std_logic_vector(3 downto 0) := "0010";
- Constant INIT_STAT									: std_logic_vector(3 downto 0) := "0100";
- Constant INIT_SPAWN									: std_logic_vector(3 downto 0) := "0101";
-
- Constant SPAWN_LOAD									: std_logic_vector(3 downto 0) := "1001";
- Constant SPAWN_START								: std_logic_vector(3 downto 0) := "1010";
- Constant SPAWN_COMP									: std_logic_vector(3 downto 0) := "1011";
- Constant SPAWN_ERR									: std_logic_vector(3 downto 0) := "1110";
-
-Constant SYNC_WSTART									: std_logic_vector(3 downto 0) := "0001";
- Constant SYNC_WPOST								: std_logic_vector(3 downto 0) := "0010";
- Constant SYNC_WCOMP									: std_logic_vector(3 downto 0) := "0011";
- Constant SYNC_WWAIT									: std_logic_vector(3 downto 0) := "0100";
--- constantes pour le NoC								
- Constant NOC_GETPORTID								: std_logic_vector(7 downto 0) := "00000001";
---constante pour les Ptr
-constant W_Status :natural:=0; --position relative des champs dans la mémoire
-constant W_Id :natural:=2;   -- pour le type MPI_Win
-constant W_GStart :natural:=3;
-constant W_GPost :natural:=5;
-constant W_Addr :natural:=7;
-constant W_Size :natural:=9;
-constant W_comm :natural:=10;
-
-Type MPI_Datatype is (MPI_BYTE,MPI_INTEGER,MPI_REAL,MPI_PACKET, MPI_pointer);
-SUBType MPI_COMM is  natural range 0 to 2**ADRLEN1-1 ; --pointeur sur la structure du communicateur
-subType Mpi_AInt is natural range 0 to 2**ADRLEN1-1 ;
---subType Mpi_win is natural range 0 to 2**ADRLEN1-1 ;
-Type MPI_COMM_struc is record
-   id : natural range 0 to 3; -- id du communicateur
-	grp : std_logic_vector(15 downto 0);     --groupe associé au communicateur
-	nproc : natural range 0 to 15;   -- nombre de membres du groupe de ce communicateur
-	AddrLib : std_logic_vector(15 downto 0); -- adresse dans la mémoire de la Lib 
-														  -- des registres GStart et GPost
-	ParentId:natural range 0 to 3; --Id du communicateur parent si Intercomm=1
-	C_open,C_close,InterComm : std_logic;  -- état du communciateur (Inistialisé ou finalisé)
-end record;
-
-Type Mpi_Win is record 
-	status : std_logic_vector(7 downto 0); --état de la fenêtre (create,Start,Complete,Post,WaitSync, etc.)
-	id : natural range 0 to 15 ; -- numéro de la fenêtre
-	
-	Addr : std_logic_vector(15 downto 0); -- adresse dans la mémoire locale du PE
-	Size : natural range 0 to 65535; -- taille de la fenêtre en octets 
-	GPost : std_logic_vector(15 downto 0);--registres de synchronisation en cible
-	GStart : std_logic_vector(15 downto 0);-- registre de synchronisation source
-	comm : MPI_COMM; -- Ptr sur communicateur associé à la fenêtre
-end record;
-Type Mpi_group is record  --normalement sous-goupe d'un communicateur
-	grp : std_logic_vector(15 downto 0); --( vecteur de la liste des processus du groupe)
-	nb : natural range 0 to 15; -- nombre de membres(processus du groupe)
-	comm_id : natural range 0 to 3; -- reférence du communicateur
-end record;
-end Packet_type;  
-
-package body Packet_type is
-
-
-end Packet_type;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Processing_node.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Processing_node.vhd	(revision 97)
+++ 	(revision )
@@ -1,397 +1,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   01:27:32 04/20/2012
--- Design Name:   
--- Module Name:   C:/Core MPI/CORE_MPI/MPICORETEST.vhd
--- Project Name:  MPI_CORE_COMPONENTS
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: MPI_NOC
--- 
--- Dependencies:
--- 
--- Revision: 11 Juillet 2012
--- Revision 0.01 - File Created
--- Additional Comments : entité de test de l'environement MPSOC il est constitué d'une
---MAE simulant le processeur
--- Notes: 
--- 
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-library NocLib ;
---use IEEE.STD_LOGIC_ARITH.ALL;
---use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use NocLib.CoreTypes.all;
-use work.Packet_type.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-USE ieee.numeric_std.ALL;
- 
-ENTITY PROCESSING_ELEMENT IS
--- entité du processeur du MPI
-port (  clk     : in std_logic;
-		reset   : in std_logic;
-		ram_we  :  in std_logic; 
-		ram_ena :  in std_logic;
-		ram_enb :  in std_logic;
-		ram_do : out std_logic_vector( downto ); --word - 1 downto 0
-		ram_din : in std_logic_vector(word - 1 downto 0);--word - 1 downto 0
-		ram_addra : out std_logic_vector(ADRLEN - 1  downto 0);-- ADRLEN - 1  downto 0
-		ram_addrb : out std_logic_vector(ADRLEN - 1  downto 0);-- ADRLEN - 1  downto 0
-		instruction_en : out std_logic;
-		hold_request : in std_logic;
-		hold_ack : out std_logic;
-		ram_sel : out std_logic;
-		lib_ready : in std_logic;
-		lib_initialized  : in std_logic; 
-		);
-END PROCESSING_ELEMENT;
- 
-ARCHITECTURE behavior OF PROCESSING_ELEMENT IS 
-
-	--données du programme PE
-	signal SrcAdr0, SrcAdr1, destAdr0, destAdr1, Datalen : std_logic_vector(word - 1downto 0);--
-	signal dpid,dpid_i : natural range 0 to 15;
- --signaux pour la gestion de la MAE
-	type typ_mae is (InitApp,InitCompleted,writeptr, putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout);
-	signal dcount : natural range 0 to 255:= 0; --permet de compter le packet de données envoyées
-	signal count,count_i : natural range 0 to 15:=0;
---signal adresse,adresse_rd :natural range 0 to 65536;
-	signal etPutGet : typ_mae;
-	signal Ram_busy :std_logic:='0';
-	--constant pour la construction du fichier
-	-- ces lignes devront être commentées lors de l'assemblage final
-BEGIN
-
-
-dpid<=dpid_i;
- pPutGet : process(clk)
-	
-	variable bfill,destrank,pid,mport : natural range 0 to 15;
-	variable fsrc,ret : natural range 0 to 15:=0;
-	variable timeout : natural range 0 to 255;
-	variable adrToset : std_logic_vector(15 downto 0);
-	variable  adresse,adresse_rd :natural range 0 to 65536;
-	begin
-	 if (clk'event and clk ='1') then 
-		if reset='1' then
-				etputget<= InitApp;
-				adresse:=0;
-				adresse_rd:=0;
-				timeout:=0;
-				dcount<=0;
-		else
-	     case  etputget is
-			
-		  when InitApp =>
-				--code pour Init ici
-				--mettre mpi_init à l'adresse mpi 
-				--initialisation du module mpi du pn
-				ram_do <=MPI_INIT & x"0" ;
-				fsrc:=1;
-				adrToSet:=std_logic_vector(to_unsigned(core_init_adr,16));
-				if ret/=fsrc then
-				    dcount<=0;
-					etputget<=writeptr;
-					adresse:=core_base_adr+2;
-				else
-					adresse:=core_init_adr;
-					etputget<= InitCompleted;
-				end if;
-		
-		when writeptr =>
-		 
-				if PE_Hold_req = '0' then --s'assurer que le bus est disponible
-					if dcount=0 then 
-						ram_do <=AdrToSet(7 downto 0);
-						dcount <=dcount+1;
-						--adresse:=adresse+1; --prépare la prochaine écriture
-					elsif dcount=1 then
-						dcount <=dcount+1;
-						adresse:=adresse+1; --prépare la prochaine écriture
-						ram_do <=AdrToSet(15 downto 8);
-					elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM
-						ret:=fsrc;
-						dcount<=0;
-						timeout:=0;
-						if fsrc=1 then
-						etputget <= InitApp;
-						elsif fsrc=2 then
-						etputget <= putdata;
-						elsif fsrc=3 then
-						etputget <= getdata;
-						else
-						etputget <= start;
-						end if;
-						
-					end if;
-					
-				end if;
-		when InitCompleted =>
-				if Lib_Init='1' then
-					etputget <= putdata;
-				end if;
-		when putdata => --construire le packet pour le Put
-				DestRank:=1;
-				adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank;
-				timeout:=0;
-				dcount<=0;
-				fsrc:=2;
-				adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16));
-				if ret/=fsrc then
-					etputget<=writeptr;
-					ret:=0;
-				else
-					etputget<= putdata2;
-				end if;
-				
-		when putdata2 =>
-		      if dcount<5 then
-						dcount<=dcount+1;
-						if dcount=0 then 
-						adresse:=core_put_adr;
-						ram_do <=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4));
-						elsif dcount=1 then 
-						adresse:=core_put_adr+dcount;
-						ram_do <=SrcAdr1 ;
-						elsif dcount=2 then
-						adresse:=core_put_adr+dcount;
-						ram_do <=SrcAdr0 ;
-						elsif dcount=3 then
-						adresse:=core_put_adr+dcount;
-						ram_do <=DestAdr1 ;
-						elsif dcount=4 then
-						adresse:=core_put_adr+dcount;
-						ram_do <=DestAdr0 ;
-						elsif dcount=5 then
-						adresse:=core_put_adr+dcount;
-						ram_do <=Datalen ;
-						end if;
-				else
-						adresse:=core_base_adr+1;
-						adresse_rd:=core_base_adr;
-						ram_do <=x"01"; --instruction pulse enable;
-						if ram_din(1)='1' then -- Instruction ack
-							if PE_Hold_Req='0' then
-								adresse:=core_base_adr+1;
-								ram_do <=x"00"; --ramener le IPulse à 0;
-								etPutGet<=putcompleted;
-							else
-								
-							end if;
-						end if;
-				end if;
-			
-			when putcompleted =>
-				adresse_rd:=core_put_adr+6;
-				if ram_din(0)='1' then  --Put completed
-					etPutGet<=GetData;
-				end if;
-			when getdata =>   --positionnement du mot de longueur des données
-			   adresse:=core_get_adr;
-				DestRank:=1;
-				timeout:=0;
-				dcount<=0;
-					fsrc:=3;
-				adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16));
-				if ret/=fsrc then
-				
-					etputget<=writeptr;
-					ret:=0;
-				else
-					etputget<= getdata2;
-				end if;
-			    
-				when getdata2 =>
-					if dcount<5 then
-						dcount<=dcount+1;
-						if dcount=0 then 
-							adresse:=core_get_adr;
-						ram_do <=MPI_GET & std_logic_vector(to_unsigned(Dpid,4));
-						adresse:=core_get_adr+dcount;
-						ram_do <=SrcAdr1 ;
-						elsif dcount=2 then
-						adresse:=core_get_adr+dcount;
-						ram_do <=SrcAdr0 ;
-						elsif dcount=3 then
-						adresse:=core_get_adr+dcount;
-						ram_do <=DestAdr1 ;
-						elsif dcount=4 then
-						adresse:=core_get_adr+dcount;
-						ram_do <=DestAdr0 ;
-						elsif dcount=5 then
-						adresse:=core_get_adr+dcount;
-						ram_do <=Datalen;
-						end if;
-				    else
-						adresse:=core_base_adr+1;
-						adresse_rd:=core_base_adr;
-						ram_do <=x"01"; --instruction pulse enable;
-						if ram_din(1)='1' then -- Instruction ack
-						etPutGet<=getcompleted;
-						else
-						
-						end if;
-				end if;
-					
-				when getcompleted =>
-				adresse_rd:=core_get_adr+6;
-				if ram_din(0)='1' then  --Put completed
-				   if PE_Hold_Req='0' then
-					adresse:=core_base_adr+1;
-					ram_do <=x"00"; --ramener le IPulse à 0;
-					etPutGet<=Terminate;
-					else
-						timeout:=timeout+1;
-					end if;
-				end if;	
-					
-						
-			when terminate =>
-			
-		
-					etputget<=start;
-					
-			when st_timeout =>
-			  
-			  --if ram_busy='1' then
-				 etputget<=start;
-			  --end if		
-			  etputget<=start;
-			end case;
-			ram_addra <=STD_LOGIC_VECTOR(to_unsigned(adresse,16));
-			ram_addrb <=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));
-		end if;   --reset='1'
-	end if;
-  end process pPutGet;	
-
-majPutGet:process (etputget)
-
-	begin
-			case  etputget is
-			when start =>
-			        ram_we <='0';
-					ram_ena<='0';
-					ram_enb<='0';
-					instruction_en<='0';
-
-		 when fillmem =>
-				   ram_we <='1';
-					ram_ena<='1';
-					
-					ram_enb<='0';
-					instruction_en<='0';
-		 when nextfill =>
-					ram_we <='1';
-					ram_ena<='1';
-					ram_enb<='0';
-					instruction_en<='0';
-	    when InitApp =>
-				   ram_we <='1';
-					ram_ena<='1';
-					ram_enb<='0';
-					instruction_en<='0';
-		 when Initcompleted =>
-			      instruction_en<='1';
-		 when writeptr =>
-					ram_we   <='1';   --écriture dans la RAM
-					ram_ena <='1';
-					
-					ram_enb <='0';
-			--		dcount<=dcount+1;
-					
-					instruction_en<='0';
-					
-			when putdata =>   --positionnement du mot de longueur des données
-				--dcount<=0;
-				srcadr0<=X"00";
-				srcadr1<=X"01";
-				destadr0<=X"00";
-				destadr1<=X"02";
-			    ram_we <='0';
-				ram_ena<='0';
-				 --lecture du n° de port de destination
-				ram_enb<='1';
-				datalen<=std_logic_vector(to_unsigned(50,8));
-				dpid_i<=to_integer(unsigned(ram_din(3 downto 0))); --le port est situé ur les 4 bits de poids faible
-				instruction_en<='0';
-			when putdata2 =>
-					ram_we   <='1';   --écriture dans la RAM
-					ram_ena <='1';
-					
-					ram_enb <='0';
-			--		dcount<=dcount+1;
-					if dcount=5 then
-					instruction_en<='1';
-					else
-					instruction_en<='0';
-					end if;
-			when putcompleted =>			
-					ram_we   <='1';
-					ram_ena <='1';
-					  -- lecture du résultat
-					ram_enb  <='1';
-					instruction_en<='1';
-			when getdata =>
-				--dcount<=0;
-				srcadr0<=X"00";
-				srcadr1<=X"02";
-				destadr0<=X"00";
-				destadr1<=X"03";
-				datalen<=std_logic_vector(to_unsigned(50,8));
-				instruction_en<='0';	
-			when getdata2 =>
-				   ram_we   <='1';   --écriture dans la RAM
-					ram_ena <='1';
-					
-					ram_enb <='0';
-				--dcount<=dcount+1;
-				   if dcount=5 then
-						instruction_en<='1';
-					else
-						instruction_en<='0';
-					end if;
-			when getcompleted =>				
-					ram_we   <='1';
-					ram_ena <='1';
-					  -- lecture du résultat
-					ram_enb  <='1';
-					instruction_en<='1';
-			when terminate =>
-			
-				   ram_we <='0';
-					ram_ena<='0';
-					ram_enb<='0';
-					instruction_en<='0';
-			
-			when st_timeout =>
-				  ram_we <='0';
-				  ram_ena<='0';
-				  ram_enb<='0';
-				  instruction_en <='0';
-			end case;
-end process majPutGet ;  
-
- hold:process (clk)
- begin
- if rising_edge(clk) then
-	if reset='1' then
-		hold_ack<='0';
-	else
-		if hold_request ='1' then
-			ramsel<='1';
-			pe_hold_ack<= '1';--not(ram_busy); --si la mémoire est occupé, forcé une libération
-		else
-			pe_hold_ack<='0';
-			ramsel<='0';
-		end if;
-	end if;
- end if;
- end process hold;
-END;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_32_32.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_32_32.vhd	(revision 97)
+++ 	(revision )
@@ -1,105 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer:  GAMOM NGOUNOU 
--- 
--- Create Date:    18:33:31 03/05/2012 
--- Design Name: 
--- Module Name:    RAM_32_32 - Behavioral 
--- Project Name: MPI_Core
--- Target Devices: 
--- Tool versions: 
--- Description: permet de stocker les données locales de la librairie MPI
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity RAM_v is
-generic(width : positive:=32; Size:positive:=16);
-Port ( clka, clkb : in std_logic;
-			  wea : in std_logic;
-			  ena, enb : in std_logic;
-			  addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse
-			  dia : in std_logic_vector(width-1 downto 0);
-			  dob : out std_logic_vector(width-1 downto 0));
-end RAM_v;
-
-architecture Behavioral of RAM_v is
-	attribute RAM_STYLE : string;
-	signal Lra,Lrb :std_logic:='0';
-	signal sel : std_logic_vector(1 downto 0);
-	signal doa,dout : std_logic_vector(width-1 downto 0);
-	type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0);
-	signal RAM: ram_type;
-	attribute RAM_STYLE of RAM: signal is "BLOCK";
-begin
- process (clka)
-	begin
-		if clka'event and clka = '1' then
-			if ena = '1' then
-				if wea = '1' then
-				  if conv_integer(addra)>8191 then
-				      report  "Erreur d'adresse";
-				  else
-          					RAM(conv_integer(addra)) <= dia;
-					end if;
-				end if;
-				if conv_integer(addrb)>8191 then
-				      report  "Erreur d'adresse";
-				  else	
-				doa<=RAM(conv_integer(addrb));
-			   end if;
-				Lra<='1';
-			else 
-				if lrb='1' then
-						Lra<='0';
-				end if;
-			end if;
-		 end if;
- end process;
-
- 
- process (clkb)	
- begin
-		if clkb'event and clkb = '1' then
-			if enb = '1' then
-				Lrb<='1';	
-				if conv_integer(addrb)>8191 then
-				      report  "Erreur d'adresse";
-				  else	
-				  dout <= RAM(conv_integer(addrb)) ;
-				end if;
-			else
-				if Lra='1' then
-					Lrb<='0';
-				end if;
-			end if;
-		end if;
- end process;
- 
- sel<=(Lra,Lrb);
- With  sel select
- dob <=dout when "11",
-      doa  when "10",
-		dout when "01",
-		dout when "00",
-		dout when others;
-		
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_64.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_64.vhd	(revision 97)
+++ 	(revision )
@@ -1,67 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: KIEGAING EMMANUEL GEL EN 5
--- 
--- Create Date:    18:54:08 04/19/2011 
--- Design Name: 
--- Module Name:    RAM_64 - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: SYNTHESE d'une RAM 64 octet par inferation
--- la ram possède un port d'écriture et un port de lecture
--- le port primaire est à lecture et ecrite et le port secondaire à lecture seule
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-Library NocLib;
-use NocLib.CoreTypes.all;
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity RAM_64 is
-    Port ( clka, clkb : in std_logic;
-			  wea : in std_logic;
-			  ena, enb : in std_logic;
-			  addra, addrb : in std_logic_vector(5 downto 0);
-			  dia : in std_logic_vector(Word-1 downto 0);
-			  dob : out std_logic_vector(Word-1 downto 0));
-end RAM_64;
-
-architecture Behavioral of RAM_64 is
-	type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0);
-	signal RAM: ram_type;
-begin
- process (clka)
-	begin
-		if clka'event and clka = '1' then
-			if ena = '1' then
-				if wea = '1' then
-					RAM(conv_integer(addra)) <= dia;
-				end if;
-			end if;
-		 end if;
- end process;
- 
- process (clkb)
-	begin
-		if clkb'event and clkb = '1' then
-			if enb = '1' then
-				--dob <= RAM(conv_integer(addrb)) ;
-			end if;
-		end if;
- end process;
-	dob <= RAM(conv_integer(addrb)) ;
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/image_pkg.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/image_pkg.vhd	(revision 97)
+++ 	(revision )
@@ -1,134 +1,0 @@
-----------------------------------------------------------------------------
--- Copyright (c) 1996, Ben Cohen.   All rights reserved.
--- This model can be used in conjunction with the Kluwer Academic books
--- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
--- "VHDL Amswers to Frequently Asked Questions", ISBN 0-7923-9791-6
--- Web page:   http://members.aol.com/vhdlcohen/vhdl
--- email: vhdlcohen@aol.com
---
--- This source file for the image  package
--- may be used and distributed without restriction provided
--- that this copyright statement is not removed from the file
--- and that any derivative work contains this copyright notice.
-------------------------------------------------------------------------------- 
-library IEEE; 
-  use IEEE.Std_Logic_1164.all;
-  use IEEE.Std_Logic_TextIO.all;  
-  use IEEE.Std_Logic_Arith.all;
-
-library Std;
-  use STD.TextIO.all;
-
-package Image_Pkg is
-  function Image(In_Image : Time) return String;
-  function Image(In_Image : Bit) return String;
-  function Image(In_Image : Bit_Vector) return String;
-  function Image(In_Image : Integer) return String;
-  function Image(In_Image : Real) return String;
-  function Image(In_Image : Std_uLogic) return String;
-  function Image(In_Image : Std_uLogic_Vector) return String;
-  function Image(In_Image : Std_Logic_Vector) return String;
-  function Image(In_Image : Signed) return String;
-  function Image(In_Image : UnSigned) return String;
-
-end Image_Pkg;
-
-package body Image_Pkg is
-  function Image(In_Image : Time) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to 25) := (others => ' '); 
-       -- Long enough to hold a time string
-  begin
-    -- the WRITE procedure creates an object with "NEW".
-    -- L is passed as an output of the procedure.
-    Std.TextIO.WRITE(L, in_image);
-    -- Copy L.all onto W
-    W(L.all'range) := L.all;
-    Deallocate(L);
-    return W;
-  end Image;
-
-  function Image(In_Image : Bit) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to 3) := (others => ' ');  
-  begin
-    Std.TextIO.WRITE(L, in_image);
-    W(L.all'range) := L.all;
-    Deallocate(L);
-    return W;
-  end Image;
-
-  function Image(In_Image : Bit_Vector) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to In_Image'length) := (others => ' ');  
-  begin
-    Std.TextIO.WRITE(L, in_image);
-    W(L.all'range) := L.all;
-    Deallocate(L);
-    return W;
-  end Image;
-
-  function Image(In_Image : Integer) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to 32) := (others => ' ');  
-     -- Long enough to hold a time string
-  begin
-    Std.TextIO.WRITE(L, in_image);
-    W(L.all'range) := L.all;
-    Deallocate(L);
-    return W;
-  end Image;
-
-  function Image(In_Image : Real) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to 32) := (others => ' ');  
-      -- Long enough to hold a time string
-  begin
-    Std.TextIO.WRITE(L, in_image);
-    W(L.all'range) := L.all;
-    Deallocate(L);
-    return W;
-  end Image;
-
-  function Image(In_Image : Std_uLogic) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to 3) := (others => ' ');  
-  begin
-    IEEE.Std_Logic_Textio.WRITE(L, in_image);
-    W(L.all'range) := L.all;
-    Deallocate(L);
-    return W;
-  end Image;
-
-  function Image(In_Image : Std_uLogic_Vector) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to In_Image'length) := (others => ' ');  
-  begin
-    IEEE.Std_Logic_Textio.WRITE(L, in_image);
-    W(L.all'range) := L.all;
-    Deallocate(L);
-    return W;
-  end Image;
-
-  function Image(In_Image : Std_Logic_Vector) return String is
-    variable L : Line;  -- access type
-    variable W : String(1 to In_Image'length) := (others => ' ');  
-  begin
-     IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
-     W(L.all'range) := L.all;
-     Deallocate(L);
-     return W;
-  end Image;
-
-  function Image(In_Image : Signed) return String is 
-  begin 
-    return Image(Std_Logic_Vector(In_Image));
-  end Image;
-
-  function Image(In_Image : UnSigned) return String is
-  begin 
-    return Image(Std_Logic_Vector(In_Image));
-  end Image;
-
-end Image_Pkg;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/load_instr.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/load_instr.vhd	(revision 97)
+++ 	(revision )
@@ -1,319 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: GAMOM NGOUNOU
--- 
--- Create Date:    04:57:14 07/15/2012 
--- Design Name: 
--- Module Name:    load_instr - Behavioral 
--- Project Name: MPI CORE
--- Target Devices: 
--- Tool versions: 
--- Description: Ce module permet de charger une instruction dans le FIFO 1
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-library NocLib;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
-use NocLib.CoreTypes.all;
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity load_instr is
-    Port ( Instruction : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Instruction_en : in  STD_LOGIC;
-			  
-           clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           dma_rd_grant : in  STD_LOGIC;
-           dma_rd_request : out  STD_LOGIC:='0';
-           instruction_ack : out  STD_LOGIC:='0';
-           fifo_din : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  fifo_wr :out std_logic:='0';
-			  copying :out std_logic:='0';
-           fifo_full : in  STD_LOGIC;
-           ram_address_rd : buffer  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
-           ram_data : in  STD_LOGIC_VECTOR (WORD-1 downto 0);
-			  Ram_rd_en : out std_logic);
-end load_instr;
-
-architecture Behavioral of load_instr is
---déclaration des types manipulés
-type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout);
---déclaration des signaux
-signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
---signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM
-signal Base_Adr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
-signal adr_ptr : natural range 0 to 65536:=0;
-signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée
-signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'-');
-signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo
-signal fifo_wr_i :std_logic:='0';
-signal base_adrset_i : std_logic:='0';
-signal instruction_ack_i :std_logic:='0';
-signal Dma_rd_request_i :std_logic:='0';
-signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE
-signal etloadinst,next_loadinst : typ_loadinst;
-begin
-SYNC_PROC: process (clk)
-   begin
-      if rising_edge(clk) then
-         if (reset = '1') or instruction_en='0' then
-            etloadinst <= init;
-            Base_adrSet<= '0';
-				dma_rd_request<='0';
-				instruction_ack<='0';
-         else
-            etloadinst <= next_loadinst;
-            fifo_din <= fifo_din_i;
-				Base_AdrSet<=Base_adrSet_i;
-				ram_address_rd<=ram_address_i;
-				adr_ptr<=to_integer(unsigned(ram_address_i));
-				dma_rd_request<=dma_rd_request_i;
-				instruction_ack<=instruction_ack_i;
-				count<=count_i;
-				Ilen<=Ilen_i;
-				
-				
-         -- assign other outputs to internal signals
-         end if;        
-      end if;
-   end process;
- 
-   --
-   OUTPUT_DECODE: process (etloadinst,Count_i,Ram_data,Dma_rd_grant,fifo_wr_i)
-	variable Adr_inst1,adr_inst2 : natural;
-   begin
-      --insert statements to decode internal output signals
-      --below is simple example
-      case etloadinst is
-		 when init =>
-		 Dma_rd_request_i<='0';
-		 fifo_wr<='0';
-		 copying<='0';
-		 Ram_rd_en<='0';
-		 Instruction_ack_i<='0';
-		 fifo_din_i<=(others=>'-');
-		 Base_AdrSet_i<='0';
-		 
-		 when SetAdr =>
-		 Dma_rd_request_i<='0';
-		 Instruction_ack_i<='0';
-		 fifo_wr<='0';
-		 copying<='0';
-		 Ram_rd_en<='0';
-		 
-		 fifo_din_i<=(others=>'-');
-		 Base_AdrSet_i<='1';
-		 
-		 when getbus =>
-		 fifo_wr<='0';
-		 copying<='1';
-		 Ram_rd_en<=Dma_rd_grant;
-		 Dma_rd_request_i<='1';
-		 Instruction_ack_i<='0';
-		 fifo_din_i<=(others=>'-');
-		 Base_AdrSet_i<='1';
-		 when readptr => 
-		 fifo_wr<='0';
-			 
-		 copying<='1';
-		 Ram_rd_en<='1';
-		 Dma_rd_request_i<='1';
-		 Instruction_ack_i<='0';
-		 fifo_din_i<=(others=>'-');
-		 Base_AdrSet_i<='1';
-		 when readmem =>
-		 Dma_rd_request_i<='1';
-		 copying<='1';
-		 Ram_rd_en<='1';
-		 fifo_wr<=fifo_wr_i;
-		 fifo_din_i<=Ram_data;
-		 Base_AdrSet_i<='1';
-		 Instruction_ack_i<='0';
-		 
-		 when freebus =>
-		 Dma_rd_request_i<='0';
-		 fifo_wr<='0';
-		 copying<='0';
-		 Ram_rd_en<='0';
-		 Instruction_ack_i<='1';
-		 fifo_din_i<=(others=>'-');
-		 Base_AdrSet_i<='1';
-		 when st_timeout =>
-		 Dma_rd_request_i<='0';
-		 fifo_wr<='0';
-		copying<='0';
-		 Ram_rd_en<='0';
-		 Instruction_ack_i<='0';
-		 fifo_din_i<=(others=>'-');
-		 Base_AdrSet_i<='1';
-		end case;
-   end process;
- 
-   NEXT_STATE_DECODE: process (etloadinst, Ram_address_rd,Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count,Ilen)
-	
-   variable ptr : std_logic_vector(ADRLEN-1 downto 0);
-	variable timeout: natural range 0 to 255;
-	variable Base_AD,ADRtmp,iptr : natural range 0 to 65535;
-	begin
-      --declare default state for next_state to avoid latches
-      next_loadinst <= etloadinst;  --default is to stay in current state
-      Ram_address_i<=Ram_address_rd;
-      --below is a simple example
-      case (etloadinst) is
-         when init => if base_adrset='1'  and Instruction_en='1' then
-							 Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur 
-								next_loadinst<=getbus;
-							elsif Instruction_en='1' then
-								next_loadinst<=Setadr;
-								Base_Adr<=X"0000";
-							else
-								next_loadinst<=init;
-								Base_Adr<=X"0000";
-								Ilen_i<=0;
-							end if;
-							fifo_wr_i<='0';
-							count_i<=0;
-							
-							--
-			When Setadr => if Base_adrSet='0' then
-									Base_Adr<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00";  --récupération des bits de poids forts de l'instruction
-										  --
-								end if;
-								next_loadinst<=init;
-					Ram_address_i<=(others=>'0');
-					count_i<=0;
-         when getbus =>
-            BASE_AD:=to_integer(unsigned(base_adr));
-				if dma_rd_grant = '1' then
-               next_loadinst <= readptr;
-					
-					-- prépare la prochaine lecture
-
-				else
-					
-				end if;
-				Ram_address_i<=(others=>'0');
-				count_i<=0;
-         When readptr =>
-				 --s'assurer que le bus est disponible
-						
-					if count=0 then 
-					  
-						Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16));
-						if dma_rd_grant='1' then
-						count_i <=count+1;
-						end if;
-					elsif count=1 then-- attend que la donnée soit positionnée	
-						if dma_rd_grant = '1' then
-						count_i <=count+1;
-					 end if;
-					elsif count=2 then
-					  if dma_rd_grant = '1' then
-						count_i <=count+1;
-						ptr(Word-1 downto 0):=Ram_data;
-						else
-						  count_i<=0;
-					 end if;
-						Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
-						
-					elsif count=3 then
-					  Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
-					  if dma_rd_grant = '1' then
-						count_i <=count+1;
-						end if;
-					elsif count=4 then
-					  if dma_rd_grant = '1' then
-						ptr(15 downto 8):=Ram_data;
-						count_i<=0;
-						timeout:=0;
-						next_loadinst <= readmem;
-						else
-						  count_i<=3;
-						 end if;
-						report "Readptr " & image(ptr);
-					else
-					
-					end if;
-					
-				if dma_rd_grant = '0' then
-				  assert true report "Mauvaise lecture" severity failure;
-				  timeout:=timeout+1;
-				end if;
-			when readmem =>
-          if fifo_full='0' then
-						if ilen >0 then
-						if count=0 then 
-							iptr:=to_integer(unsigned(ptr));
-							AdrTmp:=iptr;
-							if dma_rd_grant = '1' then 
-							count_i <=count+1;
-							fifo_wr_i<='0';
-							end if;
-						elsif	 count=1 then 
-							if dma_rd_grant = '1' then 
-							count_i <=count+1;
-							fifo_wr_i<='0';
-							end if;
-						elsif	 count=2 then 
-						 if dma_rd_grant = '1' then 
-							count_i <=count+1;
-							fifo_wr_i<='0';
-						else 
-						  count_i<=1;
-						  end if;
-						elsif	 count=3 then 
-							count_i <=count+1;		
-							fifo_wr_i<='1'; --écriture de la donnée dans le fifo
-							Ilen_i<=Ilen-1;
-							AdrTmp:=Adr_Ptr+1;
-						elsif count=4 then
-							fifo_wr_i<='0';
-							count_i<=1;
-						end if;
-						else --Ilen=0 ?
-						  fifo_wr_i<='0';
-						  next_loadinst<=freebus;
-						end if;		
-					end if;
-						
-				Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16));
-				if dma_rd_grant = '0' or Fifo_full='1' then 
-				  timeout:=timeout+1;
-				  fifo_wr_i<='0';
-				  Count_i<=1; --recommencer les cycles d'attente de la donnée
-					if timeout=200 then
-						next_loadinst<=st_timeout;
-					end if;
-				end if;
-				
-         when freebus =>
-				fifo_wr_i<='0';
-				count_i<=0;
-				 Ram_address_i<=(others=>'0');
-            if instruction_en='0' then 
-					next_loadinst <= init;
-				end if;
-			when st_timeout =>
-				fifo_wr_i<='0';
-			 Ram_address_i<=(others=>'0');
-				next_loadinst<=init;
-				report "Copie D'instruction ***  RAM/Fifo a été indisponible pour trop longtemps !!!";
-				count_i<=0;
-      end case;      
-   end process;
-
-end Behavioral;
-