Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_MUX.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_MUX.vhd	(revision 98)
+++ 	(revision )
@@ -1,96 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    21:45:28 07/26/2012 
--- Design Name: 
--- Module Name:    RAM_MUX - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
--- Multiplexeur de la memoire du noeud
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-library NocLib ;
---use IEEE.STD_LOGIC_ARITH.ALL;
---use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use NocLib.CoreTypes.all;
-use work.Packet_type.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-USE ieee.numeric_std.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity RAM_MUX is
-    Port ( ram_ena_in : in  STD_LOGIC_VECTOR (1 downto 0);
-           ram_enb_in : in  STD_LOGIC_VECTOR (1 downto 0);
-           ram_we_in : in  STD_LOGIC_VECTOR (1 downto 0);
-           ram_dina_in_0 : in  STD_LOGIC_VECTOR (word - 1 downto 0);
-           ram_dina_in_1 : in  STD_LOGIC_VECTOR (word - 1 downto 0);
-           ram_addra_in_0 : in  STD_LOGIC_VECTOR (ADRLEN - 1  downto 0);
-           ram_addra_in_1 : in  STD_LOGIC_VECTOR (ADRLEN - 1  downto 0);
-			  ram_addrb_in_0 : in  STD_LOGIC_VECTOR (ADRLEN - 1  downto 0);
-           ram_addrb_in_1 : in  STD_LOGIC_VECTOR (ADRLEN - 1  downto 0);
-           ram_dob_in : in  STD_LOGIC_VECTOR (word - 1   downto 0);
-          
-			  
-			  ram_ena_out : out  STD_LOGIC;
-           ram_enb_out : out  STD_LOGIC;
-           ram_we_out : out  STD_LOGIC;
-           ram_dina_out : out  STD_LOGIC_VECTOR (word - 1 downto 0);
-           ram_addra_out : out  STD_LOGIC_VECTOR (ADRLEN - 1  downto 0);
-   		  ram_addrb_out : out  STD_LOGIC_VECTOR (ADRLEN - 1  downto 0);
-           ram_dob_out_0 : out  STD_LOGIC_VECTOR (word - 1   downto 0);
-			  ram_dob_out_1 : out  STD_LOGIC_VECTOR (word - 1   downto 0);
-			  sel : in std_logic
-			  );
-end RAM_MUX;
-
-architecture Behavioral of RAM_MUX is
-
-begin
-
-mux : process(sel,ram_ena_in,ram_enb_in ,ram_we_in,ram_dina_in_0, ram_dina_in_1,ram_addra_in_0,ram_addra_in_1, ram_addrb_in_0, ram_addrb_in_1, ram_dob_in)
- begin
-      
-		  if sel = '1' then
-	  -- si sel est à 1 les entrées 1 sont sur les sorties correspondantes
-	        ram_ena_out <= ram_ena_in(1);
-           ram_enb_out <= ram_enb_in(1);
-           ram_we_out <= ram_we_in(1);
-           ram_dina_out <= ram_dina_in_1;
-           ram_addra_out <= ram_addra_in_1;
-   		  ram_addrb_out <= ram_addrb_in_1 ;
-           ram_dob_out_1 <= ram_dob_in;	
-           ram_dob_out_0 <= (others => '0');			  
-			else 
-	  -- si est à 0 les entrées 0 sont sur les sorties correspondantes
-	        ram_ena_out <= ram_ena_in(0);
-           ram_enb_out <= ram_enb_in(0);
-           ram_we_out <= ram_we_in(0);
-           ram_dina_out <= ram_dina_in_0;
-           ram_addra_out <= ram_addra_in_0;
-   		  ram_addrb_out <= ram_addrb_in_0 ;
-			  ram_dob_out_0 <= ram_dob_in;	
-           ram_dob_out_1 <= (others => '0');
-	 
-	 end if;
- 
- 
- end process;
-
-
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_block.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/RAM_block.vhd	(revision 98)
+++ 	(revision )
@@ -1,228 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer:  GAMOM NGOUNOU 
--- 
--- Create Date:    18:33:31 03/05/2012 
--- Design Name: 
--- Module Name:    RAM_32_32 - Behavioral 
--- Project Name: MPI_Core
--- Target Devices: 
--- Tool versions: 
--- Description: permet de stocker les données locales de la librairie MPI
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity RAM_v is
-generic(width : positive:=32; Size:positive:=16);
-Port ( clka, clkb : in std_logic;
-				reset: in std_logic;
-			  wea : in std_logic;
-			  ena, enb : in std_logic;
-			  addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse
-			  dia : in std_logic_vector(width-1 downto 0);
-			  dob : out std_logic_vector(width-1 downto 0));
-end RAM_v;
-
-architecture Behavioral of RAM_v is
-	attribute RAM_STYLE : string;
-	signal Lra,Lrb :std_logic:='0';
-	signal doado,dobdo:std_logic_vector(15 downto 0);
-	signal DOPBDOP : std_logic_vector(1 downto 0);
-	signal ADDRAWRADDR,ADDRBRDADDR :std_logic_vector(13 downto 0);
-	signal REGCEA:std_logic;
-	signal  DIADI :std_logic_vector(15 downto 0);  -- 16-bit input: A port data/LSB data input
-   signal  DIPADIP :std_logic_vector(1 downto 0);  -- 2-bit input: A port parity/LSB parity input
-	signal REGCEBREGCE :std_logic ; -- 1-bit input: B port register enable/Register enable input
-   signal  RSTBRST :std_logic ;         -- 1-bit input: B port set/reset input
-   signal  WEBWEU :std_logic_vector(1 downto 0):=(others=>'0') ;          -- 2-bit input: B port write enable input
-      -- Port B Data: 16-bit (each) input: Port B data
-   signal   DIBDI :std_logic_vector(15 downto 0):=(others=>'1');             -- 16-bit input: B port data/MSB data input
-   signal    DIPBDIP :std_logic_vector(1 downto 0):=(others=>'1');         -- 2-bit input: B port parity/MSB parity input
-	signal sel : std_logic_vector(1 downto 0);
-	signal doa,dout : std_logic_vector(width-1 downto 0);
-	type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0);
-	signal RAM: ram_type;
-	attribute RAM_STYLE of RAM: signal is "BLOCK";
-begin
- -- RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM
-   --            Spartan-6
-   -- Xilinx HDL Language Template, version 13.3
-
-   RAMB8BWER_inst : RAMB8BWER
-   generic map (
-      -- DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36'
-      DATA_WIDTH_A => 9,
-      DATA_WIDTH_B => 9,
-      -- DOA_REG/DOB_REG: Optional output register (0 or 1)
-      DOA_REG => 0,
-      DOB_REG => 0,
-      -- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
-      EN_RSTRAM_A => TRUE,
-      EN_RSTRAM_B => TRUE,
-      -- INITP_00 to INITP_03: Initial memory contents.
-      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      -- INIT_00 to INIT_1F: Initial memory contents.
-      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
-      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-      -- INIT_A/INIT_B: Initial values on output port
-      INIT_A => X"00000",
-      INIT_B => X"00000",
-      -- INIT_FILE: Not Supported
-      INIT_FILE => "NONE",                                                             -- Do not modify
-      -- RAM_MODE: "SDP" or "TDP" 
-      RAM_MODE => "TDP",
-      -- RSTTYPE: "SYNC" or "ASYNC" 
-      RSTTYPE => "SYNC",
-      -- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR" 
-      RST_PRIORITY_A => "CE",
-      RST_PRIORITY_B => "CE",
-      -- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE" 
-      SIM_COLLISION_CHECK => "ALL",
-      -- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
-      SRVAL_A => X"00000",
-      SRVAL_B => X"00000",
-      -- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" 
-      WRITE_MODE_A => "WRITE_FIRST",
-      WRITE_MODE_B => "WRITE_FIRST" 
-   )
-   port map (
-      -- Port A Data: 16-bit (each) output: Port A data
-      DOADO => DOADO,             -- 16-bit output: A port data/LSB data output
-      DOPADOP => DOPADOP,         -- 2-bit output: A port parity/LSB parity output
-      -- Port B Data: 16-bit (each) output: Port B data
-      DOBDO => DOBDO,             -- 16-bit output: B port data/MSB data output
-      DOPBDOP => DOPBDOP,         -- 2-bit output: B port parity/MSB parity output
-      -- Port A Address/Control Signals: 13-bit (each) input: Port A address and control signals (write port
-      -- when RAM_MODE="SDP")
-      ADDRAWRADDR => ADDRAWRADDR, -- 13-bit input: A port address/Write address input
-      CLKAWRCLK => CLKA,     -- 1-bit input: A port clock/Write clock input
-      ENAWREN => ENA,         -- 1-bit input: A port enable/Write enable input
-      REGCEA => REGCEA,           -- 1-bit input: A port register enable input
-      RSTA => Reset,               -- 1-bit input: A port set/reset input
-      WEAWEL => WEA,           -- 2-bit input: A port write enable input
-      -- Port A Data: 16-bit (each) input: Port A data
-      DIADI => DIADI,             -- 16-bit input: A port data/LSB data input
-      DIPADIP => DIPADIP,         -- 2-bit input: A port parity/LSB parity input
-      -- Port B Address/Control Signals: 13-bit (each) input: Port B address and control signals (read port
-      -- when RAM_MODE="SDP")
-      ADDRBRDADDR => ADDRBRDADDR, -- 13-bit input: B port address/Read address input
-      CLKBRDCLK => clkb,     -- 1-bit input: B port clock/Read clock input
-      ENBRDEN => ENB,         -- 1-bit input: B port enable/Read enable input
-      REGCEBREGCE => REGCEBREGCE, -- 1-bit input: B port register enable/Register enable input
-      RSTBRST => reset,         -- 1-bit input: B port set/reset input
-      WEBWEU => WEBWEU,           -- 2-bit input: B port write enable input
-      -- Port B Data: 16-bit (each) input: Port B data
-      DIBDI => DIBDI,             -- 16-bit input: B port data/MSB data input
-      DIPBDIP => DIPBDIP          -- 2-bit input: B port parity/MSB parity input
-   );
- 
- DIADI(width-1 downto 0)<=dia;
- ADDRAWRADDR <=addra(10 downto 0);
- ADDRBRDADDR <=addrb(10 downto 0);
- doa<=DOADO(width-1 downt0 0);
- dout<=DOBDO(width-1 downt0 0);
- process (clka)
-	begin
-		if clka'event and clka = '1' then
-			if ena = '1' then
-				if wea = '1' then
-				  if conv_integer(addra)>8191 then
-				      report  "Erreur d'adresse";
-				  else
-          					--RAM(conv_integer(addra)) <= dia;
-					end if;
-				end if;
-				if conv_integer(addrb)>8191 then
-				      report  "Erreur d'adresse";
-				  else	
-				--doa<=RAM(conv_integer(addrb));
-			   end if;
-				Lra<='1';
-			else 
-				if lrb='1' then
-						Lra<='0';
-				end if;
-			end if;
-		 end if;
- end process;
-
- 
- process (clkb)	
- begin
-		if clkb'event and clkb = '1' then
-			if enb = '1' then
-				Lrb<='1';	
-				if conv_integer(addrb)>8191 then
-				      report  "Erreur d'adresse";
-				  else	
-				  --dout <= RAM(conv_integer(addrb)) ;
-				end if;
-			else
-				if Lra='1' then
-					Lrb<='0';
-				end if;
-			end if;
-		end if;
- end process;
- 
- sel<=(Lra,Lrb);
- With  sel select
- dob <=dout when "11",
-      doa  when "10",
-		dout when "01",
-		dout when "00",
-		dout when others;
-		
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/SetBit.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/SetBit.vhd	(revision 98)
+++ 	(revision )
@@ -1,187 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    20:30:11 08/01/2013 
--- Design Name: 
--- Module Name:    SetBit - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-Library NocLib;
-use NoCLib.CoreTypes.all;
---use work.packet_type.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity SetBit is
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-			  BitMask : in std_logic_vector(Word-1 downto 0);
-			  BitVal : in std_logic;
-			  whole : in std_logic;			  
-			  dma_wr_grant : in  STD_LOGIC;
-				dma_wr_request : out  STD_LOGIC;
-				dma_rd_grant : in  STD_LOGIC;
-				dma_rd_request : out  STD_LOGIC;
-				ram_rd : out std_logic;
-				ram_wr : out std_logic;
-				start : in std_logic;
-				done :  out std_logic;
-				ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage
-				Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-				Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0));
-end SetBit;
-
-architecture Behavioral of SetBit is
-signal State,Next_State:natural range 0 to 15 :=0;
-signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
-signal tempval,tempval_i : std_logic_vector(Word-1 downto 0):=(others=>'1');
-begin
-PSetBit_sync:process(clk,reset)
-
-begin
-if rising_edge(clk) then
-if reset='1' then
-	State<=0;
-	Tempval<=(others=>'0');
-else
-  State<=Next_State;
-  Tempval<=tempval_i;
-end if;
-end if;
-end process;
-
-PSetBit:process (State,tempval,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out)
-  begin
-    Next_State<=State;
-
-    tempval_i<=tempval;
-	 wr_ok<='0';
-	 rd_ok<='0';
-if State >0  then     
-			
-		dma_wr<='1';  --demander un accès exclusif au bus
-		dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-	else
-		dma_wr<='0';										
-		dma_rd<='0';
-	end if;
-case State is
-when 0 =>Ram_data_in<=tempval;
-  rd_ok<='0';
-		Wr_ok<='0';
-		done<='0';
-	if  start='1' and whole='1' then
-	 Next_State<=5;
-	 wr_ok<='0';
-	 ram_data_in<=bitmask;
-	 elsif start='1' then
-		Next_State<=State+1;
-		end if;
-		
-when 1=>	Ram_data_in<=tempval;
-		if dma_rd_grant='1' then
-		Next_State<=State+1;
-		
-		end if;
-		rd_ok<='1';
-		wr_ok<='0';
-		done<='0';
-	When 2|3=>Ram_data_in<=Ram_data_out;
-		if dma_rd_grant='1' then --cycle d'attente
-			Next_State<=State+1;
-		else
-		  Next_State<=1; --recommencer l'attente si perte de priorité
-		end if;
-			rd_ok<='1';
-			wr_ok<='0';
-			done<='0';
-	When 4 =>
-			Ram_data_in<=ram_data_out;
-			done<='0';
-			rd_ok<='1';
-			if dma_rd_grant='1' and dma_wr_grant='1' then
-				Next_State<=5;
-				--tempval<=Ram_data_out;
---				if bitval='1' then 
---					tempval<= Ram_data_out or BitMask;  	
---				else
---					tempval<= Ram_data_out and not (BitMask);
---				end if;
-				if whole='1' then
-				  --ram_data_in<=bitmask;
-				  tempval_i<=  BitMask;
-				 else
-				 if bitval='1' then
-					--ram_data_in<=Ram_data_out or BitMask; 
-					tempval_i<= Ram_data_out or BitMask; 
-				  else
-					--Ram_data_in<=Ram_data_out and not (BitMask);
-					tempval_i<= Ram_data_out and not (BitMask);
-				  end if;
-				end if;
-				rd_ok<='1';
-				wr_ok<='1';
-			else
-			  Next_State<=State;
-			  report "SetBit:Impossible d'avoir accès en R/W à la RAM";
-			end if;
-	When 5 |6 =>
-	Ram_data_in<=tempval;
-	  if dma_wr_grant='1' then
-	       if whole='1' then
-				    ram_data_in<=bitmask;
-				 else
-				    ram_data_in<=tempval;
-				end if;
-				Next_State<=State+1;
-		else
-		    Next_state<=5;
-		end if;
-		wr_ok<='1';
-		rd_ok<='1';
-		done<='0';
-	When 7=>
-		done<='1';
-		if start='0' then
-    		Next_State<=0;
- 	    wr_ok<='0';	
-		end if;
-		rd_ok<='0';
-		wr_ok<='0';
-		Ram_data_in<=tempval;
-	When others =>
-	  Next_State<=0;
-	  rd_ok<='0';
-		wr_ok<='0';
-		done<='0';
-		Ram_data_in<=tempval;
-end case;
-
-end process PSetBit;
-dma_rd_request <= dma_rd;
-dma_wr_request <=dma_wr;
-Ram_wr<=wr_ok;
-Ram_rd<=rd_ok;
---Ram_data_out<=data_to_ram;
- 
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/SetBit.vhd.bak
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/SetBit.vhd.bak	(revision 98)
+++ 	(revision )
@@ -1,187 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    20:30:11 08/01/2013 
--- Design Name: 
--- Module Name:    SetBit - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-Library NocLib;
-use NoCLib.CoreTypes.all;
---use work.packet_type.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity SetBit is
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-			  BitMask : in std_logic_vector(Word-1 downto 0);
-			  BitVal : in std_logic;
-			  whole : in std_logic;			  
-			  dma_wr_grant : in  STD_LOGIC;
-				dma_wr_request : out  STD_LOGIC;
-				dma_rd_grant : in  STD_LOGIC;
-				dma_rd_request : out  STD_LOGIC;
-				ram_rd : out std_logic;
-				ram_wr : out std_logic;
-				start : in std_logic;
-				done :  out std_logic;
-				ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage
-				Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
-				Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0));
-end SetBit;
-
-architecture Behavioral of SetBit is
-signal State,Next_State:natural range 0 to 15 :=0;
-signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
-signal tempval,tempval_i : std_logic_vector(Word-1 downto 0):=(others=>'1');
-begin
-PSetBit_sync:process(clk,reset)
-
-begin
-if rising_edge(clk) then
-if reset='1' then
-	State<=0;
-	Tempval<=(others=>'0');
-else
-  State<=Next_State;
-  Tempval<=tempval_i;
-end if;
-end if;
-end process;
-
-PSetBit:process (State,tempval,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out)
-  begin
-    Next_State<=State;
-
-    tempval_i<=tempval;
-	 wr_ok<='0';
-	 rd_ok<='0';
-if State >0  then     
-			
-		dma_wr<='1';  --demander un accès exclusif au bus
-		dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
-	else
-		dma_wr<='0';										
-		dma_rd<='0';
-	end if;
-case State is
-when 0 =>Ram_data_in<=tempval;
-  rd_ok<='0';
-		Wr_ok<='0';
-		done<='0';
-	if  start='1' and whole='1' then
-	 Next_State<=5;
-	 wr_ok<='1';
-	 ram_data_in<=bitmask;
-	 elsif start='1' then
-		Next_State<=State+1;
-		end if;
-		
-when 1=>	Ram_data_in<=tempval;
-		if dma_rd_grant='1' then
-		Next_State<=State+1;
-		
-		end if;
-		rd_ok<='1';
-		wr_ok<='0';
-		done<='0';
-	When 2|3=>Ram_data_in<=Ram_data_out;
-		if dma_rd_grant='1' then --cycle d'attente
-			Next_State<=State+1;
-		else
-		  Next_State<=1; --recommencer l'attente si perte de priorité
-		end if;
-			rd_ok<='1';
-			wr_ok<='0';
-			done<='0';
-	When 4 =>
-			Ram_data_in<=ram_data_out;
-			done<='0';
-			rd_ok<='1';
-			if dma_rd_grant='1' and dma_wr_grant='1' then
-				Next_State<=5;
-				--tempval<=Ram_data_out;
---				if bitval='1' then 
---					tempval<= Ram_data_out or BitMask;  	
---				else
---					tempval<= Ram_data_out and not (BitMask);
---				end if;
-				if whole='1' then
-				  --ram_data_in<=bitmask;
-				  tempval_i<=  BitMask;
-				 else
-				 if bitval='1' then
-					--ram_data_in<=Ram_data_out or BitMask; 
-					tempval_i<= Ram_data_out or BitMask; 
-				  else
-					--Ram_data_in<=Ram_data_out and not (BitMask);
-					tempval_i<= Ram_data_out and not (BitMask);
-				  end if;
-				end if;
-				rd_ok<='1';
-				wr_ok<='1';
-			else
-			  Next_State<=State;
-			  report "SetBit:Impossible d'avoir accès en R/W à la RAM";
-			end if;
-	When 5 |6 =>
-	Ram_data_in<=tempval;
-	  if dma_wr_grant='1' then
-	       if whole='1' then
-				    ram_data_in<=bitmask;
-				 else
-				    ram_data_in<=tempval;
-				end if;
-				Next_State<=State+1;
-		else
-		    Next_state<=5;
-		end if;
-		wr_ok<='1';
-		rd_ok<='1';
-		done<='0';
-	When 7=>
-		done<='1';
-		if start='0' then
-    		Next_State<=0;
- 	    wr_ok<='0';	
-		end if;
-		rd_ok<='0';
-		wr_ok<='0';
-		Ram_data_in<=tempval;
-	When others =>
-	  Next_State<=0;
-	  rd_ok<='0';
-		wr_ok<='0';
-		done<='0';
-		Ram_data_in<=tempval;
-end case;
-
-end process PSetBit;
-dma_rd_request <= dma_rd;
-dma_wr_request <=dma_wr;
-Ram_wr<=wr_ok;
-Ram_rd<=rd_ok;
---Ram_data_out<=data_to_ram;
- 
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/round_robbin_machine.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/round_robbin_machine.vhd	(revision 98)
+++ 	(revision )
@@ -1,79 +1,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    09:53:00 06/13/2011 
--- Design Name: 
--- Module Name:    round_robbin_machine - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity round_robbin_machine is
-    Port ( get_request_fifo_empty : in  STD_LOGIC;
-           instruction_fifo_empty : in  STD_LOGIC;
-           priority_rotation : in  STD_LOGIC;
-           clk : in  STD_LOGIC;
-           fifo_selected : out  STD_LOGIC;
-           instruction_available : out  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           mux_sel : out  STD_LOGIC);
-end round_robbin_machine;
-
-architecture Behavioral of round_robbin_machine is
-signal priority : std_logic;
-signal fifo_selected_signal : std_logic;
-
-begin
--- instruction disponible si au moins un fifo n'est pas vide
-instruction_available <= '1' when instruction_fifo_empty = '0' or get_request_fifo_empty = '0' else
-								 '0';
---signal  indiquant a EX1_FSM le fifo selectionne
-fifo_selected <= fifo_selected_signal;
-mux_sel <= fifo_selected_signal;	
-						 
-rr_machine_process : process(clk)
-begin
-	if rising_edge(clk) then
-		if reset  = '1' then
-		   priority <= '0';
-			fifo_selected_signal <= '0';
-		 elsif priority_rotation = '1' then
-		    if priority = '0' then
-			    if instruction_fifo_empty = '0' then
-				    fifo_selected_signal  <= '0';
-					elsif get_request_fifo_empty = '0' then
-					 fifo_selected_signal  <= '1';
-				  end if;
-			    priority <= '1';
-           else 
-				if get_request_fifo_empty = '0' then
-				    fifo_selected_signal  <= '1';
-					 elsif instruction_fifo_empty = '0' then
-					 fifo_selected_signal  <= '0';
-				  end if;
-			    priority <= '0';
-			  end if;
-		end if;
-	end if;
- end process;
-end Behavioral;
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/sim_fifo.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/sim_fifo.vhd	(revision 98)
+++ 	(revision )
@@ -1,185 +1,0 @@
--- TestBench Template 
--- ce module permet de tester le FIFO et de valider son fonctionnement.
-  LIBRARY ieee;
-  USE ieee.std_logic_1164.ALL;
-  USE ieee.numeric_std.ALL;
-  Library  NocLib ;
- use NocLib.CoreTypes.all;
-  ENTITY testbench IS
-  END testbench;
-
-  ARCHITECTURE behavior OF testbench IS 
-constant clk_period : time := 10 ns;
-constant MSIZE :natural :=256;
-  signal clk : std_logic := '0';
-  signal reset : std_logic := '0';
-  -- Component Declaration
-         
-component FIFO_256_FWFT  --Le FIFO à tester
-	port (
-	clk: IN std_logic;
-	din: IN std_logic_VECTOR(7 downto 0);
-	rd_en: IN std_logic;
-	srst: IN std_logic;
-	wr_en: IN std_logic;
-	dout: OUT std_logic_VECTOR(7 downto 0);
-	empty: OUT std_logic;
-	full: OUT std_logic);
-end component;
-component proto_receiv -- permet de tester la lecture dans le FIFO
-generic (sizemem : natural := 64);
- port (
- clk,reset : in std_logic;
- fifo_empty,fifo_full : in std_logic;
-  pop : out std_logic:='0';
- fifo_out : in std_logic_vector(Word-1 downto 0);
- rcv_start : in std_logic; --début de la réception
- rcv_ack :in std_logic;   -- acquittement de la réception
- rcv_comp : out std_logic; -- fin de la réception
- mem :out memory(0 to sizemem-1));
-end component;
-
-component proto_send
-generic (sizemem : natural := 64);
- port (
- clk,reset : in std_logic;
- fifo_empty,fifo_full : in std_logic;
-  push : out std_logic:='0';
- fifo_in : out std_logic_vector(Word-1 downto 0);
- snd_start : in std_logic; --début de l'emission
- snd_ack :in std_logic;   -- acquittement de l'émission
- snd_comp : out std_logic; -- fin de l'émission
- mem :in memory(0 to sizemem-1));
- 
- end component;
- 
-type typ_snd_rec is ( fillmem,send1, send2, recv1,recv2);
-type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end);
-			signal storage1,storage2 : memory (0 to MSIZE-1);
-          SIGNAL fifo_empty,fifo_full :  std_logic:='0';
-			 signal push,pop ,spush,spop:  std_logic:='0';
-          SIGNAL data_in,data_out:  std_logic_vector(7 downto 0);
-          signal ROn,Rdone,RAck:std_logic:='0';
-			 signal SOn,Sdone,SAck:std_logic:='0';
-			 signal etreceiv :typ_receiv;
-			
-			 signal pipo : typ_snd_rec;
-
-  BEGIN
-			
-  
-
-uut : FIFO_256_FWFT
-		port map (
-			clk => clk,
-			din => data_in,
-			rd_en => pop,
-			srst => reset,
-			wr_en => push,
-			dout => data_out,
-			empty => fifo_empty,
-			full => fifo_full);
-			
-rec_pro: proto_receiv generic map(sizemem =>MSIZE)
-	port map (clk=>clk,
-				reset=>reset,
-				fifo_empty=>fifo_empty,
-				fifo_full=>fifo_full,
-				rcv_start =>Ron,
-				rcv_ack => Rack,
-				rcv_comp=> Rdone,
-				pop=>pop,
-				fifo_out =>data_out,
-				mem=>storage2
-				);
-snd_pro: proto_send generic map (sizemem =>MSIZE)
-port map (clk=>clk,
-				reset=>reset,
-				fifo_empty=>fifo_empty,
-				fifo_full=>fifo_full,
-				snd_start =>Son,
-				snd_ack => Sack,
-				snd_comp=> Sdone,
-				push=>push,
-				fifo_in =>data_in,
-				mem=>storage1
-				);
- clk_process :process
-   begin
-		clk <= '0';
-		wait for clk_period/2;
-		clk <= '1';
-		wait for clk_period/2;
-		
-   end process;
-reset_proc: process 
-   begin		
-      -- hold reset state for 100 ns.
-      reset<='0';
-		wait for 1 ns;	
-		reset<='1';
-      wait for clk_period*10;
-		reset<='0';
-		wait;
-      -- insert stimulus here 
-end process;
-pr_pingpong : process(clk,reset)
-variable i: natural range 0 to MSIZE-1;
-begin
-if reset='1' then
-	pipo<=fillmem;
-	i:=0;
-	else
-	if rising_edge(clk) then
-	case pipo is
-		when fillmem => -- remplissage de la mémoire d'envoie
-		if i=0 then
-		storage1(0)<=x"51"; -- le code de la fonction
-		elsif i=1 then
-		storage1(1)<=x"05"; -- le nombre d'octets à envoyer dans le tampon.
-		elsif (i>=2) and (i<= MSIZE-2) then
-		storage1(i)<=std_logic_vector(to_unsigned(i-2,Word));
-		
-		else
-			pipo<=send1;
-			i:=0;
-		end if;
-		i:=i+1;
-		when send1 =>
-			
-			Son<='1'; --activer l'emission des données
-			Sack<='0';
-			if i=2 then --activer la réception des données
-				Ron<='1';
-			else 
-				Ron<='0';
-				i:=i+1;
-			end if;
-			if sdone='1' then
-				pipo<=send2;
-						
-			end if;
-		when send2 =>
-			i:=0;
-			Son<='0';
-			Sack<='1';
-			pipo<=recv1;
-		when recv1 =>
-			ron<='1';
-			rack<='0';
-			if Rdone='1' then
-				pipo<=recv2;
-			end if;
-		when recv2 =>
-			Ron<='0';
-			Rack<='1';
-			pipo<=send1;
-			i:=0;
-	end case;
-		
-	
-	end if;
-end if;
-end process;
-
-END;
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/test_DMA.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/test_DMA.vhd	(revision 98)
+++ 	(revision )
@@ -1,295 +1,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   14:37:10 03/18/2013
--- Design Name:   
--- Module Name:   C:/Core MPI/CORE_MPI/test_DMA.vhd
--- Project Name:  MPI_CORE_COMPONENTS
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: DMA_ARBITER
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
-ENTITY test_DMA IS
-END test_DMA;
- 
-ARCHITECTURE behavior OF test_DMA IS 
- 
-    -- Component Declaration for the Unit Under Test (UUT)
- 
-    COMPONENT DMA_ARBITER
-    PORT(
-         dma_rd_request : IN  std_logic_vector(3 downto 0);
-         data_wr_in : IN  std_logic_vector(7 downto 0);
-         data_rd_out : OUT  std_logic_vector(7 downto 0);
-         address_rd : IN  std_logic_vector(15 downto 0);
-         address_wr : IN  std_logic_vector(15 downto 0);
-         address_out_wr : OUT  std_logic_vector(15 downto 0);
-         address_out_rd : OUT  std_logic_vector(15 downto 0);
-         ram_en : OUT  std_logic;
-         ram_we : OUT  std_logic;
-         data_wr_mem : OUT  std_logic_vector(7 downto 0);
-         data_rd_mem : IN  std_logic_vector(7 downto 0);
-         dma_wr_grant : OUT  std_logic_vector(3 downto 0);
-         hold_req : OUT  std_logic;
-         hold_ack : IN  std_logic;
-         clk : IN  std_logic;
-         reset : IN  std_logic;
-         dma_rd_grant : OUT  std_logic_vector(3 downto 0);
-         dma_wr_request : IN  std_logic_vector(3 downto 0)
-        );
-    END COMPONENT;
-    
-COMPONENT RAM_v
-  generic (width : positive;size :positive);
-	PORT(
-		clka : IN std_logic;
-		clkb : IN std_logic;
-		wea : IN std_logic;
-		ena : IN std_logic;
-		enb : IN std_logic;
-		addra : IN std_logic_vector;
-		addrb : IN std_logic_vector;
-		dia : IN std_logic_vector;          
-		dob : OUT std_logic_vector
-		);
-	END COMPONENT;
-   --Inputs
-   signal dma_rd_request : std_logic_vector(3 downto 0) := (others => '0');
-   signal data_wr_in : std_logic_vector(7 downto 0) := (others => '0');
-   signal address_rd : std_logic_vector(15 downto 0) := (others => '0');
-   signal address_wr : std_logic_vector(15 downto 0) := (others => '0');
-   signal data_rd_mem : std_logic_vector(7 downto 0) := (others => '0');
-   signal hold_ack : std_logic := '0';
-   signal clk : std_logic := '0';
-   signal reset : std_logic := '0';
-   signal dma_wr_request : std_logic_vector(3 downto 0) := (others => '0');
-	
- 	--Outputs
-   signal data_rd_out : std_logic_vector(7 downto 0);
-   signal address_out_wr : std_logic_vector(15 downto 0);
-   signal address_out_rd : std_logic_vector(15 downto 0);
-   signal ram_en : std_logic;
-   signal ram_we : std_logic;
-   signal data_wr_mem : std_logic_vector(7 downto 0);
-   signal dma_wr_grant : std_logic_vector(3 downto 0);
-   signal hold_req : std_logic;
-   signal dma_rd_grant : std_logic_vector(3 downto 0);
-
-   -- Clock period definitions
-   constant clk_period : time := 10 ns;
- 
-BEGIN
- 
-	-- Instantiate the Unit Under Test (UUT)
-   uut: DMA_ARBITER PORT MAP (
-          dma_rd_request => dma_rd_request,
-          data_wr_in => data_wr_in,
-          data_rd_out => data_rd_out,
-          address_rd => address_rd,
-          address_wr => address_wr,
-          address_out_wr => address_out_wr,
-          address_out_rd => address_out_rd,
-          ram_en => ram_en,
-          ram_we => ram_we,
-          data_wr_mem => data_wr_mem,
-          data_rd_mem => data_rd_mem,
-          dma_wr_grant => dma_wr_grant,
-          hold_req => hold_req,
-          hold_ack => hold_ack,
-          clk => clk,
-          reset => reset,
-          dma_rd_grant => dma_rd_grant,
-          dma_wr_request => dma_wr_request
-        );
-
-Inst_RAM_v: RAM_v generic map(width=>8,size=>16)
-	PORT MAP(
-		clka =>clk,
-		clkb => clk,
-		wea => ram_we,
-		ena => ram_en,
-		enb => ram_en,
-		addra => address_out_wr,
-		addrb =>address_out_rd,
-		dia => data_wr_mem,
-		dob => data_rd_mem 
-	);
-   -- Clock process definitions
-   clk_process :process
-   begin
-		clk <= '0';
-		wait for clk_period/2;
-		clk <= '1';
-		wait for clk_period/2;
-   end process;
- 
-
-   -- Stimulus process
-   reset_proc: process
-   begin		
-      -- hold reset state for 100 ns.
-		reset <='1';
-      wait for 100 ns;	
-		reset<='0';
-      wait for clk_period*10;
-		
-      -- insert stimulus here 
-
-      wait;
-   end process;
-	
-	stim_proc: process (clk,reset) 
-	variable i,j,k,l : std_logic_vector(15 downto 0);
-	variable x: integer ; --indique le temps à partir duquel chaque 
-	--permet de faire des requêtes DMA et de les valider
-   begin	
-		if rising_edge(clk) then
-			if reset ='1' then 
-				x:=0;
-			else
-				x:=x+1;
-				if x>=1 and x<=20 then
-				dma_rd_request<="0001";
-				elsif x>=21 and x<=40 then
-				dma_rd_request<="0011";
-				elsif x>=41 and x<=60 then
-				dma_rd_request<="0010";
-				elsif x>=61 and x<=80 then
-				dma_rd_request<="0110";
-				elsif x>=81 and x<=100 then
-				dma_rd_request<="0100";
-				elsif x>=61 and x<=80 then
-				dma_rd_request<="1100";
-				elsif x>=101 and x<=120 then
-				dma_rd_request<="1101";
-				elsif x>=121 and x<=140 then
-				dma_rd_request<="1001";
-				elsif x>=141 and x<=160 then
-				dma_rd_request<="1000";
-				elsif x>=161 and x<=180 then
-				dma_rd_request<="0000";
-				elsif x>=181 and x<=200 then
-				dma_rd_request<="0111";
-				elsif x>=181 and x<=200 then
-				dma_rd_request<="1111";
-				elsif x>=181 and x<=200 then
-				dma_rd_request<="1110";
-				else
-					x:=0;
-				
-				end if;
-	
-			end if;
-      end if;
-   end process;
-stim2_proc: process (clk,reset) 
-	variable i,j,k,l : std_logic_vector(15 downto 0);
-	variable x: integer ; --indique le temps à partir duquel chaque 
-	--permet de faire des requêtes DMA et de les valider
-   begin	
-		if rising_edge(clk) then
-			if reset ='1' then 
-				x:=0;
-			else
-				x:=x+1;
-				if x>=1 and x<=10 then
-				dma_wr_request<="0001";
-				elsif x>=11 and x<=20 then
-				dma_wr_request<="0011";
-				elsif x>=21 and x<=30 then
-				dma_wr_request<="0010";
-				elsif x>=31 and x<=40 then
-				dma_wr_request<="0110";
-				elsif x>=41 and x<=50 then
-				dma_wr_request<="0100";
-				elsif x>=51 and x<=60 then
-				dma_wr_request<="1100";
-				elsif x>=61 and x<=80 then
-				dma_wr_request<="1101";
-				elsif x>=81 and x<=90 then
-				dma_wr_request<="1001";
-				elsif x>=91 and x<=100 then
-				dma_wr_request<="1000";
-				elsif x>=101 and x<=110 then
-				dma_wr_request<="0000";
-				elsif x>=111 and x<=120 then
-				dma_wr_request<="0111";
-				elsif x>=121 and x<=130 then
-				dma_wr_request<="1111";
-				elsif x>=131 and x<=200 then
-				dma_wr_request<="1110";
-				else
-					x:=0;
-				
-				end if;
-	
-			end if;
-      end if;
-   end process;
-liredat:process (dma_rd_grant)
-begin
-
-
-if dma_rd_grant="0001" then
-address_rd<=x"0000";
-elsif dma_rd_grant="0010" then
-address_rd<=x"0002";
-elsif dma_rd_grant="0100" then
-address_rd<=x"0004";
-elsif dma_rd_grant="1000" then
-address_rd<=x"0006";
-else
-
- address_rd<=x"0000";
-end if;
-
-end process;
-ecriredat:process (dma_wr_grant)
-begin
-
-
-if dma_wr_grant="0001" then
-address_wr<=x"0000";
-data_wr_in<=x"0a";
-elsif dma_rd_grant="0010" then
-address_wr<=x"0002";
-data_wr_in<=x"20";
-elsif dma_rd_grant="0100" then
-address_wr<=x"0004";
-data_wr_in<=x"a0";
-elsif dma_rd_grant="1000" then
-address_wr<=x"0006";
-data_wr_in<=x"0F";
-else
-
- address_wr<=x"0000";
- 
-end if;
-
-end process;
-Hold_ack<=Hold_req; -- toujours autoriser la gestion de la mémoire par le DMA
-
-END;