xilinx.com
CoreGen
mem_coregen
1.0
blk_mem_gen_v6_2
blk_mem_gen_v6_2
Native
AXI4_Full
Memory_Slave
false
4
Simple_Dual_Port_RAM
No_ECC
false
false
false
Single_Bit_Error_Injection
true
8
Minimum_Area
8kx2
false
8
4096
8
WRITE_FIRST
Use_ENA_Pin
8
8
WRITE_FIRST
Use_ENB_Pin
false
false
false
false
false
false
false
false
0
false
no_coe_file_loaded
false
0
false
false
CE
0
false
false
CE
0
SYNC
false
100
50
100
0
100
100
ALL
false
false
spartan6
spartan6
D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/
0
1
0
0
4
1
8
1
1
0
no_coe_file_loaded
0
0
SYNC
0
CE
0
0
1
0
1
1
WRITE_FIRST
8
8
4096
4096
12
0
CE
0
0
1
0
1
1
WRITE_FIRST
8
8
4096
4096
12
0
0
0
0
0
0
0
0
0
0
ALL
0
0
0
mem_coregen
./
./tmp/
./tmp/_cg/
xc6slx45
spartan6
csg324
-3
BusFormatAngleBracketNotRipped
VHDL
true
Other
false
false
false
Ngc
false
Behavioral
VHDL
false
2011-03-11T08:24:14.000Z
apply_current_project_options_generator
customization_generator
./summary.log
unknown
Mon Mar 03 07:01:21 GMT 2014
0x4F489DB4
generationid_4243181522
model_parameter_resolution_generator
./summary.log
unknown
Mon Mar 03 07:01:29 GMT 2014
0x4F489DB4
generationid_4243181522
ip_xco_generator
./blk_mem_gen_v6_2.xco
xco
Mon Mar 03 07:01:30 GMT 2014
0xF014F97C
generationid_4243181522
associated_files_generator
./blk_mem_gen_ds512.pdf
pdf
Tue Oct 04 23:21:26 GMT 2011
0xA43B8952
generationid_4243181522
./blk_mem_gen_v6_2_readme.txt
txt
Tue Oct 04 23:21:26 GMT 2011
0x399E1D72
generationid_4243181522
ejava_generator
./blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf
ignore
ucf
Mon Mar 03 07:01:32 GMT 2014
0x8915DFA1
generationid_4243181522
./blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd
ignore
vhdl
Mon Mar 03 07:01:32 GMT 2014
0x39D6EEDA
generationid_4243181522
./blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc
ignore
xdc
Mon Mar 03 07:01:32 GMT 2014
0x78E2D49A
generationid_4243181522
./blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd
ignore
vhdl
Mon Mar 03 07:01:32 GMT 2014
0x5C3F6B98
generationid_4243181522
./blk_mem_gen_v6_2_ste/implement/implement.bat
ignore
unknown
Mon Mar 03 07:01:32 GMT 2014
0xE86DEA05
generationid_4243181522
./blk_mem_gen_v6_2_ste/implement/implement.sh
ignore
unknown
Mon Mar 03 07:01:32 GMT 2014
0xBF76F109
generationid_4243181522
./blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat
ignore
unknown
Mon Mar 03 07:01:32 GMT 2014
0x86FAE7F8
generationid_4243181522
./blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh
ignore
unknown
Mon Mar 03 07:01:32 GMT 2014
0xD25129D7
generationid_4243181522
./blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl
ignore
tcl
Mon Mar 03 07:01:32 GMT 2014
0x30DC827D
generationid_4243181522
./blk_mem_gen_v6_2_ste/implement/xst.prj
ignore
unknown
Mon Mar 03 07:01:32 GMT 2014
0x263C68FF
generationid_4243181522
./blk_mem_gen_v6_2_ste/implement/xst.scr
ignore
unknown
Mon Mar 03 07:01:32 GMT 2014
0xF4B7D6CF
generationid_4243181522
ngc_netlist_generator
./blk_mem_gen_v6_2.ngc
ngc
Mon Mar 03 07:03:01 GMT 2014
0xB393819B
generationid_4243181522
obfuscate_netlist_generator
padded_implementation_netlist_generator
instantiation_template_generator
./blk_mem_gen_v6_2.vho
vho
Mon Mar 03 07:03:02 GMT 2014
0xC2F71940
generationid_4243181522
structural_simulation_model_generator
./blk_mem_gen_v6_2.vhd
vhdl
Mon Mar 03 07:03:03 GMT 2014
0x509FA329
generationid_4243181522
asy_generator
./blk_mem_gen_v6_2.asy
asy
Mon Mar 03 07:03:09 GMT 2014
0x6178BCD9
generationid_4243181522
./summary.log
unknown
Mon Mar 03 07:03:09 GMT 2014
0x4F489DB4
generationid_4243181522
xmdf_generator
./blk_mem_gen_v6_2_xmdf.tcl
tclXmdf
tcl
Mon Mar 03 07:03:09 GMT 2014
0x9F2E33B8
generationid_4243181522
ise_generator
./blk_mem_gen_v6_2.gise
ignore
gise
Mon Mar 03 07:03:22 GMT 2014
0x94E343F5
generationid_4243181522
./blk_mem_gen_v6_2.xise
ignore
xise
Mon Mar 03 07:03:22 GMT 2014
0x69700327
generationid_4243181522
deliver_readme_generator
flist_generator
./blk_mem_gen_v6_2_flist.txt
ignore
txtFlist
txt
Mon Mar 03 07:03:23 GMT 2014
0xF86013AF
generationid_4243181522
view_readme_generator
mem_coregen
./
./tmp/
./tmp/_cg/
xc6slx45
spartan6
csg324
-3
BusFormatAngleBracketNotRipped
VHDL
true
Other
false
false
false
Ngc
false
Behavioral
VHDL
false