Generating component instance 'mem8k8' of 'xilinx.com:ip:blk_mem_gen:6.2' from 'C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml'. A core named 'mem8k8' already exists in the project. Output products for this core may be overwritten. Pre-processing HDL files for 'mem8k8'... Finished generation of ASY schematic symbol. Finished FLIST file generation.