Release 12.3 par M.70d (nt64) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. GAMOM-PC:: Fri Aug 03 10:50:23 2012 par -w -intstyle ise -ol high -t 1 CORE_MPI_map.ncd CORE_MPI.ncd CORE_MPI.pcf Constraints file: CORE_MPI.pcf. Loading device for application Rf_Device from file '3s1200e.nph' in environment d:\Xilinx\12.3\ISE_DS\ISE\. "CORE_MPI" is an NCD, version 3.2, device xc3s1200e, package ft256, speed -5 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc3s1200e' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.27 2010-09-15". Design Summary Report: Number of External IOBs 95 out of 190 50% Number of External Input IOBs 31 Number of External Input IBUFs 31 Number of External Output IOBs 64 Number of External Output IOBs 64 Number of External Bidir IOBs 0 Number of BUFGMUXs 3 out of 24 12% Number of Slices 791 out of 8672 9% Number of SLICEMs 40 out of 4336 1% Overall effort level (-ol): High Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 4 secs Finished initial Timing Analysis. REAL time: 4 secs Starting Placer Total REAL time at the beginning of Placer: 4 secs Total CPU time at the beginning of Placer: 1 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:605e1) REAL time: 4 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:605e1) REAL time: 4 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:605e1) REAL time: 4 secs Phase 4.2 Initial Clock and IO Placement .... Phase 4.2 Initial Clock and IO Placement (Checksum:d0963d4) REAL time: 4 secs Phase 5.30 Global Clock Region Assignment Phase 5.30 Global Clock Region Assignment (Checksum:d0963d4) REAL time: 4 secs Phase 6.36 Local Placement Optimization Phase 6.36 Local Placement Optimization (Checksum:d0963d4) REAL time: 4 secs Phase 7.3 Local Placement Optimization ... Phase 7.3 Local Placement Optimization (Checksum:540caf82) REAL time: 5 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:540caf82) REAL time: 5 secs Phase 9.8 Global Placement ............................ ............................................................... ................................... ..................................................... .......................................................... Phase 9.8 Global Placement (Checksum:3441d173) REAL time: 11 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:3441d173) REAL time: 11 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:d6f58577) REAL time: 13 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:d6f58577) REAL time: 13 secs Total REAL time to Placer completion: 13 secs Total CPU time to Placer completion: 11 secs Writing design to file CORE_MPI.ncd Starting Router Phase 1 : 5847 unrouted; REAL time: 20 secs Phase 2 : 5365 unrouted; REAL time: 20 secs Phase 3 : 1243 unrouted; REAL time: 21 secs Phase 4 : 1368 unrouted; (Par is working to improve performance) REAL time: 22 secs Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 22 secs Updating file: CORE_MPI.ncd with current fully routed design. Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 33 secs Updating file: CORE_MPI.ncd with current fully routed design. Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 35 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 35 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs WARNING:Route:455 - CLK Net:LD_instr/etloadinst_cmp_eq0022 may have excessive skew because 0 CLK pins and 2 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:LD_instr/etloadinst_cmp_eq0019 may have excessive skew because 0 CLK pins and 7 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/timeout_i_not0001 may have excessive skew because 4 CLK pins and 0 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/CM_RDY may have excessive skew because 1 CLK pins and 3 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:dma_data_in_not0001 may have excessive skew because 3 CLK pins and 0 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX1_FSM/ram_rd_or0000 may have excessive skew because 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd11 may have excessive skew because 0 CLK pins and 13 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX2_FSM/ex2_state_mach_FSM_FFd18 may have excessive skew because 1 CLK pins and 5 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd12 may have excessive skew because 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:IAck may have excessive skew because 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 may have excessive skew because 0 CLK pins and 8 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 may have excessive skew because 1 CLK pins and 10 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 may have excessive skew because 1 CLK pins and 4 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/DS_RDY may have excessive skew because 1 CLK pins and 18 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/stInit2_FSM_FFd9 may have excessive skew because 1 CLK pins and 24 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd7 may have excessive skew because 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 may have excessive skew because 0 CLK pins and 6 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:dma_rd_grant<3> may have excessive skew because 0 CLK pins and 97 NON_CLK pins failed to route using a CLK template. Total REAL time to Router completion: 36 secs Total CPU time to Router completion: 33 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clkout_OBUF | BUFGMUX_X2Y10| No | 289 | 0.178 | 0.328 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/etloadinst_ | | | | | | | cmp_eq0020 | BUFGMUX_X1Y10| No | 17 | 0.069 | 0.225 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/stI | | | | | | | nit2_FSM_FFd2 | BUFGMUX_X1Y0| No | 26 | 0.108 | 0.325 | +---------------------+--------------+------+------+------------+-------------+ | dma_rd_grant<3> | Local| | 105 | 0.099 | 2.200 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/Mtrien_Ram_ | | | | | | | address_i_not0001 | Local| | 1 | 0.000 | 0.742 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/stI | | | | | | | nit2_FSM_FFd9 | Local| | 25 | 0.000 | 1.150 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/stI | | | | | | | nit2_FSM_FFd11 | Local| | 15 | 0.000 | 1.752 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/stI | | | | | | | nit2_FSM_FFd12 | Local| | 12 | 0.000 | 1.825 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/Nex | | | | | | | tRank_or0000 | Local| | 5 | 0.008 | 1.288 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/DS_ | | | | | | | RDY | Local| | 24 | 0.739 | 2.022 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/count_i_not | | | | | | | 0001 | Local| | 10 | 0.065 | 1.634 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/Mtridata_Ra | | | | | | | m_address_i_not0001 | Local| | 14 | 0.212 | 1.819 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/etloadinst_ | | | | | | | cmp_eq0022 | Local| | 7 | 0.238 | 2.258 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/etloadinst_ | | | | | | | cmp_eq0019 | Local| | 11 | 0.132 | 1.645 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/stI | | | | | | | nit2_FSM_FFd10 | Local| | 11 | 0.000 | 1.166 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/Por | | | | | | | tNum_i_or0000 | Local| | 2 | 0.003 | 1.577 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/CTR | | | | | | | _or0000 | Local| | 1 | 0.000 | 0.980 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX1_FSM/ex1 | | | | | | |_state_mach_FSM_FFd7 | | | | | | | | Local| | 12 | 0.000 | 2.998 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_wr_grant_0_not0 | | | | | | | 001 | Local| | 1 | 0.000 | 0.979 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/Dat | | | | | | | aRam_or0000 | Local| | 4 | 0.002 | 1.323 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/Ran | | | | | | | kAsked_i_or0000 | Local| | 1 | 0.000 | 0.742 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/tim | | | | | | | eout_i_not0001 | Local| | 5 | 1.297 | 3.312 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX1_FSM/App | | | | | | | InitReq_or0000 | Local| | 1 | 0.000 | 0.717 | +---------------------+--------------+------+------+------------+-------------+ | IAck | Local| | 2 | 0.000 | 0.947 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_rd_grant_0_not0 | | | | | | | 001 | Local| | 1 | 0.000 | 0.938 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/Dat | | | | | | | aToSend_0_or0000 | Local| | 3 | 0.178 | 1.759 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/Dat | | | | | | | alen_or0000 | Local| | 3 | 0.034 | 1.010 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_wr_grant_1_cmp_ | | | | | | | eq0000 | Local| | 1 | 0.000 | 0.245 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX2_FSM/fif | | | | | | | o_wr_en_or0000 | Local| | 1 | 0.000 | 0.245 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX2_FSM/ex2 | | | | | | |_state_mach_FSM_FFd1 | | | | | | | 8 | Local| | 6 | 0.000 | 0.634 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/Cmd | | | | | | |Received_2_cmp_eq000 | | | | | | | 0 | Local| | 5 | 0.009 | 1.615 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/etc | | | | | | | md_FSM_FFd9 | Local| | 9 | 0.118 | 1.860 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_rd_grant_3_cmp_ | | | | | | | eq0000 | Local| | 5 | 0.000 | 0.997 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_rd_grant_1_cmp_ | | | | | | | eq0000 | Local| | 1 | 0.000 | 0.245 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_wr_grant_2_cmp_ | | | | | | | eq0000 | Local| | 1 | 0.000 | 0.979 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/CM_ | | | | | | | RDY | Local| | 4 | 0.000 | 0.557 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/timeout_not | | | | | | | 0001 | Local| | 6 | 0.183 | 1.801 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_rd_grant_2_cmp_ | | | | | | | eq0000 | Local| | 1 | 0.000 | 0.245 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_DMA_ARBITER | | | | | | |/dma_wr_grant_3_cmp_ | | | | | | | eq0000 | Local| | 1 | 0.000 | 0.245 | +---------------------+--------------+------+------+------------+-------------+ |LD_instr/fifo_wr_i_n | | | | | | | ot0001 | Local| | 1 | 0.000 | 0.745 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/stI | | | | | | | nit2_FSM_FFd5 | Local| | 11 | 0.031 | 1.936 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/WeR | | | | | | | am_or0000 | Local| | 1 | 0.000 | 0.981 | +---------------------+--------------+------+------+------------+-------------+ | dma_data_in_not0001 | Local| | 5 | 0.784 | 2.286 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX4_FSM/DS_ | | | | | | | Ack_or0000 | Local| | 1 | 0.000 | 0.757 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX1_FSM/ram | | | | | | | _rd_or0000 | Local| | 2 | 0.000 | 0.733 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX1_FSM/ram | | | | | | | _wr_or0000 | Local| | 1 | 0.000 | 1.040 | +---------------------+--------------+------+------+------------+-------------+ |MPI_CORE_EX1_FSM/Res | | | | | | | ult_1_or0000 | Local| | 1 | 0.000 | 1.339 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. Timing Score: 0 (Setup: 0, Hold: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net clk | SETUP | N/A| 7.585ns| N/A| 0 out_OBUF | HOLD | 0.627ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net dma | SETUP | N/A| 2.016ns| N/A| 0 _rd_grant<3> | HOLD | 1.200ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net MPI | SETUP | N/A| 4.044ns| N/A| 0 _CORE_EX4_FSM/NextRank_or0000 | HOLD | 1.076ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net LD_ | SETUP | N/A| 6.878ns| N/A| 0 instr/Mtridata_Ram_address_i_not0001 | HOLD | 1.411ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net LD_ | SETUP | N/A| 5.451ns| N/A| 0 instr/etloadinst_cmp_eq0020 | HOLD | 1.200ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net MPI | SETUP | N/A| 1.807ns| N/A| 0 _CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 | HOLD | 1.200ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net LD_ | SETUP | N/A| 3.654ns| N/A| 0 instr/timeout_not0001 | HOLD | 1.408ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net MPI | SETUP | N/A| 3.476ns| N/A| 0 _CORE_EX4_FSM/stInit2_FSM_FFd2 | HOLD | 1.450ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 37 secs Total CPU time to PAR completion: 34 secs Peak Memory Usage: 315 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 18 Number of info messages: 1 Writing design to file CORE_MPI.ncd PAR done!