Release 12.3 - par M.70d (nt64) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Fri Aug 03 10:51:00 2012 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: 1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. 2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. 3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. INPUT FILE: CORE_MPI_map.ncd OUTPUT FILE: CORE_MPI_pad.txt PART TYPE: xc3s1200e SPEED GRADE: -5 PACKAGE: ft256 Pinout by Pin Number: +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |A1 | | |GND | | | | | | | | | | | | |A2 | | |TDI | | | | | | | | | | | | |A3 | |IBUF |IP |UNUSED | |0 | | | | | | | | | |A4 | |DIFFS |IO_L17N_0/VREF_0 |UNUSED | |0 | | | | | | | | | |A5 | |DIFFM |IO_L17P_0 |UNUSED | |0 | | | | | | | | | |A6 | | |VCCAUX | | | | | | | |2.5 | | | | |A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |A8 | |DIFFMI |IP_L10P_0/GCLK8 |UNUSED | |0 | | | | | | | | | |A9 | |DIFFS |IO_L09N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |A10 | |DIFFM |IO_L09P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |A11 | | |VCCAUX | | | | | | | |2.5 | | | | |A12 | |IOB |IO |UNUSED | |0 | | | | | | | | | |A13 | |DIFFS |IO_L03N_0/VREF_0 |UNUSED | |0 | | | | | | | | | |A14 | |DIFFS |IO_L01N_0 |UNUSED | |0 | | | | | | | | | |A15 | | |TCK | | | | | | | | | | | | |A16 | | |GND | | | | | | | | | | | | |B1 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | | |B2 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | | |B3 | |DIFFS |IO_L19N_0/HSWAP |UNUSED | |0 | | | | | | | | | |B4 | |IOB |IO |UNUSED | |0 | | | | | | | | | |B5 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |B6 | |IOB |IO |UNUSED | |0 | | | | | | | | | |B7 | |DIFFM |IO_L13P_0 |UNUSED | |0 | | | | | | | | | |B8 |clk |IBUF |IP_L10N_0/GCLK9 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE | |B9 | | |GND | | | | | | | | | | | | |B10 | |IOB |IO |UNUSED | |0 | | | | | | | | | |B11 | |DIFFS |IO_L05N_0/VREF_0 |UNUSED | |0 | | | | | | | | | |B12 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |B13 | |DIFFM |IO_L03P_0 |UNUSED | |0 | | | | | | | | | |B14 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | |B15 | | |TMS | | | | | | | | | | | | |B16 | |IBUF |IP |UNUSED | |1 | | | | | | | | | |C1 | |DIFFM |IO_L02P_3 |UNUSED | |3 | | | | | | | | | |C2 | |DIFFS |IO_L02N_3/VREF_3 |UNUSED | |3 | | | | | | | | | |C3 | |DIFFM |IO_L19P_0 |UNUSED | |0 | | | | | | | | | |C4 | |DIFFS |IO_L18N_0 |UNUSED | |0 | | | | | | | | | |C5 | |DIFFM |IO_L18P_0 |UNUSED | |0 | | | | | | | | | |C6 | |DIFFM |IO_L15P_0 |UNUSED | |0 | | | | | | | | | |C7 | |DIFFS |IO_L13N_0 |UNUSED | |0 | | | | | | | | | |C8 | |DIFFM |IO_L11P_0/GCLK10 |UNUSED | |0 | | | | | | | | | |C9 | |DIFFSI |IP_L07N_0 |UNUSED | |0 | | | | | | | | | |C10 | |DIFFMI |IP_L07P_0 |UNUSED | |0 | | | | | | | | | |C11 | |DIFFM |IO_L05P_0 |UNUSED | |0 | | | | | | | | | |C12 | |DIFFSI |IP_L02N_0 |UNUSED | |0 | | | | | | | | | |C13 | |IBUF |IP |UNUSED | |0 | | | | | | | | | |C14 | | |TDO | | | | | | | | | | | | |C15 | |DIFFS |IO_L19N_1/LDC2 |UNUSED | |1 | | | | | | | | | |C16 |ram_data_out<7> |IBUF |IO_L19P_1/LDC1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |D1 | |DIFFM |IO_L05P_3 |UNUSED | |3 | | | | | | | | | |D2 | |IBUF |IP |UNUSED | |3 | | | | | | | | | |D3 | | |PROG_B | | | | | | | | | | | | |D4 | | |VCCINT | | | | | | | |1.2 | | | | |D5 | |DIFFMI |IP_L16P_0 |UNUSED | |0 | | | | | | | | | |D6 | |DIFFS |IO_L15N_0 |UNUSED | |0 | | | | | | | | | |D7 | |DIFFS |IO_L14N_0/VREF_0 |UNUSED | |0 | | | | | | | | | |D8 | |DIFFS |IO_L11N_0/GCLK11 |UNUSED | |0 | | | | | | | | | |D9 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | |D10 | |DIFFM |IO_L06P_0 |UNUSED | |0 | | | | | | | | | |D11 | |DIFFM |IO_L04P_0 |UNUSED | |0 | | | | | | | | | |D12 | |DIFFMI |IP_L02P_0 |UNUSED | |0 | | | | | | | | | |D13 | | |VCCINT | | | | | | | |1.2 | | | | |D14 |ram_data_out<6> |IBUF |IO_L18N_1/LDC0 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |D15 |ram_address_rd<12> |IOB |IO_L18P_1/HDC |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |D16 |ram_data_out<5> |IBUF |IP/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |E1 | |DIFFS |IO_L05N_3 |UNUSED | |3 | | | | | | | | | |E2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |E3 | |DIFFM |IO_L03P_3 |UNUSED | |3 | | | | | | | | | |E4 | |DIFFS |IO_L03N_3 |UNUSED | |3 | | | | | | | | | |E5 | | |VCCINT | | | | | | | |1.2 | | | | |E6 | |DIFFSI |IP_L16N_0 |UNUSED | |0 | | | | | | | | | |E7 | |DIFFM |IO_L14P_0 |UNUSED | |0 | | | | | | | | | |E8 | |DIFFM |IO_L12P_0 |UNUSED | |0 | | | | | | | | | |E9 | |DIFFM |IO_L08P_0/GCLK4 |UNUSED | |0 | | | | | | | | | |E10 | |DIFFS |IO_L06N_0 |UNUSED | |0 | | | | | | | | | |E11 | |DIFFS |IO_L04N_0 |UNUSED | |0 | | | | | | | | | |E12 | | |VCCINT | | | | | | | |1.2 | | | | |E13 |ram_address_rd<14> |IOB |IO_L17P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |E14 |ram_data_out<4> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |E15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |E16 |ram_address_rd<10> |IOB |IO_L17N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |F1 | | |VCCAUX | | | | | | | |2.5 | | | | |F2 | |IBUF |IP |UNUSED | |3 | | | | | | | | | |F3 | |DIFFM |IO_L04P_3 |UNUSED | |3 | | | | | | | | | |F4 | |DIFFS |IO_L04N_3/VREF_3 |UNUSED | |3 | | | | | | | | | |F5 | |IBUF |IP |UNUSED | |3 | | | | | | | | | |F6 | | |GND | | | | | | | | | | | | |F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |F8 | |DIFFS |IO_L12N_0 |UNUSED | |0 | | | | | | | | | |F9 | |DIFFS |IO_L08N_0/GCLK5 |UNUSED | |0 | | | | | | | | | |F10 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |F11 | | |GND | | | | | | | | | | | | |F12 |ram_address_rd<7> |IOB |IO_L16N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |F13 |switch_port_in_data<3> |IOB |IO_L16P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |F14 |ram_address_rd<11> |IOB |IO_L15P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |F15 |clkout |IOB |IO_L15N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |F16 | | |VCCAUX | | | | | | | |2.5 | | | | |G1 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | |G2 | |DIFFS |IO_L07N_3 |UNUSED | |3 | | | | | | | | | |G3 | |DIFFM |IO_L07P_3 |UNUSED | |3 | | | | | | | | | |G4 | |DIFFS |IO_L06N_3 |UNUSED | |3 | | | | | | | | | |G5 | |DIFFM |IO_L06P_3 |UNUSED | |3 | | | | | | | | | |G6 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |G7 | | |GND | | | | | | | | | | | | |G8 | | |GND | | | | | | | | | | | | |G9 | | |GND | | | | | | | | | | | | |G10 | | |GND | | | | | | | | | | | | |G11 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |G12 |ram_data_out<3> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |G13 |ram_address_rd<5> |IOB |IO_L14P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |G14 |ram_address_rd<3> |IOB |IO_L14N_1/A0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |G15 |switch_port_in_data<5> |IOB |IO_L13P_1/A2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |G16 |ram_address_rd<15> |IOB |IO_L13N_1/A1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |H1 | |IBUF |IP |UNUSED | |3 | | | | | | | | | |H2 | | |GND | | | | | | | | | | | | |H3 | |DIFFM |IO_L09P_3/LHCLK2 |UNUSED | |3 | | | | | | | | | |H4 | |DIFFS |IO_L09N_3/LHCLK3/IRDY2 |UNUSED | |3 | | | | | | | | | |H5 | |DIFFM |IO_L08P_3/LHCLK0 |UNUSED | |3 | | | | | | | | | |H6 | |DIFFS |IO_L08N_3/LHCLK1 |UNUSED | |3 | | | | | | | | | |H7 | | |GND | | | | | | | | | | | | |H8 | | |GND | | | | | | | | | | | | |H9 | | |GND | | | | | | | | | | | | |H10 | | |GND | | | | | | | | | | | | |H11 |ram_address_rd<13> |IOB |IO_L12N_1/A3/RHCLK7 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |H12 |switch_port_in_data<4> |IOB |IO_L12P_1/A4/RHCLK6 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |H13 |ram_data_out<2> |IBUF |IP/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |H14 |switch_port_in_data<2> |IOB |IO_L11N_1/A5/RHCLK5 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |H15 |ram_address_rd<6> |IOB |IO_L11P_1/A6/RHCLK4/IRDY1|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |H16 |ram_data_out<1> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |J1 | |DIFFM |IO_L12P_3 |UNUSED | |3 | | | | | | | | | |J2 | |DIFFM |IO_L10P_3/LHCLK4/TRDY2 |UNUSED | |3 | | | | | | | | | |J3 | |DIFFS |IO_L10N_3/LHCLK5 |UNUSED | |3 | | | | | | | | | |J4 | |DIFFS |IO_L11N_3/LHCLK7 |UNUSED | |3 | | | | | | | | | |J5 | |DIFFM |IO_L11P_3/LHCLK6 |UNUSED | |3 | | | | | | | | | |J6 | |IBUF |IP |UNUSED | |3 | | | | | | | | | |J7 | | |GND | | | | | | | | | | | | |J8 | | |GND | | | | | | | | | | | | |J9 | | |GND | | | | | | | | | | | | |J10 | | |GND | | | | | | | | | | | | |J11 |instruction_en |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |J12 |ram_data_out<0> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |J13 |ram_address_rd<9> |IOB |IO_L10N_1/A7/RHCLK3/TRDY1|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |J14 |switch_port_in_data<1> |IOB |IO_L10P_1/A8/RHCLK2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |J15 | | |GND | | | | | | | | | | | | |J16 |switch_port_in_data<7> |IOB |IO_L09N_1/A9/RHCLK1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |K1 |hold_req |IOB |IO_L12N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |K2 | |DIFFM |IO_L13P_3 |UNUSED | |3 | | | | | | | | | |K3 | |DIFFS |IO_L13N_3 |UNUSED | |3 | | | | | | | | | |K4 | |IBUF |IP |UNUSED | |3 | | | | | | | | | |K5 | |DIFFM |IO_L15P_3 |UNUSED | |3 | | | | | | | | | |K6 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |K7 | | |GND | | | | | | | | | | | | |K8 | | |GND | | | | | | | | | | | | |K9 | | |GND | | | | | | | | | | | | |K10 | | |GND | | | | | | | | | | | | |K11 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |K12 |switch_port_in_data<0> |IOB |IO_L07N_1/A11 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |K13 |ram_address_rd<2> |IOB |IO_L07P_1/A12 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |K14 |ram_address_rd<4> |IOB |IO_L08N_1/VREF_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |K15 |switch_port_in_wr_en |IOB |IO_L08P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |K16 |switch_port_in_data<6> |IOB |IO_L09P_1/A10/RHCLK0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |L1 | | |VCCAUX | | | | | | | |2.5 | | | | |L2 | |DIFFS |IO_L14N_3/VREF_3 |UNUSED | |3 | | | | | | | | | |L3 | |DIFFM |IO_L14P_3 |UNUSED | |3 | | | | | | | | | |L4 | |DIFFS |IO_L17N_3 |UNUSED | |3 | | | | | | | | | |L5 | |DIFFS |IO_L15N_3 |UNUSED | |3 | | | | | | | | | |L6 | | |GND | | | | | | | | | | | | |L7 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |L8 |ram_address_wr<6> |IOB |IO_L09N_2/D6/GCLK13 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |L9 |ram_address_wr<13> |IOB |IO_L13P_2/M0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |L10 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |L11 | | |GND | | | | | | | | | | | | |L12 |hold_ack |IBUF |IO_L05P_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |L13 |switch_port_in_cmd_en |IOB |IO_L05N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |L14 |ram_address_rd<0> |IOB |IO_L06P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |L15 |ram_address_rd<1> |IOB |IO_L06N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |L16 | | |VCCAUX | | | | | | | |2.5 | | | | |M1 | |DIFFM |IO_L16P_3 |UNUSED | |3 | | | | | | | | | |M2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |M3 |instruction<0> |IBUF |IP |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | |M4 |ram_data_in<0> |IOB |IO_L17P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |M5 | | |VCCINT | | | | | | | |1.2 | | | | |M6 |ram_data_in<6> |IOB |IO_L05P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |M7 |ram_address_wr<0> |IOB |IO |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |M8 |ram_address_wr<5> |IOB |IO_L09P_2/D7/GCLK12 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |M9 |ram_address_wr<14> |IOB |IO_L13N_2/DIN/D0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |M10 |ram_we |IOB |IO_L15N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |M11 |switch_port_out_data<1> |IBUF |IP_L17N_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |M12 | | |VCCINT | | | | | | | |1.2 | | | | |M13 |switch_port_out_data_vailaible|IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |M14 |switch_port_in_empty |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |M15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |M16 |ram_address_rd<8> |IOB |IO_L04N_1/VREF_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |N1 | |DIFFS |IO_L16N_3 |UNUSED | |3 | | | | | | | | | |N2 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | |N3 | |IBUF |IP |UNUSED | |3 | | | | | | | | | |N4 | | |VCCINT | | | | | | | |1.2 | | | | |N5 |ram_data_in<2> |IOB |IO_L03N_2/MOSI/CSI_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |N6 |ram_data_in<7> |IOB |IO_L05N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |N7 |ram_address_wr<3> |IOB |IO_L07P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |N8 |ram_address_wr<8> |IOB |IO_L10P_2/D4/GCLK14 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |N9 |ram_address_wr<11> |IOB |IO_L12N_2/D1/GCLK3 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |N10 |instruction<7> |IBUF |IO_L15P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |N11 |switch_port_out_data<0> |IBUF |IP_L17P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |N12 |switch_port_out_data<3> |IBUF |IO_L18N_2/A20 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |N13 | | |VCCINT | | | | | | | |1.2 | | | | |N14 |PushOut<4> |IOB |IO_L03P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |N15 |switch_port_in_full |IBUF |IO_L03N_1/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | |N16 |switch_port_out_rd_en |IOB |IO_L04P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P1 | |DIFFS |IO_L18N_3 |UNUSED | |3 | | | | | | | | | |P2 | |DIFFM |IO_L18P_3 |UNUSED | |3 | | | | | | | | | |P3 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | | |P4 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | | |P5 |ram_data_in<1> |IOB |IO_L03P_2/DOUT/BUSY |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P6 |ram_address_wr<2> |IOB |IO_L06N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P7 |ram_address_wr<4> |IOB |IO_L07N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P8 |ram_address_wr<9> |IOB |IO_L10N_2/D3/GCLK15 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P9 |ram_address_wr<10> |IOB |IO_L12P_2/D2/GCLK2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P10 |ram_address_wr<15> |IOB |IO_L14P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P11 |PushOut<5> |IOB |IO_L16N_2/A22 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P12 |PushOut<0> |IOB |IO_L18P_2/A21 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P13 |switch_port_out_data<6> |IBUF |IO/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |P14 |PushOut<3> |IOB |IO_L20P_2/VS0/A17 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P15 |instruction_fifo_full |IOB |IO_L02N_1/A13 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |P16 |barrier_completed |IOB |IO_L02P_1/A14 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |R1 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | | |R2 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | | |R3 |instruction<2> |IBUF |IP_L02N_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |R4 |ram_data_in<3> |IOB |IO/VREF_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |R5 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |R6 |ram_address_wr<1> |IOB |IO_L06P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |R7 |instruction<3> |IBUF |IP_L08P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |R8 | | |GND | | | | | | | | | | | | |R9 |instruction<6> |IBUF |IP_L11N_2/M2/GCLK1 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |R10 |ram_en |IOB |IO_L14N_2/VREF_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |R11 |PushOut<1> |IOB |IO_L16P_2/A23 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |R12 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |R13 |switch_port_out_data<5> |IBUF |IO_L19N_2/VS1/A18 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |R14 |switch_port_out_data<2> |IBUF |IO_L20N_2/CCLK |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |R15 |PushOut<2> |IOB |IO_L01N_1/A15 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |R16 |packet_received |IOB |IO_L01P_1/A16 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |T1 | | |GND | | | | | | | | | | | | |T2 | |IBUF |IP |UNUSED | |2 | | | | | | | | | |T3 |instruction<1> |IBUF |IP_L02P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |T4 |ram_data_in<4> |IOB |IO_L04P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |T5 |ram_data_in<5> |IOB |IO_L04N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |T6 | | |VCCAUX | | | | | | | |2.5 | | | | |T7 |instruction<4> |IBUF |IP_L08N_2/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |T8 |ram_address_wr<7> |IOB |IO/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |T9 |instruction<5> |IBUF |IP_L11P_2/RDWR_B/GCLK0 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |T10 |ram_address_wr<12> |IOB |IO/M1 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | |T11 | | |VCCAUX | | | | | | | |2.5 | | | | |T12 |reset |IBUF |IO |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |T13 |switch_port_out_data<7> |IBUF |IO_L19P_2/VS2/A19 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |T14 |switch_port_out_data<4> |IBUF |IP |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | |T15 | | |DONE | | | | | | | | | | | | |T16 | | |GND | | | | | | | | | | | | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Default value. ** This default Pullup/Pulldown value can be overridden in Bitgen. ****** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.