Release 12.3 Map M.70d (nt64) Xilinx Mapping Report File for Design 'MPI_NOC' Design Information ------------------ Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off -c 100 -o MPI_NOC_map.ncd MPI_NOC.ngd MPI_NOC.pcf Target Device : xc3s1200e Target Package : ft256 Target Speed : -5 Mapper Version : spartan3e -- $Revision: 1.52 $ Mapped Date : Fri Aug 03 10:15:46 2012 Design Summary -------------- Number of errors: 0 Number of warnings: 80 Logic Utilization: Total Number Slice Registers: 1,420 out of 17,344 8% Number used as Flip Flops: 883 Number used as Latches: 537 Number of 4 input LUTs: 2,986 out of 17,344 17% Logic Distribution: Number of occupied Slices: 1,832 out of 8,672 21% Number of Slices containing only related logic: 1,832 out of 1,832 100% Number of Slices containing unrelated logic: 0 out of 1,832 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 3,188 out of 17,344 18% Number used as logic: 2,826 Number used as a route-thru: 202 Number used for Dual Port RAMs: 160 (Two LUTs used per Dual Port RAM) The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 146 out of 190 76% Number of RAMB16s: 4 out of 28 14% Number of BUFGMUXs: 5 out of 24 20% Average Fanout of Non-Clock Nets: 3.61 Peak Memory Usage: 289 MB Total REAL time to MAP completion: 10 secs Total CPU time to MAP completion: 5 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Timing Report Section 11 - Configuration String Information Section 12 - Control Set Information Section 13 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/LD_instr/count_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/LD_instr/count_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/LD_instr/timeout_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/dma_data_in_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 00 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 00 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/dma_data_in_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or 0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or 0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/LD_instr/timeout_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Section 3 - Informational ------------------------- INFO:Security:54 - 'xc3s1200e' is a WebPack part. INFO:LIT:243 - Logical network MPI_Node_in<2>_clk has no load. INFO:LIT:395 - The above info message is repeated 95 more times for the following (max. 5 shown): MPI_Node_in<2>_packet_ack, MPI_Node_in<1>_packet_ack, MPI_Node_in<2>_reset, connect_core[2].hardmpi/MyRank<0>, connect_core[2].hardmpi/MyRank<1> To see the details of these info messages, please use the -detail switch. INFO:MapLib:562 - No environment variables are currently set. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Section 4 - Removed Logic Summary --------------------------------- 41 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/XST_GND VCC Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/XST_VCC GND Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/fifo_RAM_256/XST_GND VCC Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/fifo_RAM_256/XST_VCC GND Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/XST_GND VCC Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/XST_VCC GND Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/fifo_RAM_256/XST_GND VCC Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI FO/fifo_RAM_256/XST_VCC GND Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_GND VCC Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_VCC GND Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM _256/XST_GND VCC Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM _256/XST_VCC GND Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/XST_GND VCC Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/XST_VCC GND Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_GND VCC Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_VCC GND Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM _256/XST_GND VCC Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM _256/XST_VCC VCC Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/XST_VCC GND connect_core[1].hardmpi/Instruction_Fifo2/XST_GND GND connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND GND connect_core[1].hardmpi/LD_instr/XST_GND VCC connect_core[1].hardmpi/LD_instr/XST_VCC GND connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/XST_GND GND connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_GND VCC connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_VCC GND connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_GND GND connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_GND VCC connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_VCC GND connect_core[1].hardmpi/XST_GND GND connect_core[2].hardmpi/Instruction_Fifo2/XST_GND GND connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND GND connect_core[2].hardmpi/LD_instr/XST_GND VCC connect_core[2].hardmpi/LD_instr/XST_VCC GND connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/XST_GND GND connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_GND VCC connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_VCC GND connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_GND GND connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_GND VCC connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_VCC GND connect_core[2].hardmpi/XST_GND To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | MPI_Node_Out<1>_PushOut<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_PushOut<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_PushOut<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_PushOut<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_PushOut<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_PushOut<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_PushOut<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_PushOut<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_barrier_completed | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_hold_req | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_instruction_fifo_f | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | ull | | | | | | | | | | | MPI_Node_Out<1>_packet_received | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_rd<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_address_wr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_data_in<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<1>_ram_we | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_PushOut<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_barrier_completed | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_hold_req | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_instruction_fifo_f | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | ull | | | | | | | | | | | MPI_Node_Out<2>_packet_received | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_rd<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_address_wr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_data_in<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_Out<2>_ram_we | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | MPI_Node_in<1>_clk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_hold_ack | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_instruction_en | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_ram_data_out<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<1>_reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_hold_ack | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_instruction_en | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | MPI_Node_in<2>_ram_data_out<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Timing Report -------------------------- This design was not run using timing mode. Section 11 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 12 - Control Set Information ------------------------------------ No control set information for this architecture. Section 13 - Utilization by Hierarchy ------------------------------------- Use the "-detail" map option to print out the Utilization by Hierarchy section.