MPICORETEST Project Status (08/03/2012 - 19:01:09) | |||
Project File: | MPI_CORE_COMPONENTS.xise | Parser Errors: | No Errors |
Module Name: | MPI_NOC | Implementation State: | Synthesized (Stopped) |
Target Device: | xc6slx100t-3fgg484 |
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Product Version: | ISE 12.3 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Total Number Slice Registers | 1,420 | 17,344 | 8% | ||
Number used as Flip Flops | 883 | ||||
Number used as Latches | 537 | ||||
Number of 4 input LUTs | 2,986 | 17,344 | 17% | ||
Number of occupied Slices | 1,832 | 8,672 | 21% | ||
Number of Slices containing only related logic | 1,832 | 1,832 | 100% | ||
Number of Slices containing unrelated logic | 0 | 1,832 | 0% | ||
Total Number of 4 input LUTs | 3,188 | 17,344 | 18% | ||
Number used as logic | 2,826 | ||||
Number used as a route-thru | 202 | ||||
Number used for Dual Port RAMs | 160 | ||||
Number of bonded IOBs | 146 | 190 | 76% | ||
Number of RAMB16s | 4 | 28 | 14% | ||
Number of BUFGMUXs | 5 | 24 | 20% | ||
Average Fanout of Non-Clock Nets | 3.61 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fri 3. Aug 10:15:28 2012 | ||||
Translation Report | Current | Fri 3. Aug 10:15:38 2012 | ||||
Map Report | Current | Fri 3. Aug 10:15:57 2012 | ||||
Place and Route Report | Current | Fri 3. Aug 10:17:02 2012 | ||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | Current | Fri 3. Aug 10:17:12 2012 | ||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |