Release 12.3 par M.70d (nt64) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. GAMOM-PC:: Tue Aug 14 16:11:11 2012 par -w -intstyle ise -ol high -mt off MultiMPITest_map.ncd MultiMPITest.ncd MultiMPITest.pcf Constraints file: MultiMPITest.pcf. Loading device for application Rf_Device from file '6slx100.nph' in environment d:\Xilinx\12.3\ISE_DS\ISE\. "MultiMPITest" is an NCD, version 3.2, device xc6slx100, package fgg484, speed -3 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.12c 2010-09-15". Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 1,515 out of 126,576 1% Number used as Flip Flops: 1,137 Number used as Latches: 378 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 3,025 out of 63,288 4% Number used as logic: 2,942 out of 63,288 4% Number using O6 output only: 2,058 Number using O5 output only: 294 Number using O5 and O6: 590 Number used as ROM: 0 Number used as Memory: 48 out of 15,616 1% Number used as Dual Port RAM: 48 Number using O6 output only: 48 Number using O5 output only: 0 Number using O5 and O6: 0 Number used as Single Port RAM: 0 Number used as Shift Register: 0 Number used exclusively as route-thrus: 35 Number with same-slice register load: 7 Number with same-slice carry load: 28 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 1,099 out of 15,822 6% Number of LUT Flip Flop pairs used: 3,230 Number with an unused Flip Flop: 1,806 out of 3,230 55% Number with an unused LUT: 205 out of 3,230 6% Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% Number of slice register sites lost to control set restrictions: 0 out of 126,576 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 10 out of 326 3% Specific Feature Utilization: Number of RAMB16BWERs: 64 out of 268 23% Number of RAMB8BWERs: 4 out of 536 1% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFG/BUFGMUXs: 3 out of 16 18% Number used as BUFGs: 3 Number used as BUFGMUX: 0 Number of DCM/DCM_CLKGENs: 0 out of 12 0% Number of ILOGIC2/ISERDES2s: 0 out of 506 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% Number of OLOGIC2/OSERDES2s: 0 out of 506 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 384 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 180 0% Number of ICAPs: 0 out of 1 0% Number of MCBs: 0 out of 4 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 6 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 9 secs WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. Starting Router Phase 1 : 19877 unrouted; REAL time: 11 secs Phase 2 : 17702 unrouted; REAL time: 14 secs Phase 3 : 7443 unrouted; REAL time: 23 secs Phase 4 : 7448 unrouted; (Par is working to improve performance) REAL time: 27 secs Updating file: MultiMPITest.ncd with current fully routed design. Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 36 secs Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 37 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 38 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 39 secs Total REAL time to Router completion: 39 secs Total CPU time to Router completion: 40 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode. Timing Score: 293 (Setup: 293, Hold: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net clk | SETUP | N/A| 9.399ns| N/A| 0 m_BUFGP | HOLD | 0.278ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.579ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.905ns| | 0| 0 nst[2]_PWR_99_o_Mux_295_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.211ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.898ns| | 0| 0 nst[2]_PWR_99_o_Mux_295_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.058ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.867ns| | 0| 0 nst[2]_PWR_72_o_Mux_259_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.073ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.922ns| | 0| 0 nst[2]_PWR_72_o_Mux_259_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.673ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.867ns| | 0| 0 nst[2]_PWR_93_o_Mux_287_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.262ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 1.054ns| | 0| 0 nst[2]_PWR_93_o_Mux_287_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.275ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.016ns| | 0| 0 nst[2]_PWR_105_o_Mux_303_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.214ns| N/A| 43 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 1.038ns| | 0| 0 nst[2]_PWR_105_o_Mux_303_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 1.947ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.729ns| | 0| 0 nst[2]_PWR_66_o_Mux_251_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.486ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.935ns| | 0| 0 nst[2]_PWR_66_o_Mux_251_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.797ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.148ns| | 0| 0 nst[2]_PWR_90_o_Mux_283_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.023ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.942ns| | 0| 0 nst[2]_PWR_90_o_Mux_283_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.265ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.052ns| | 0| 0 nst[2]_PWR_102_o_Mux_299_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.074ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.880ns| | 0| 0 nst[2]_PWR_102_o_Mux_299_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 1.444ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.642ns| | 0| 0 nst[2]_PWR_69_o_Mux_255_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 1.455ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.476ns| | 0| 0 nst[2]_PWR_69_o_Mux_255_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.460ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.135ns| | 0| 0 nst[2]_PWR_84_o_Mux_275_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.483ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 1.163ns| | 0| 0 nst[2]_PWR_84_o_Mux_275_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.207ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.957ns| | 0| 0 nst[2]_PWR_81_o_Mux_271_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.721ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.990ns| | 0| 0 nst[2]_PWR_81_o_Mux_271_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.040ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.837ns| | 0| 0 nst[2]_PWR_60_o_Mux_243_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.187ns| N/A| 168 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.864ns| | 0| 0 nst[2]_PWR_60_o_Mux_243_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.524ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.072ns| | 0| 0 nst[2]_PWR_87_o_Mux_279_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.433ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.593ns| | 0| 0 nst[2]_PWR_87_o_Mux_279_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.022ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.741ns| | 0| 0 nst[2]_PWR_78_o_Mux_267_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.893ns| N/A| 7 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.009ns| | 0| 0 nst[2]_PWR_96_o_Mux_291_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.247ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.704ns| | 0| 0 nst[2]_PWR_96_o_Mux_291_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 1.914ns| N/A| 0 /connect_core[1].hardmpi/MPI_CORE_EX4_FSM | HOLD | 0.530ns| | 0| 0 /stInit2_FSM_FFd1_BUFG | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.130ns| N/A| 0 /connect_core[2].hardmpi/MPI_CORE_EX4_FSM | HOLD | 0.545ns| | 0| 0 /stInit2_FSM_FFd1_BUFG | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.453ns| N/A| 0 /connect_core[1].hardmpi/MPI_CORE_EX4_FSM | HOLD | 0.979ns| | 0| 0 /stInit2[3]_PWR_316_o_Mux_111_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.866ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.402ns| | 0| 0 nst[2]_PWR_140_o_Mux_371_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.958ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.476ns| | 0| 0 nst[2]_PWR_140_o_Mux_371_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.531ns| N/A| 0 /connect_core[2].hardmpi/MPI_CORE_EX4_FSM | HOLD | 1.012ns| | 0| 0 /stInit2[3]_PWR_316_o_Mux_111_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.200ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.964ns| | 0| 0 nst[2]_PWR_75_o_Mux_263_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.188ns| N/A| 0 /connect_core[2].hardmpi/LD_instr/etloadi | HOLD | 0.963ns| | 0| 0 nst[2]_PWR_63_o_Mux_247_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.692ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.199ns| | 0| 0 nst[2]_PWR_63_o_Mux_247_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.413ns| N/A| 0 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 1.076ns| | 0| 0 nst[2]_PWR_75_o_Mux_263_o | | | | | ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uut | SETUP | N/A| 2.116ns| N/A| 75 /connect_core[1].hardmpi/LD_instr/etloadi | HOLD | 0.940ns| | 0| 0 nst[2]_PWR_78_o_Mux_267_o | | | | | ---------------------------------------------------------------------------------------------------------- 4 constraints not met. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 41 secs Total CPU time to PAR completion: 41 secs Peak Memory Usage: 570 MB Placer: Placement generated during map. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 10 Number of info messages: 2 Writing design to file MultiMPITest.ncd PAR done!