]> Release 12.3 Trace (nt64)Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml CORE_MPI.twx CORE_MPI.ncd -o CORE_MPI.twr CORE_MPI.pcf CORE_MPI.ncdCORE_MPI.ncdCORE_MPI.pcfCORE_MPI.pcfxc3s1200e-5PRODUCTION 1.27 2010-09-153INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.clkhold_ack3.319-0.085instruction_en5.2770.181ram_data_out<0>1.1880.201ram_data_out<1>0.5040.749ram_data_out<2>1.538-0.084ram_data_out<3>0.3560.861ram_data_out<4>1.0840.270ram_data_out<5>1.2820.112ram_data_out<6>2.652-0.981ram_data_out<7>2.074-0.520reset6.6751.317switch_port_in_empty0.1411.366switch_port_in_full7.5050.772switch_port_out_data<0>3.6711.216switch_port_out_data<1>3.5251.240switch_port_out_data<2>4.0591.054switch_port_out_data<3>3.4531.025switch_port_out_data<4>5.1840.556switch_port_out_data<5>6.0640.826switch_port_out_data<6>5.3641.212switch_port_out_data<7>5.5690.858switch_port_out_data_vailaible5.0671.541clkclkclk7.585clkclkout6.836ram_data_out<0>switch_port_in_data<0>6.903ram_data_out<1>switch_port_in_data<1>7.039ram_data_out<2>switch_port_in_data<2>6.694ram_data_out<3>switch_port_in_data<3>7.561ram_data_out<4>switch_port_in_data<4>8.919ram_data_out<5>switch_port_in_data<5>9.958ram_data_out<6>switch_port_in_data<6>10.951ram_data_out<7>switch_port_in_data<7>9.270switch_port_in_fullswitch_port_in_wr_en9.334Fri Aug 03 10:51:04 2012 TraceTrace Settings Peak Memory Usage: 203 MB