Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

Tue Aug 14 16:11:52 2012

All signals are completely routed.

WARNING:ParHelpers:361 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

   uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O
   uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O
   uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O
   uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O
   uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O
   uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O
   uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O
   uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O