Release 12.3 - xst M.70d (nt64) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.09 secs --> Reading design: RAM_v.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "RAM_v.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "RAM_v" Output Format : NGC Target Device : xc6slx100-3-fgg484 ---- Source Options Top Module Name : RAM_v Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : Soft Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "\Core MPI\CORE_MPI\../SWITCH_GENERIC_16_16/CoreTypes.vhd" into library NocLib Parsing package . Parsing package body . Parsing VHDL file "\Core MPI\CORE_MPI\RAM_32_32.vhd" into library work Parsing entity . Parsing architecture of entity . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating entity (architecture ) with generics from library . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "/core mpi/core_mpi/ram_32_32.vhd". width = 32 Size = 16 Found 65536x32-bit dual-port RAM for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Summary: inferred 1 RAM(s). inferred 66 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 1 65536x32-bit dual-port RAM : 1 # Registers : 4 1-bit register : 2 32-bit register : 2 # Multiplexers : 1 32-bit 2-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Synthesizing (advanced) Unit . INFO:Xst:3031 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 65536-word x 32-bit | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 65536-word x 32-bit | | | addrB | connected to signal | | | doB | connected to internal node | | ----------------------------------------------------------------------- Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # RAMs : 1 65536x32-bit dual-port distributed RAM : 1 # Registers : 66 Flip-Flops : 66 # Multiplexers : 1 32-bit 2-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block RAM_v, actual ratio is 52. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 66 Flip-Flops : 66 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : RAM_v.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 12007 # GND : 1 # LUT2 : 4 # LUT3 : 34 # LUT4 : 32 # LUT6 : 11936 # FlipFlops/Latches : 66 # FDE : 64 # FDR : 2 # RAMS : 12288 # RAM64M : 10240 # RAM64X1D : 2048 # Clock Buffers : 2 # BUFGP : 2 # IO Buffers : 99 # IBUF : 67 # OBUF : 32 Device utilization summary: --------------------------- Selected Device : 6slx100fgg484-3 Slice Logic Utilization: Number of Slice Registers: 66 out of 126576 0% Number of Slice LUTs: 57062 out of 63288 90% Number used as Logic: 12006 out of 63288 18% Number used as Memory: 45056 out of 15616 288% (*) Number used as RAM: 45056 Slice Logic Distribution: Number of LUT Flip Flop pairs used: 57062 Number with an unused Flip Flop: 56996 out of 57062 99% Number with an unused LUT: 0 out of 57062 0% Number of fully used LUT-FF pairs: 66 out of 57062 0% Number of unique control sets: 4 IO Utilization: Number of IOs: 101 Number of bonded IOBs: 101 out of 326 30% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 2 out of 16 12% WARNING:Xst:1336 - (*) More than 100% of Device resources are used --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clka | BUFGP | 12321 | clkb | BUFGP | 33 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -3 Minimum period: 6.754ns (Maximum Frequency: 148.055MHz) Minimum input arrival time before clock: 16.914ns Maximum output required time after clock: 5.602ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clka' Clock period: 6.754ns (frequency: 148.055MHz) Total number of paths / destination ports: 32769 / 33 ------------------------------------------------------------------------- Delay: 6.754ns (Levels of Logic = 5) Source: Mram_RAM427 (RAM) Destination: doa_1 (FF) Source Clock: clka rising Destination Clock: clka rising Data Path: Mram_RAM427 to doa_1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAM64M:WCLK->DOB 1 1.131 0.856 Mram_RAM427 (N3586) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_2229 (inst_LPM_MUX1_2229) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_178 (inst_LPM_MUX1_178) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_122 (inst_LPM_MUX1_122) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_7 (inst_LPM_MUX1_7) LUT6:I2->O 2 0.254 0.000 addrb<15>110 (_n0028<1>) FDE:D 0.074 doa_1 ---------------------------------------- Total 6.754ns (2.475ns logic, 4.279ns route) (36.6% logic, 63.4% route) ========================================================================= Timing constraint: Default period analysis for Clock 'clkb' Clock period: 2.278ns (frequency: 439.057MHz) Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Delay: 2.278ns (Levels of Logic = 1) Source: Lrb (FF) Destination: Lrb (FF) Source Clock: clkb rising Destination Clock: clkb rising Data Path: Lrb to Lrb Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 34 0.525 1.429 Lrb (Lrb) LUT2:I0->O 1 0.250 0.000 Lrb_glue_set (Lrb_glue_set) FDR:D 0.074 Lrb ---------------------------------------- Total 2.278ns (0.849ns logic, 1.429ns route) (37.3% logic, 62.7% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clka' Total number of paths / destination ports: 300386 / 131138 ------------------------------------------------------------------------- Offset: 16.914ns (Levels of Logic = 7) Source: addrb<5> (PAD) Destination: doa_30 (FF) Destination Clock: clka rising Data Path: addrb<5> to doa_30 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 32768 1.228 9.827 addrb_5_IBUF (addrb_5_IBUF) RAM64X1D:DPRA5->DPO 1 0.235 0.856 Mram_RAM106671 (N64172) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_2229 (inst_LPM_MUX30_2229) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_178 (inst_LPM_MUX30_178) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_122 (inst_LPM_MUX30_122) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_7 (inst_LPM_MUX30_7) LUT6:I2->O 2 0.254 0.000 addrb<15>301 (_n0028<30>) FDE:D 0.074 doa_30 ---------------------------------------- Total 16.914ns (2.807ns logic, 14.107ns route) (16.6% logic, 83.4% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clkb' Total number of paths / destination ports: 34146 / 66 ------------------------------------------------------------------------- Offset: 16.914ns (Levels of Logic = 7) Source: addrb<5> (PAD) Destination: dout_30 (FF) Destination Clock: clkb rising Data Path: addrb<5> to dout_30 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 32768 1.228 9.827 addrb_5_IBUF (addrb_5_IBUF) RAM64X1D:DPRA5->DPO 1 0.235 0.856 Mram_RAM106671 (N64172) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_2229 (inst_LPM_MUX30_2229) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_178 (inst_LPM_MUX30_178) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_122 (inst_LPM_MUX30_122) LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_7 (inst_LPM_MUX30_7) LUT6:I2->O 2 0.254 0.000 addrb<15>301 (_n0028<30>) FDE:D 0.074 dout_30 ---------------------------------------- Total 16.914ns (2.807ns logic, 14.107ns route) (16.6% logic, 83.4% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clkb' Total number of paths / destination ports: 64 / 32 ------------------------------------------------------------------------- Offset: 5.602ns (Levels of Logic = 2) Source: Lrb (FF) Destination: dob<31> (PAD) Source Clock: clkb rising Data Path: Lrb to dob<31> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 34 0.525 1.549 Lrb (Lrb) LUT4:I1->O 1 0.235 0.579 Mmux_dob321 (dob_9_OBUF) OBUF:I->O 2.715 dob_9_OBUF (dob<9>) ---------------------------------------- Total 5.602ns (3.475ns logic, 2.127ns route) (62.0% logic, 38.0% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clka' Total number of paths / destination ports: 64 / 32 ------------------------------------------------------------------------- Offset: 5.497ns (Levels of Logic = 2) Source: Lra (FF) Destination: dob<31> (PAD) Source Clock: clka rising Data Path: Lra to dob<31> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 34 0.525 1.429 Lra (Lra) LUT4:I2->O 1 0.250 0.579 Mmux_dob321 (dob_9_OBUF) OBUF:I->O 2.715 dob_9_OBUF (dob<9>) ---------------------------------------- Total 5.497ns (3.490ns logic, 2.007ns route) (63.5% logic, 36.5% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock clka ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clka | 6.754| | | | clkb | 3.241| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clkb ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clka | 6.754| | | | clkb | 2.278| | | | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 587.00 secs Total CPU time to Xst completion: 587.28 secs --> Total memory usage is 1227976 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 1 ( 0 filtered)