#-----------------------------------------------------------
# PlanAhead v12.3
# Build 101344 by hdbuild on Sat Sep  4 00:26:34 MDT 2010
# Start of session at: Fri Aug 17 14:11:50 2012
# Process ID: 17924
# Log file: C:/Core MPI/CORE_MPI/planAhead_run_1/planAhead.log
# Journal file: C:/Core MPI/CORE_MPI/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead
INFO: [HD-Licensing 1] Got a license: PlanAhead
INFO: [HD-Licensing 3] Your PlanAhead license expires in -291 day(s)
INFO: [HD-ArchReader 0] Loading parts and site information from D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\arch.xml
INFO: [HD-RTPRIM 0] Parsing RTL primitives file 'D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file 'D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
start_gui -source {C:/Core MPI/CORE_MPI/pa.fromHdl.tcl}
# create_project -name MPI_CORE_COMPONENTS -dir "C:/Core MPI/CORE_MPI/planAhead_run_1" -part xc6slx100fgg484-3
# set_param project.pinAheadLayout yes
# set srcset [get_property srcset [current_run -impl]]
# set_property top MultiMPITest $srcset
# set_param project.paUcfFile  "MultiMPITest.ucf"
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/CoreTypes.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/RAM_256.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Arbiter.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbit.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {round_robbin_machine.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {RAM_64.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Packet_type.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {MUX8.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {MUX1.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {DEMUX1.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Scheduler.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbar.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {MPI_CORE_SCHEDULER.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {load_instr.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {FIFO_64_FWFT.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {EX4_FSM.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {EX3_FSM.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {EX2_FSM.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {EX1_FSM.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Ex0_Fsm.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {DMA_ARBITER.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library NocLib $hdlfile
# set hdlfile [add_files [list {RAM_32_32.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {CORE_MPI.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {PE.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {MPI_NOC.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {MultiMPITest.vhd}]]
# set_property file_type VHDL $hdlfile
# set_property library work $hdlfile
# add_files "MultiMPITest.ucf" -fileset [get_property constrset [current_run]]
# add_files -norecurse { {C:/Core MPI/CORE_MPI} }
# open_rtl_design -part xc6slx100fgg484-3
INFO: [HD-RTLIN 2] Parsing VHDL file "D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
INFO: [HD-RTLIN 2] Parsing package <attributes>.
INFO: [HD-RTLIN 2] Parsing VHDL file "D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
INFO: [HD-RTLIN 2] Parsing package <attributes>.
INFO: [HD-RTLIN 2] Parsing Verilog file "C:\Core MPI\CORE_MPI\Ex0_FSM.v" into library work
INFO: [HD-RTLIN 2] Parsing module <Ex0_FSM>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing package <CoreTypes>.
INFO: [HD-RTLIN 2] Parsing package body <CoreTypes>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\RAM_256.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <RAM_256>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_256>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Arbiter.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <Arbiter>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <arbiter>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\FIFO_256_FWFT.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <FIFO_256_FWFT>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <fifo_256_fwft>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbit.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <Crossbit>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <crossbit>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\round_robbin_machine.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <round_robbin_machine>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <round_robbin_machine>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_64.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <RAM_64>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_64>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Packet_type.vhd" into library work
INFO: [HD-RTLIN 2] Parsing package <Packet_type>.
INFO: [HD-RTLIN 2] Parsing package body <Packet_type>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MUX8.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <MUX8>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mux8>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MUX1.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <MUX1>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mux1>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\DEMUX1.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <DEMUX1>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <demux1>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Scheduler.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <Scheduler>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <scheduler>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\OUTPUT_PORT_MODULE.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <OUTPUT_PORT_MODULE>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral_description> of entity <output_port_module>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <INPUT_PORT_MODULE>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <input_port_module>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <Crossbar>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <crossbar>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_CORE_SCHEDULER.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <MPI_CORE_SCHEDULER>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mpi_core_scheduler>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\load_instr.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <load_instr>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <load_instr>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <FIFO_64_FWFT>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <fifo_64_fwft>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX4_FSM.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <EX4_FSM>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex4_fsm>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX3_FSM.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <EX3_FSM>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex3_fsm>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX2_FSM.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <EX2_FSM>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex2_fsm>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX1_FSM.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <EX1_FSM>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex1_fsm>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Ex0_Fsm.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <Ex0_Fsm>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex0_fsm>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <DMA_ARBITER>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <dma_arbiter>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.vhd" into library NocLib
INFO: [HD-RTLIN 2] Parsing entity <SWITCH_GEN>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <switch_gen>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_32_32.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <RAM_v>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_v>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\CORE_MPI.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <CORE_MPI>.
INFO: [HD-RTLIN 2] Parsing architecture <Structural> of entity <core_mpi>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\PE.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <PE>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <pe>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_NOC.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <MPI_NOC>.
INFO: [HD-RTLIN 2] Parsing architecture <structural> of entity <mpi_noc>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MultiMPITest.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <MultiMPITest>.
INFO: [HD-RTLIN 2] Parsing architecture <behavior> of entity <multimpitest>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_MUX.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <RAM_MUX>.
INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_mux>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Processing_node.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <PROCESSING_ELEMENT>.
ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(43) Syntax error near "downto".
ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(53) Syntax error near ")".
ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(62) Syntax error near "type".
ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(66) <typ_mae> is not declared.
ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(70) Syntax error near "BEGIN".
ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(81) Syntax error near "begin".
INFO: [HD-RTLIN 2] VHDL file C:\Core MPI\CORE_MPI\Processing_node.vhd ignored due to errors
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_RMA.vhd" into library work
INFO: [HD-RTLIN 2] Parsing package <Mpi_Rma>.
INFO: [HD-RTLIN 2] Parsing package body <MPI_Rma>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_PKG.vhd" into library work
INFO: [HD-RTLIN 2] Parsing package <mpi_pkg>.
INFO: [HD-RTLIN 2] Parsing package body <MPI_PKG>.
INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPICORETEST.vhd" into library work
INFO: [HD-RTLIN 2] Parsing entity <MPICORETEST>.
INFO: [HD-RTLIN 2] Parsing architecture <behavior> of entity <mpicoretest>.
ERROR: Unable to process your HDL design.  Please review Elaboration Messages. 
exit
INFO: [HD-Application 0] Exiting PlanAhead...
INFO: [HD-Licensing 2] Releasing license: PlanAhead