-- VHDL Instantiation Created from source file MUX1.vhd -- 12:17:39 06/13/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT MUX1
	PORT(
		di1 : IN std_logic;
		di2 : IN std_logic;
		sel : IN std_logic;          
		do : OUT std_logic
		);
	END COMPONENT;

	Inst_MUX1: MUX1 PORT MAP(
		di1 => ,
		di2 => ,
		do => ,
		sel => 
	);