Release 11.1 - xst L.33 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.18 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.18 secs --> Reading design: INPUT_PORT_MODULE.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "INPUT_PORT_MODULE.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "INPUT_PORT_MODULE" Output Format : NGC Target Device : xc3s1200e-4-fg320 ---- Source Options Top Module Name : INPUT_PORT_MODULE Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Library Search Order : INPUT_PORT_MODULE.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd" in Library work. Architecture behavioral of Entity ram_256 is up to date. Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd" in Library work. Architecture behavioral of Entity fifo_256_fwft is up to date. Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ) with generics. number_of_ports = 4 Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing generic Entity in library (Architecture ). number_of_ports = 4 Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd". Found 256x8-bit dual-port RAM for signal . Found 8-bit register for signal . Summary: inferred 1 RAM(s). inferred 8 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | srst (positive) | | Reset type | synchronous | | Reset State | state0 | | Power Up State | state0 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal . Found 8-bit updown counter for signal . Found 8-bit up counter for signal . Found 8-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 Counter(s). inferred 8 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 9 | | Inputs | 4 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | reset_signal (positive) | | Reset type | synchronous | | Reset State | state0 | | Power Up State | state0 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal . Found 8-bit subtractor for signal created at line 434. Found 1-bit register for signal . Found 8-bit register for signal . Found 5-bit comparator greater for signal created at line 110. Found 4-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 21 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Comparator(s). Unit synthesized. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 1 256x8-bit dual-port RAM : 1 # Adders/Subtractors : 1 8-bit subtractor : 1 # Counters : 3 8-bit up counter : 2 8-bit updown counter : 1 # Registers : 6 1-bit register : 1 4-bit register : 1 8-bit register : 4 # Comparators : 1 5-bit comparator greater : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Choose code 2 with characteristics nb_luts=8,nb_literals=21,nb_ffs=2,depth=2 ... Optimizing FSM on signal with gray encoding. -------------------- State | Encoding -------------------- state0 | 00 state1 | 01 state2 | 11 state3 | 10 -------------------- Analyzing FSM for best encoding. Choose code 7 with characteristics nb_luts=5,nb_literals=16,nb_ffs=2,depth=2 ... Optimizing FSM on signal with user encoding. -------------------- State | Encoding -------------------- state0 | 00 state1 | 01 state2 | 10 -------------------- Synthesizing (advanced) Unit . INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 256-word x 8-bit | | | mode | read-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 256-word x 8-bit | | | mode | write-first | | | clkB | connected to signal | rise | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 2 # RAMs : 1 256x8-bit dual-port block RAM : 1 # Adders/Subtractors : 1 8-bit subtractor : 1 # Counters : 3 8-bit up counter : 2 8-bit updown counter : 1 # Registers : 29 Flip-Flops : 29 # Comparators : 1 5-bit comparator greater : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block INPUT_PORT_MODULE, actual ratio is 0. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 57 Flip-Flops : 57 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : INPUT_PORT_MODULE.ngr Top Level Output File Name : INPUT_PORT_MODULE Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 31 Cell Usage : # BELS : 142 # GND : 1 # INV : 2 # LUT1 : 14 # LUT2 : 4 # LUT3 : 20 # LUT3_D : 1 # LUT3_L : 2 # LUT4 : 44 # LUT4_D : 5 # LUT4_L : 2 # MUXCY : 21 # MUXF5 : 1 # VCC : 1 # XORCY : 24 # FlipFlops/Latches : 57 # FDE : 8 # FDR : 3 # FDRE : 37 # FDRS : 9 # RAMS : 1 # RAMB16_S9_S9 : 1 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 30 # IBUF : 14 # OBUF : 16 ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s1200efg320-4 Number of Slices: 49 out of 8672 0% Number of Slice Flip Flops: 57 out of 17344 0% Number of 4 input LUTs: 94 out of 17344 0% Number of IOs: 31 Number of bonded IOBs: 31 out of 250 12% Number of BRAMs: 1 out of 28 3% Number of GCLKs: 1 out of 24 4% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 58 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: 7.226ns (Maximum Frequency: 138.389MHz) Minimum input arrival time before clock: 9.258ns Maximum output required time after clock: 7.556ns Maximum combinational path delay: 8.635ns Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 7.226ns (frequency: 138.389MHz) Total number of paths / destination ports: 1824 / 119 ------------------------------------------------------------------------- Delay: 7.226ns (Levels of Logic = 11) Source: pop_state_FSM_FFd1 (FF) Destination: INPUT_PORT_FIFO/fifo_counter_7 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: pop_state_FSM_FFd1 to INPUT_PORT_FIFO/fifo_counter_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 18 0.591 1.103 pop_state_FSM_FFd1 (pop_state_FSM_FFd1) LUT4_D:I2->O 1 0.704 0.455 INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14) LUT3:I2->O 14 0.704 1.035 INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal) LUT3:I2->O 1 0.704 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>) MUXCY:S->O 1 0.464 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>) MUXCY:CI->O 0 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>) XORCY:CI->O 1 0.804 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>) FDRE:D 0.308 INPUT_PORT_FIFO/fifo_counter_7 ---------------------------------------- Total 7.226ns (4.633ns logic, 2.593ns route) (64.1% logic, 35.9% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 528 / 134 ------------------------------------------------------------------------- Offset: 9.258ns (Levels of Logic = 13) Source: grant<1> (PAD) Destination: INPUT_PORT_FIFO/fifo_counter_7 (FF) Destination Clock: clk rising Data Path: grant<1> to INPUT_PORT_FIFO/fifo_counter_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 1.218 0.595 grant_1_IBUF (grant_1_IBUF) LUT4:I0->O 16 0.704 1.209 port_granted1 (port_granted) LUT4_D:I0->O 1 0.704 0.455 INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14) LUT3:I2->O 14 0.704 1.035 INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal) LUT3:I2->O 1 0.704 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>) MUXCY:S->O 1 0.464 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>) MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>) MUXCY:CI->O 0 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>) XORCY:CI->O 1 0.804 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>) FDRE:D 0.308 INPUT_PORT_FIFO/fifo_counter_7 ---------------------------------------- Total 9.258ns (5.964ns logic, 3.294ns route) (64.4% logic, 35.6% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 53 / 16 ------------------------------------------------------------------------- Offset: 7.556ns (Levels of Logic = 3) Source: pop_state_FSM_FFd1 (FF) Destination: request<4> (PAD) Source Clock: clk rising Data Path: pop_state_FSM_FFd1 to request<4> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 18 0.591 1.243 pop_state_FSM_FFd1 (pop_state_FSM_FFd1) LUT4:I0->O 4 0.704 0.622 request_decoder_and00001 (request_decoder_and0000) LUT3:I2->O 1 0.704 0.420 request_decoder<4>1 (request_4_OBUF) OBUF:I->O 3.272 request_4_OBUF (request<4>) ---------------------------------------- Total 7.556ns (5.271ns logic, 2.285ns route) (69.8% logic, 30.2% route) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 8 / 2 ------------------------------------------------------------------------- Delay: 8.635ns (Levels of Logic = 4) Source: grant<1> (PAD) Destination: data_out_pulse (PAD) Data Path: grant<1> to data_out_pulse Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 1.218 0.595 grant_1_IBUF (grant_1_IBUF) LUT4:I0->O 16 0.704 1.209 port_granted1 (port_granted) LUT4:I0->O 11 0.704 0.933 data_out_pulse1 (data_out_pulse_OBUF) OBUF:I->O 3.272 data_out_pulse_OBUF (data_out_pulse) ---------------------------------------- Total 8.635ns (5.898ns logic, 2.737ns route) (68.3% logic, 31.7% route) ========================================================================= Total REAL time to Xst completion: 10.00 secs Total CPU time to Xst completion: 9.84 secs --> Total memory usage is 137348 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 2 ( 0 filtered)