-- VHDL Instantiation Created from source file Scheduler4_4.vhd -- 13:38:35 06/19/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT Scheduler4_4
	PORT(
		Request : IN std_logic_vector(16 downto 1);
		Fifo_full : IN std_logic_vector(4 downto 1);
		clk : IN std_logic;
		reset : IN std_logic;
		priority_rotation : IN std_logic_vector(4 downto 1);          
		port_grant : OUT std_logic_vector(16 downto 1)
		);
	END COMPONENT;

	Inst_Scheduler4_4: Scheduler4_4 PORT MAP(
		Request => ,
		Fifo_full => ,
		clk => ,
		reset => ,
		priority_rotation => ,
		port_grant => 
	);