-- VHDL Instantiation Created from source file DMA_ARBITER.vhd -- 05:54:04 06/21/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT DMA_ARBITER
	PORT(
		dma_rd_request : IN std_logic;
		data_wr_in : IN std_logic_vector(7 downto 0);
		data_rd_in : IN std_logic_vector(7 downto 0);
		address_rd : IN std_logic_vector(15 downto 0);
		address_wr : IN std_logic_vector(15 downto 0);
		clk : IN std_logic;
		reset : IN std_logic;
		dma_wr_request : IN std_logic;          
		address_out : OUT std_logic_vector(15 downto 0);
		ram_en : OUT std_logic;
		ram_we : OUT std_logic;
		data_wr_out : OUT std_logic_vector(7 downto 0);
		data_rd_out : OUT std_logic_vector(7 downto 0);
		dma_wr_grant : OUT std_logic;
		dma_rd_grant : OUT std_logic
		);
	END COMPONENT;

	Inst_DMA_ARBITER: DMA_ARBITER PORT MAP(
		dma_rd_request => ,
		data_wr_in => ,
		data_rd_in => ,
		address_rd => ,
		address_wr => ,
		address_out => ,
		ram_en => ,
		ram_we => ,
		data_wr_out => ,
		data_rd_out => ,
		dma_wr_grant => ,
		clk => ,
		reset => ,
		dma_rd_grant => ,
		dma_wr_request => 
	);