-- VHDL Instantiation Created from source file EX3_FSM.vhd -- 05:56:26 06/21/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT EX3_FSM
	PORT(
		instruction : IN std_logic_vector(7 downto 0);
		clk : IN std_logic;
		reset : IN std_logic;          
		pid_nprocs : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	Inst_EX3_FSM: EX3_FSM PORT MAP(
		instruction => ,
		pid_nprocs => ,
		clk => ,
		reset => 
	);