reset reset ram_we ram_we ram_ena ram_ena ram_enb ram_enb ramsel ramsel pe_instr_en pe_instr_en pe_ram_we pe_ram_we pe_ram_ena pe_ram_ena pe_ram_enb pe_ram_enb clkm clkm etputget etputget ram_din[7:0] ram_din[7:0] HEXRADIX ram_addra[15:0] ram_addra[15:0] HEXRADIX ram_addrb[15:0] ram_addrb[15:0] HEXRADIX ram_do[7:0] ram_do[7:0] HEXRADIX pe_ram_do[7:0] pe_ram_do[7:0] HEXRADIX pe_ram_din[7:0] pe_ram_din[7:0] HEXRADIX pe_ram_addra[15:0] pe_ram_addra[15:0] HEXRADIX pe_ram_addrb[15:0] pe_ram_addrb[15:0] HEXRADIX etloadinst etloadinst ilatch ilatch iack iack fifo_wr fifo_wr fifo_din[7:0] fifo_din[7:0] HEXRADIX pe_hold_ack pe_hold_ack pe_hold_req pe_hold_req lib_ready lib_ready lib_init lib_init mpi_node_in[1:2] mpi_node_in[1:2] HEXRADIX mpi_node_out[1:2] mpi_node_out[1:2] HEXRADIX ex1_state_mach ex1_state_mach fifo_data_out[7:0] fifo_data_out[7:0] instruction_ack_i instruction_ack_i instruction_ack instruction_ack