-- VHDL Instantiation Created from source file DEMUX1.vhd -- 12:17:42 06/13/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT DEMUX1
	PORT(
		di : IN std_logic;
		sel : IN std_logic;          
		do1 : OUT std_logic;
		do2 : OUT std_logic
		);
	END COMPONENT;

	Inst_DEMUX1: DEMUX1 PORT MAP(
		di => ,
		sel => ,
		do1 => ,
		do2 => 
	);