-- VHDL Instantiation Created from source file EX1_FSM.vhd -- 05:54:42 06/21/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT EX1_FSM
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		fifo_empty : IN std_logic;
		fifo_data_out : IN std_logic_vector(7 downto 0);
		switch_port_in_full : IN std_logic;
		ram_data : IN std_logic_vector(7 downto 0);
		dma_grant : IN std_logic;          
		ram_address : OUT std_logic_vector(15 downto 0);
		priority_rotation : OUT std_logic;
		fifo_rd_en : OUT std_logic;
		switch_port_in_data : OUT std_logic_vector(7 downto 0);
		switch_port_in_wr_en : OUT std_logic;
		dma_request : OUT std_logic
		);
	END COMPONENT;

	Inst_EX1_FSM: EX1_FSM PORT MAP(
		clk => ,
		reset => ,
		fifo_empty => ,
		fifo_data_out => ,
		switch_port_in_full => ,
		ram_data => ,
		ram_address => ,
		priority_rotation => ,
		fifo_rd_en => ,
		switch_port_in_data => ,
		switch_port_in_wr_en => ,
		dma_request => ,
		dma_grant => 
	);