-- VHDL Instantiation Created from source file INPUT_PORT_MODULE.vhd -- 15:22:33 06/19/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT INPUT_PORT_MODULE
	PORT(
		data_in : IN std_logic_vector(7 downto 0);
		data_in_en : IN std_logic;
		reset : IN std_logic;
		clk : IN std_logic;
		grant : IN std_logic_vector(4 downto 1);          
		request : OUT std_logic_vector(4 downto 1);
		fifo_full : OUT std_logic;
		fifo_empty : OUT std_logic;
		priority_rotation : OUT std_logic;
		data_out : OUT std_logic_vector(7 downto 0);
		data_out_pulse : OUT std_logic
		);
	END COMPONENT;

	Inst_INPUT_PORT_MODULE: INPUT_PORT_MODULE PORT MAP(
		data_in => ,
		data_in_en => ,
		reset => ,
		clk => ,
		request => ,
		grant => ,
		fifo_full => ,
		fifo_empty => ,
		priority_rotation => ,
		data_out => ,
		data_out_pulse => 
	);