-- VHDL Instantiation Created from source file MPI_CORE_SCHEDULER.vhd -- 06:00:01 06/21/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT MPI_CORE_SCHEDULER
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		priority_rotation : IN std_logic;
		instruction_fifo_empty : IN std_logic;
		get_request_fifo_empty : IN std_logic;
		instruction_fifo_data : IN std_logic_vector(7 downto 0);
		get_request_fifo_data : IN std_logic_vector(7 downto 0);
		fifo_rd_en : IN std_logic;          
		instruction_fifo_rd_en : OUT std_logic;
		get_request_fifo_rd_en : OUT std_logic;
		fifo_selected : OUT std_logic;
		instruction_available : OUT std_logic;
		fifo_empty : OUT std_logic;
		data_out : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	Inst_MPI_CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP(
		clk => ,
		reset => ,
		priority_rotation => ,
		instruction_fifo_empty => ,
		get_request_fifo_empty => ,
		instruction_fifo_rd_en => ,
		get_request_fifo_rd_en => ,
		instruction_fifo_data => ,
		get_request_fifo_data => ,
		fifo_selected => ,
		instruction_available => ,
		fifo_empty => ,
		fifo_rd_en => ,
		data_out => 
	);