-- VHDL Instantiation Created from source file MUX8.vhd -- 12:18:04 06/13/2011
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT MUX8
	PORT(
		di1 : IN std_logic_vector(7 downto 0);
		di2 : IN std_logic_vector(7 downto 0);
		sel : IN std_logic;          
		do : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	Inst_MUX8: MUX8 PORT MAP(
		di1 => ,
		di2 => ,
		sel => ,
		do => 
	);