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Mar 3, 2014:

4:47 PM Changeset [89] by szahmed

Added Headline comments for Verilog files explaining their brief …

4:09 PM Changeset [88] by lambert

Updating qsys file

4:09 PM Changeset [87] by lambert

Adding generation simulation support for verilog

3:12 PM Changeset [86] by szahmed

correct qsys.qsys

3:06 PM Changeset [85] by szahmed

Added Projects folder

2:44 PM Changeset [84] by lambert

Adding hierarchical subdirectory for every component

2:34 PM Changeset [83] by szahmed

Initial Commit

Feb 25, 2014:

11:10 AM Changeset [82] by lambert

Removing .ht* tests, doesn't work sadly

11:08 AM Changeset [81] by lambert

* Adding Doc/README to test revision file * Testing .htaccess and …

10:25 AM Changeset [80] by lambert

Adding standard layout of svn tree

9:46 AM Changeset [79] by lambert

Introducing PROJECT_SMART_EEG in syel svn repository