| 1 | #include <systemc.h> |
|---|
| 2 | |
|---|
| 3 | #define ASSERT(x) \ |
|---|
| 4 | { \ |
|---|
| 5 | if (!(x)) \ |
|---|
| 6 | { \ |
|---|
| 7 | cerr << "ASSERT : " #x "\n"; \ |
|---|
| 8 | exit (1); \ |
|---|
| 9 | } \ |
|---|
| 10 | } |
|---|
| 11 | |
|---|
| 12 | using namespace std; |
|---|
| 13 | |
|---|
| 14 | struct test : sc_module { |
|---|
| 15 | int reg; |
|---|
| 16 | sc_signal<bool> reg_bool; |
|---|
| 17 | sc_signal<int> reg_int; |
|---|
| 18 | sc_signal<unsigned int> reg_unsigned_int; |
|---|
| 19 | sc_signal<char> reg_char; |
|---|
| 20 | sc_signal<double> reg_double; |
|---|
| 21 | sc_signal<long> reg_long; |
|---|
| 22 | sc_signal<sc_uint<32> > reg_ui32; |
|---|
| 23 | sc_signal<sc_uint<16> > reg_ui16; |
|---|
| 24 | sc_signal<sc_uint<6> > reg_ui6; |
|---|
| 25 | sc_signal<sc_int<32> > reg_i32; |
|---|
| 26 | sc_signal<sc_int<16> > reg_i16; |
|---|
| 27 | sc_signal<sc_int<6> > reg_i6; |
|---|
| 28 | |
|---|
| 29 | sc_in_clk clk; |
|---|
| 30 | sc_in<bool> resetn; |
|---|
| 31 | |
|---|
| 32 | void trans () |
|---|
| 33 | { |
|---|
| 34 | if (resetn.read() == true) |
|---|
| 35 | { |
|---|
| 36 | ASSERT(((reg & 1)) == reg_bool .read()); |
|---|
| 37 | ASSERT(((int) reg) == reg_int .read()); |
|---|
| 38 | ASSERT(((unsigned int)reg) == reg_unsigned_int .read()); |
|---|
| 39 | ASSERT(((char) reg) == reg_char .read()); |
|---|
| 40 | ASSERT(((double)reg) == reg_double.read()); |
|---|
| 41 | ASSERT(((long) reg) == reg_long .read()); |
|---|
| 42 | ASSERT(((unsigned int) reg & 0xFFFFFFFF) == (unsigned int) (reg_ui32 .read())); |
|---|
| 43 | ASSERT(((unsigned int) reg & 0x0000FFFF) == (unsigned int) (reg_ui16 .read())); |
|---|
| 44 | #if 0 |
|---|
| 45 | cerr << reg_ui6.read() << " " << (reg & 0x0000003F) << endl; |
|---|
| 46 | #endif |
|---|
| 47 | ASSERT(((unsigned int) reg & 0x0000003F) == (unsigned int) (reg_ui6 .read())); |
|---|
| 48 | ASSERT(((signed int) reg & 0xFFFFFFFF) == (signed int) (reg_i32 .read())); |
|---|
| 49 | ASSERT(((signed int) reg & 0x0000FFFF) == (signed int) (reg_i16 .read())); |
|---|
| 50 | ASSERT(((signed int) reg & 0x0000003F) == (signed int) (reg_i6 .read())); |
|---|
| 51 | reg = reg + 1; |
|---|
| 52 | reg_bool = reg & 1; |
|---|
| 53 | reg_int = reg; |
|---|
| 54 | reg_unsigned_int = reg; |
|---|
| 55 | reg_char = reg; |
|---|
| 56 | reg_double = reg; |
|---|
| 57 | reg_long = reg; |
|---|
| 58 | reg_ui32 = reg; |
|---|
| 59 | reg_ui16 = reg; |
|---|
| 60 | reg_ui6 = reg; |
|---|
| 61 | reg_i32 = reg; |
|---|
| 62 | reg_i16 = reg; |
|---|
| 63 | reg_i6 = reg; |
|---|
| 64 | } else { |
|---|
| 65 | reg = 0; |
|---|
| 66 | reg_bool = 0; |
|---|
| 67 | reg_int = 0; |
|---|
| 68 | reg_unsigned_int = 0; |
|---|
| 69 | reg_char = 0; |
|---|
| 70 | reg_double = 0; |
|---|
| 71 | reg_long = 0; |
|---|
| 72 | reg_ui32 = 0; |
|---|
| 73 | reg_ui16 = 0; |
|---|
| 74 | reg_ui6 = 0; |
|---|
| 75 | reg_i32 = 0; |
|---|
| 76 | reg_i16 = 0; |
|---|
| 77 | reg_i6 = 0; |
|---|
| 78 | } |
|---|
| 79 | } |
|---|
| 80 | |
|---|
| 81 | SC_HAS_PROCESS(test); |
|---|
| 82 | test (sc_module_name n) : sc_module (n), |
|---|
| 83 | clk("clk") |
|---|
| 84 | { |
|---|
| 85 | SC_METHOD(trans); |
|---|
| 86 | sensitive << clk.pos(); |
|---|
| 87 | dont_initialize(); |
|---|
| 88 | }; |
|---|
| 89 | }; |
|---|
| 90 | |
|---|
| 91 | int sc_main (int argc, char *argv[]) |
|---|
| 92 | { |
|---|
| 93 | sc_clock signal_clk("my_clock",1, 0.5); |
|---|
| 94 | sc_signal<bool> resetn("resetn"); |
|---|
| 95 | |
|---|
| 96 | test test1("test1"); |
|---|
| 97 | test1.clk (signal_clk); |
|---|
| 98 | test1.resetn (resetn); |
|---|
| 99 | |
|---|
| 100 | // Init & run |
|---|
| 101 | sc_start (0); |
|---|
| 102 | |
|---|
| 103 | resetn = false; |
|---|
| 104 | sc_start (4); |
|---|
| 105 | resetn = true; |
|---|
| 106 | sc_start (100); |
|---|
| 107 | |
|---|
| 108 | return EXIT_SUCCESS; |
|---|
| 109 | } |
|---|
| 110 | |
|---|
| 111 | #undef sc_inout |
|---|
