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system.cpp @ 18

Last change on this file since 18 was 1, checked in by buchmann, 17 years ago
Initial import from CVS repository
File size: 16.3 KB

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1	#include <stdio.h>
2	#include <stdarg.h>
3	#include <stdlib.h>
4	#include <signal.h>
5	#include <systemc.h>
6
7	#include "chrono.h"
8	#include "shared/soclib_vci_interfaces.h"
9	#include "cache/soclib_caches_interfaces.h"
10	#include "binary/mips_binary.h"
11
12	/* VCI template parameters */
13	const int ERRLEN = 0;
14	const short ADDRSIZE = 32;
15	const short CELLSIZE = 4;
16
17	#include "interconnect/soclib_vci_gmn.h"
18	#include "processor/soclib_multi_mips.h"
19	#include "cache/soclib_vci_xcache.h"
20	#include "tty/soclib_vci_tty.h"
21	#include "systemio/locks/soclib_vci_ramlocks.h"
22	#include "systemio/timer/soclib_vci_multi_timer.h"
23	#include "shared/soclib_segment_table.h"
24	#include "ram/soclib_vci_multiram.h"
25
26	/* Max number of cycles to perform */
27	int max_cycles;
28
29	/* signal handler */
30	void sighandler (int i)
31	{
32	cerr << "Simulation aborted.\n";
33	exit (-1);
34	}
35
36
37	/* main */
38	int sc_main (int argc, char *argv[])
39	{
40
41	if (argc!=2)
42	{
43	printf("Usage : ./system.x nbCyclesToGo\n");
44	exit(1);
45	}
46	sscanf(argv[1],"%d",&max_cycles);
47
48	signal( SIGINT, sighandler );
49	signal( SIGTERM, sighandler );
50
51	/************************************************************************
52	*
53	* Signal declaration
54	*
55	************************************************************************/
56
57	sc_clock signal_clk("clock");
58	sc_signal<bool> signal_resetn("resetn");
59	ICACHE_SIGNALS _xcache0_ICACHE_mips0_ICACHE;
60	DCACHE_SIGNALS _xcache0_DCACHE_mips0_DCACHE;
61	ICACHE_SIGNALS _xcache1_ICACHE_mips1_ICACHE;
62	DCACHE_SIGNALS _xcache1_DCACHE_mips1_DCACHE;
63	ICACHE_SIGNALS _xcache2_ICACHE_mips2_ICACHE;
64	DCACHE_SIGNALS _xcache2_DCACHE_mips2_DCACHE;
65	ICACHE_SIGNALS _xcache3_ICACHE_mips3_ICACHE;
66	DCACHE_SIGNALS _xcache3_DCACHE_mips3_DCACHE;
67	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _gmn_T_VCI_3__xcache3_VCI;
68	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _gmn_T_VCI_2__xcache2_VCI;
69	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _gmn_T_VCI_1__xcache1_VCI;
70	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _gmn_T_VCI_0__xcache0_VCI;
71	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _vcitty0_VCI_gmn_I_VCI_0_;
72	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _vcitty1_VCI_gmn_I_VCI_1_;
73	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _vcitty2_VCI_gmn_I_VCI_2_;
74	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _vcitty3_VCI_gmn_I_VCI_3_;
75	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _locks_VCI_gmn_I_VCI_6_;
76	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _multitimer_VCI_gmn_I_VCI_5_;
77	sc_signal<bool> _multitimer_IRQ_0__mips0_IT_0;
78	sc_signal<bool> _multitimer_IRQ_1__mips1_IT_0;
79	sc_signal<bool> _multitimer_IRQ_2__mips2_IT_0;
80	sc_signal<bool> _multitimer_IRQ_3__mips3_IT_0;
81	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _multiram0_VCI_gmn_I_VCI_4_;
82	ADVANCED_VCI_SIGNALS<ADDRSIZE,CELLSIZE,ERRLEN> _multiram1_VCI_gmn_I_VCI_7_;
83	sc_signal<bool> _mips0_IT_5;
84	sc_signal<bool> _mips0_IT_4;
85	sc_signal<bool> _mips0_IT_3;
86	sc_signal<bool> _mips0_IT_2;
87	sc_signal<bool> _mips0_IT_1;
88	sc_signal<sc_uint<1> > _mips0_D_FRZ;
89	sc_signal<sc_uint<1> > _mips0_I_FRZ;
90	sc_signal<bool> _mips1_IT_5;
91	sc_signal<bool> _mips1_IT_4;
92	sc_signal<bool> _mips1_IT_3;
93	sc_signal<bool> _mips1_IT_2;
94	sc_signal<bool> _mips1_IT_1;
95	sc_signal<sc_uint<1> > _mips1_D_FRZ;
96	sc_signal<sc_uint<1> > _mips1_I_FRZ;
97	sc_signal<bool> _mips2_IT_5;
98	sc_signal<bool> _mips2_IT_4;
99	sc_signal<bool> _mips2_IT_3;
100	sc_signal<bool> _mips2_IT_2;
101	sc_signal<bool> _mips2_IT_1;
102	sc_signal<sc_uint<1> > _mips2_D_FRZ;
103	sc_signal<sc_uint<1> > _mips2_I_FRZ;
104	sc_signal<bool> _mips3_IT_5;
105	sc_signal<bool> _mips3_IT_4;
106	sc_signal<bool> _mips3_IT_3;
107	sc_signal<bool> _mips3_IT_2;
108	sc_signal<bool> _mips3_IT_1;
109	sc_signal<sc_uint<1> > _mips3_D_FRZ;
110	sc_signal<sc_uint<1> > _mips3_I_FRZ;
111
112	/************************************************************************
113	*
114	* Segment table
115	*
116	************************************************************************/
117
118	SOCLIB_SEGMENT_TABLE segtab;
119	segtab.setMSBNumber(8);
120	segtab.setDefaultTarget(0);
121	segtab.addSegment("rom_reset",0xBFC00000,10000,4,false);
122	segtab.addSegment("rom_excep",0x80000080,10000,4,false);
123	segtab.addSegment("rom_code",0x00400000,50000,4, false);
124	segtab.addSegment("ram_util",0x10000000,50000,7, false);
125	segtab.addSegment("loc0",0x20000000,20000,7,false);
126	segtab.addSegment("loc1",0x21000000,20000,7,false);
127	segtab.addSegment("loc2",0x22000000,20000,7,false);
128	segtab.addSegment("loc3",0x23000000,20000,7,false);
129	segtab.addSegment("tty0",0xA0000000,100,0,true);
130	segtab.addSegment("tty1",0xA1000000,100,1,true);
131	segtab.addSegment("tty2",0xA2000000,100,2,true);
132	segtab.addSegment("tty3",0xA3000000,100,3,true);
133	segtab.addSegment("timer",0xB0000000,1000,5,true);
134	segtab.addSegment("locks",0xB2000000,10000,6,true);
135
136	/************************************************************************
137	*
138	* Soclib components instanciation
139	*
140	************************************************************************/
141
142	SOCLIB_VCI_GMN<4,8,2,8,32,4,0> gmn ("gmn",segtab);
143	SOCLIB_MULTI_MIPS<false,1,0> mips0 ("mips0",0,segtab);
144	SOCLIB_VCI_XCACHE<8,8,8,8> xcache0 ("xcache0",0);
145	SOCLIB_MULTI_MIPS<false,1,0> mips1 ("mips1",1,segtab);
146	SOCLIB_VCI_XCACHE<8,8,8,8> xcache1 ("xcache1",1);
147	SOCLIB_MULTI_MIPS<false,1,0> mips2 ("mips2",2,segtab);
148	SOCLIB_VCI_XCACHE<8,8,8,8> xcache2 ("xcache2",2);
149	SOCLIB_MULTI_MIPS<false,1,0> mips3 ("mips3",3,segtab);
150	SOCLIB_VCI_XCACHE<8,8,8,8> xcache3 ("xcache3",3);
151	SOCLIB_VCI_TTY vcitty0 ("vcitty0",0,segtab,true);
152	SOCLIB_VCI_TTY vcitty1 ("vcitty1",1,segtab,true);
153	SOCLIB_VCI_TTY vcitty2 ("vcitty2",2,segtab,true);
154	SOCLIB_VCI_TTY vcitty3 ("vcitty3",3,segtab,true);
155	SOCLIB_VCI_RAMLOCKS locks ("locks",6,segtab);
156	SOCLIB_VCI_MULTI_TIMER<4> multitimer("multitimer",5,segtab);
157	SOCLIB_VCI_MULTIRAM multiram0 ("multiram0",4,segtab);
158	SOCLIB_VCI_MULTIRAM multiram1 ("multiram1",7,segtab);
159
160	/************************************************************************
161	*
162	* Soclib topcell netlist
163	*
164	************************************************************************/
165
166	gmn.I_VCI[0](_vcitty0_VCI_gmn_I_VCI_0_);
167	gmn.I_VCI[3](_vcitty3_VCI_gmn_I_VCI_3_);
168	gmn.I_VCI[6](_locks_VCI_gmn_I_VCI_6_);
169	gmn.I_VCI[1](_vcitty1_VCI_gmn_I_VCI_1_);
170	gmn.I_VCI[4](_multiram0_VCI_gmn_I_VCI_4_);
171	gmn.I_VCI[7](_multiram1_VCI_gmn_I_VCI_7_);
172	gmn.I_VCI[2](_vcitty2_VCI_gmn_I_VCI_2_);
173	gmn.I_VCI[5](_multitimer_VCI_gmn_I_VCI_5_);
174	gmn.T_VCI[1](_gmn_T_VCI_1__xcache1_VCI);
175	gmn.T_VCI[2](_gmn_T_VCI_2__xcache2_VCI);
176	gmn.T_VCI[0](_gmn_T_VCI_0__xcache0_VCI);
177	gmn.T_VCI[3](_gmn_T_VCI_3__xcache3_VCI);
178	gmn.CLK(signal_clk);
179	gmn.RESETN(signal_resetn);
180
181	mips0.DCACHE(_xcache0_DCACHE_mips0_DCACHE);
182	mips0.ICACHE(_xcache0_ICACHE_mips0_ICACHE);
183	mips0.IT_5(_mips0_IT_5);
184	mips0.IT_4(_mips0_IT_4);
185	mips0.IT_3(_mips0_IT_3);
186	mips0.IT_2(_mips0_IT_2);
187	mips0.IT_1(_mips0_IT_1);
188	mips0.IT_0(_multitimer_IRQ_0__mips0_IT_0);
189	mips0.D_FRZ(_mips0_D_FRZ);
190	mips0.I_FRZ(_mips0_I_FRZ);
191	mips0.CLK(signal_clk);
192	mips0.RESETN(signal_resetn);
193
194	xcache0.VCI(_gmn_T_VCI_0__xcache0_VCI);
195	xcache0.DCACHE(_xcache0_DCACHE_mips0_DCACHE);
196	xcache0.ICACHE(_xcache0_ICACHE_mips0_ICACHE);
197	xcache0.CLK(signal_clk);
198	xcache0.RESETN(signal_resetn);
199
200	mips1.DCACHE(_xcache1_DCACHE_mips1_DCACHE);
201	mips1.ICACHE(_xcache1_ICACHE_mips1_ICACHE);
202	mips1.IT_5(_mips1_IT_5);
203	mips1.IT_4(_mips1_IT_4);
204	mips1.IT_3(_mips1_IT_3);
205	mips1.IT_2(_mips1_IT_2);
206	mips1.IT_1(_mips1_IT_1);
207	mips1.IT_0(_multitimer_IRQ_1__mips1_IT_0);
208	mips1.D_FRZ(_mips1_D_FRZ);
209	mips1.I_FRZ(_mips1_I_FRZ);
210	mips1.CLK(signal_clk);
211	mips1.RESETN(signal_resetn);
212
213	xcache1.VCI(_gmn_T_VCI_1__xcache1_VCI);
214	xcache1.DCACHE(_xcache1_DCACHE_mips1_DCACHE);
215	xcache1.ICACHE(_xcache1_ICACHE_mips1_ICACHE);
216	xcache1.CLK(signal_clk);
217	xcache1.RESETN(signal_resetn);
218
219	mips2.DCACHE(_xcache2_DCACHE_mips2_DCACHE);
220	mips2.ICACHE(_xcache2_ICACHE_mips2_ICACHE);
221	mips2.IT_5(_mips2_IT_5);
222	mips2.IT_4(_mips2_IT_4);
223	mips2.IT_3(_mips2_IT_3);
224	mips2.IT_2(_mips2_IT_2);
225	mips2.IT_1(_mips2_IT_1);
226	mips2.IT_0(_multitimer_IRQ_2__mips2_IT_0);
227	mips2.D_FRZ(_mips2_D_FRZ);
228	mips2.I_FRZ(_mips2_I_FRZ);
229	mips2.CLK(signal_clk);
230	mips2.RESETN(signal_resetn);
231
232	xcache2.VCI(_gmn_T_VCI_2__xcache2_VCI);
233	xcache2.DCACHE(_xcache2_DCACHE_mips2_DCACHE);
234	xcache2.ICACHE(_xcache2_ICACHE_mips2_ICACHE);
235	xcache2.CLK(signal_clk);
236	xcache2.RESETN(signal_resetn);
237
238	mips3.DCACHE(_xcache3_DCACHE_mips3_DCACHE);
239	mips3.ICACHE(_xcache3_ICACHE_mips3_ICACHE);
240	mips3.IT_5(_mips3_IT_5);
241	mips3.IT_4(_mips3_IT_4);
242	mips3.IT_3(_mips3_IT_3);
243	mips3.IT_2(_mips3_IT_2);
244	mips3.IT_1(_mips3_IT_1);
245	mips3.IT_0(_multitimer_IRQ_3__mips3_IT_0);
246	mips3.D_FRZ(_mips3_D_FRZ);
247	mips3.I_FRZ(_mips3_I_FRZ);
248	mips3.CLK(signal_clk);
249	mips3.RESETN(signal_resetn);
250
251	xcache3.VCI(_gmn_T_VCI_3__xcache3_VCI);
252	xcache3.DCACHE(_xcache3_DCACHE_mips3_DCACHE);
253	xcache3.ICACHE(_xcache3_ICACHE_mips3_ICACHE);
254	xcache3.CLK(signal_clk);
255	xcache3.RESETN(signal_resetn);
256
257	vcitty0.VCI(_vcitty0_VCI_gmn_I_VCI_0_);
258	vcitty0.CLK(signal_clk);
259	vcitty0.RESETN(signal_resetn);
260
261	vcitty1.VCI(_vcitty1_VCI_gmn_I_VCI_1_);
262	vcitty1.CLK(signal_clk);
263	vcitty1.RESETN(signal_resetn);
264
265	vcitty2.VCI(_vcitty2_VCI_gmn_I_VCI_2_);
266	vcitty2.CLK(signal_clk);
267	vcitty2.RESETN(signal_resetn);
268
269	vcitty3.VCI(_vcitty3_VCI_gmn_I_VCI_3_);
270	vcitty3.CLK(signal_clk);
271	vcitty3.RESETN(signal_resetn);
272
273	locks.VCI(_locks_VCI_gmn_I_VCI_6_);
274	locks.CLK(signal_clk);
275	locks.RESETN(signal_resetn);
276
277	multitimer.IRQ[0](_multitimer_IRQ_0__mips0_IT_0);
278	multitimer.IRQ[3](_multitimer_IRQ_3__mips3_IT_0);
279	multitimer.IRQ[1](_multitimer_IRQ_1__mips1_IT_0);
280	multitimer.IRQ[2](_multitimer_IRQ_2__mips2_IT_0);
281	multitimer.VCI(_multitimer_VCI_gmn_I_VCI_5_);
282	multitimer.CLK(signal_clk);
283	multitimer.RESETN(signal_resetn);
284
285
286	multiram0.VCI(_multiram0_VCI_gmn_I_VCI_4_);
287	multiram0.CLK(signal_clk);
288	multiram0.RESETN(signal_resetn);
289
290	multiram1.VCI(_multiram1_VCI_gmn_I_VCI_7_);
291	multiram1.CLK(signal_clk);
292	multiram1.RESETN(signal_resetn);
293
294	/************************************************************************
295	*
296	* Load Application Binaries into memories
297	*
298	************************************************************************/
299
300	char *sections_rom_reset[]={".reset",NULL};
301	MIPS_BINARY mb_rom_reset("a.out",sections_rom_reset);
302	multiram0.load("rom_reset",mb_rom_reset);
303
304	char *sections_rom_excep[]={".excep",NULL};
305	MIPS_BINARY mb_rom_excep("a.out",sections_rom_excep);
306	multiram0.load("rom_excep",mb_rom_excep);
307
308	char *sections_rom_code[]={".text",NULL};
309	MIPS_BINARY mb_rom_code("a.out",sections_rom_code);
310	multiram0.load("rom_code",mb_rom_code);
311
312	char *sections_ram_util[]={".rodata",".data",".sdata",".sbss",".bss",NULL};
313	MIPS_BINARY mb_ram_util("a.out",sections_ram_util);
314	multiram1.load("ram_util",mb_ram_util);
315
316
317	/************************************************************************
318	*
319	* Signal trace management
320	*
321	************************************************************************/
322
323	#ifdef ENABLE_TRACE
324	/* Open trace file */
325	sc_trace_file *system_trace_file;
326	system_trace_file = sc_create_vcd_trace_file ("trace_file");
327
328	/* clk and resetn waveforms are always useful */
329	sc_trace(system_trace_file, signal_clk, "clk");
330	sc_trace(system_trace_file, signal_resetn, "resetn");
331	sc_trace(system_trace_file, mips0.PC[0], "mips0.PC");
332	sc_trace(system_trace_file, mips1.PC[0], "mips1.PC");
333	sc_trace(system_trace_file, mips2.PC[0], "mips2.PC");
334	sc_trace(system_trace_file, mips3.PC[0], "mips3.PC");
335	sc_trace(system_trace_file, _mips0_IT_5, "_mips0_IT_5");
336	sc_trace(system_trace_file, _mips0_IT_4, "_mips0_IT_4");
337	sc_trace(system_trace_file, _mips0_IT_3, "_mips0_IT_3");
338	sc_trace(system_trace_file, _mips0_IT_2, "_mips0_IT_2");
339	sc_trace(system_trace_file, _mips0_IT_1, "_mips0_IT_1");
340	sc_trace(system_trace_file, _mips0_D_FRZ, "_mips0_D_FRZ");
341	sc_trace(system_trace_file, _mips0_I_FRZ, "_mips0_I_FRZ");
342	sc_trace(system_trace_file, _multiram0_VCI_gmn_I_VCI_4_, "_multiram0_VCI_gmn_I_VCI_4_");
343	sc_trace(system_trace_file, multiram0.VCI, "multiram0.VCI");
344	sc_trace(system_trace_file, gmn.I_VCI[4], "gmn.I_VCI(4)");
345	sc_trace(system_trace_file, gmn.I_VCI[3], "gmn.I_VCI(3)");
346	sc_trace(system_trace_file, gmn.I_VCI[2], "gmn.I_VCI(2)");
347	sc_trace(system_trace_file, gmn.I_VCI[1], "gmn.I_VCI(1)");
348	sc_trace(system_trace_file, gmn.I_VCI[0], "gmn.I_VCI(0)");
349	sc_trace(system_trace_file, gmn.T_VCI[3], "gmn.T_VCI(3)");
350	sc_trace(system_trace_file, gmn.T_VCI[2], "gmn.T_VCI(2)");
351	sc_trace(system_trace_file, gmn.T_VCI[1], "gmn.T_VCI(1)");
352	sc_trace(system_trace_file, gmn.T_VCI[0], "gmn.T_VCI(0)");
353	sc_trace(system_trace_file, _xcache0_ICACHE_mips0_ICACHE, "_ICACHE_mips0");
354	sc_trace(system_trace_file, _xcache0_DCACHE_mips0_DCACHE, "_DCACHE_mips0");
355	#ifdef ENABLE_PAT
356	/* Open trace file */
357	sc_trace_file *system_trace_file2;
358	system_trace_file2 = sc_create_pat_trace_file ("trace_file");
359
360	/* clk and resetn waveforms are always useful */
361	sc_trace(system_trace_file2, signal_clk, "clk");
362	sc_trace(system_trace_file2, signal_resetn, "resetn");
363	sc_trace(system_trace_file2, mips0.PC[0], "mips0.PC");
364	sc_trace(system_trace_file2, mips1.PC[0], "mips1.PC");
365	sc_trace(system_trace_file2, mips2.PC[0], "mips2.PC");
366	sc_trace(system_trace_file2, mips3.PC[0], "mips3.PC");
367	sc_trace(system_trace_file2, _mips2_IT_5, "mips2_IT_5");
368	sc_trace(system_trace_file2, _mips2_IT_4, "mips2_IT_4");
369	sc_trace(system_trace_file2, _mips2_IT_3, "mips2_IT_3");
370	sc_trace(system_trace_file2, _mips2_IT_2, "mips2_IT_2");
371	sc_trace(system_trace_file2, _mips2_IT_1, "mips2_IT_1");
372	sc_trace(system_trace_file2, _mips2_D_FRZ, "mips2_D_FRZ");
373	sc_trace(system_trace_file2, _mips2_I_FRZ, "mips2_I_FRZ");
374	sc_trace(system_trace_file2, mips0 .DCACHE, "mips0.DCACHE");
375	sc_trace(system_trace_file2, mips0 .ICACHE, "mips0.ICACHE");
376	sc_trace(system_trace_file2, mips1 .DCACHE, "mips1.DCACHE");
377	sc_trace(system_trace_file2, mips1 .ICACHE, "mips1.ICACHE");
378	sc_trace(system_trace_file2, mips2 .DCACHE, "mips2.DCACHE");
379	sc_trace(system_trace_file2, mips2 .ICACHE, "mips2.ICACHE");
380	sc_trace(system_trace_file2, mips3 .DCACHE, "mips3.DCACHE");
381	sc_trace(system_trace_file2, mips3 .ICACHE, "mips3.ICACHE");
382	sc_trace(system_trace_file2, xcache0 .VCI, "xcache0.VCI");
383	sc_trace(system_trace_file2, xcache1 .VCI, "xcache1.VCI");
384	sc_trace(system_trace_file2, xcache2 .VCI, "xcache2.VCI");
385	sc_trace(system_trace_file2, xcache3 .VCI, "xcache3.VCI");
386	sc_trace(system_trace_file2, vcitty0 .VCI, "vcitty0.VCI");
387	sc_trace(system_trace_file2, vcitty1 .VCI, "vcitty1.VCI");
388	sc_trace(system_trace_file2, vcitty2 .VCI, "vcitty2.VCI");
389	sc_trace(system_trace_file2, vcitty3 .VCI, "vcitty3.VCI");
390	sc_trace(system_trace_file2, locks .VCI, "locks.VCI");
391	sc_trace(system_trace_file2, multitimer.VCI, "multitimer.VCI");
392	sc_trace(system_trace_file2, multiram0 .VCI, "multiram0.VCI");
393	sc_trace(system_trace_file2, multiram1 .VCI, "multiram1.VCI");
394
395	#endif
396
397	#endif
398
399	/******************************************************************************
400	*
401	* Simulation loop
402	*
403	******************************************************************************/
404
405	sc_initialize ();
406
407	chrono_t chrono;
408	chrono.start ();
409	signal_resetn = false;
410	sc_start(1);
411	signal_resetn = true;
412	_mips0_IT_5=0;
413	_mips0_IT_4=0;
414	_mips0_IT_3=0;
415	_mips0_IT_2=0;
416	_mips0_IT_1=0;
417	_mips0_D_FRZ=0;
418	_mips0_I_FRZ=0;
419	_mips1_IT_5=0;
420	_mips1_IT_4=0;
421	_mips1_IT_3=0;
422	_mips1_IT_2=0;
423	_mips1_IT_1=0;
424	_mips1_D_FRZ=0;
425	_mips1_I_FRZ=0;
426	_mips2_IT_5=0;
427	_mips2_IT_4=0;
428	_mips2_IT_3=0;
429	_mips2_IT_2=0;
430	_mips2_IT_1=0;
431	_mips2_D_FRZ=0;
432	_mips2_I_FRZ=0;
433	_mips3_IT_5=0;
434	_mips3_IT_4=0;
435	_mips3_IT_3=0;
436	_mips3_IT_2=0;
437	_mips3_IT_1=0;
438	_mips3_D_FRZ=0;
439	_mips3_I_FRZ=0;
440
441	sc_start(max_cycles);
442	/*
443	for (int i = 0; i < max_cycles; i++)
444	{
445	sc_start(1);
446	cout << sc_simulation_time () << " cycle : ";
447	cout << "PC = " << hex << mips0.PC[0];
448	cout << ",IR = " << hex << mips0.IR[0];
449	cout << "\n";
450
451	if (((int)(sc_simulation_time ()) % 10000) == 0)
452	{
453	printf("\nElapsed : %10.10d cycles.", (int)(sc_simulation_time ()));
454	}
455	}
456	*/
457	chrono.stop ();
458	unsigned int d = chrono;
459	cout << "Time elapsed (sec) : " << d << endl;
460	cout << "Cycles done : " << sc_simulation_time () << endl;
461	cout << "Performance : " << sc_simulation_time () / d << endl;
462
463	//
464	#ifdef ENABLE_TRACE
465	sc_close_vcd_trace_file (system_trace_file);
466	#ifdef ENABLE_PAT
467	sc_close_pat_trace_file (system_trace_file2);
468	#endif
469	#endif
470
471	printf("\nPress <RETURN> to exit simulation.");
472	char buf_ret[2];
473	cin.getline(buf_ret,1);
474
475	return EXIT_SUCCESS;
476	}

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source: sources/examples/soclib_date04/timer4_gmn_handmade/system.cpp @ 18

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