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vci_cc_vcache_wrapper.h @ 494

Last change on this file since 494 was 494, checked in by devigne, 12 years ago
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1	/* -- c++ --
2	*
3	* File : vci_cc_vcache_wrapper.h
4	* Copyright (c) UPMC, Lip6, SoC
5	* Authors : Alain GREINER, Yang GAO
6	* Date : 27/11/2011
7	*
8	* SOCLIB_LGPL_HEADER_BEGIN
9	*
10	* This file is part of SoCLib, GNU LGPLv2.1.
11	*
12	* SoCLib is free software; you can redistribute it and/or modify it
13	* under the terms of the GNU Lesser General Public License as published
14	* by the Free Software Foundation; version 2.1 of the License.
15	*
16	* SoCLib is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* Lesser General Public License for more details.
20	*
21	* You should have received a copy of the GNU Lesser General Public
22	* License along with SoCLib; if not, write to the Free Software
23	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24	* 02110-1301 USA
25	*
26	* SOCLIB_LGPL_HEADER_END
27	*
28	* Maintainers: cesar.fuguet-tortolero@lip6.fr
29	* alexandre.joannou@lip6.fr
30	*/
31
32	#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33	#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35	#include <inttypes.h>
36	#include <systemc>
37	#include "caba_base_module.h"
38	#include "multi_write_buffer.h"
39	#include "generic_fifo.h"
40	#include "generic_tlb.h"
41	#include "generic_cache.h"
42	#include "vci_initiator.h"
43	#include "dspin_interface.h"
44	#include "dspin_dhccp_param.h"
45	#include "mapping_table.h"
46	#include "static_assert.h"
47	#include "iss2.h"
48
49	#define LLSC_TIMEOUT 10000
50
51	namespace soclib {
52	namespace caba {
53
54	using namespace sc_core;
55
56	////////////////////////////////////////////
57	template<typename vci_param,
58	size_t dspin_in_width,
59	size_t dspin_out_width,
60	typename iss_t>
61	class VciCcVCacheWrapper
62	////////////////////////////////////////////
63	: public soclib::caba::BaseModule
64	{
65
66	typedef typename vci_param::fast_addr_t paddr_t;
67
68	enum icache_fsm_state_e
69	{
70	ICACHE_IDLE,
71	// handling XTN processor requests
72	ICACHE_XTN_TLB_FLUSH,
73	ICACHE_XTN_CACHE_FLUSH,
74	ICACHE_XTN_CACHE_FLUSH_GO,
75	ICACHE_XTN_TLB_INVAL,
76	ICACHE_XTN_CACHE_INVAL_VA,
77	ICACHE_XTN_CACHE_INVAL_PA,
78	ICACHE_XTN_CACHE_INVAL_GO,
79	// handling tlb miss
80	ICACHE_TLB_WAIT,
81	// handling cache miss
82	ICACHE_MISS_SELECT,
83	ICACHE_MISS_CLEAN,
84	ICACHE_MISS_WAIT,
85	ICACHE_MISS_DATA_UPDT,
86	ICACHE_MISS_DIR_UPDT,
87	// handling unc read
88	ICACHE_UNC_WAIT,
89	// handling coherence requests
90	ICACHE_CC_CHECK,
91	ICACHE_CC_UPDT,
92	ICACHE_CC_INVAL,
93	};
94
95	enum dcache_fsm_state_e
96	{
97	DCACHE_IDLE,
98	// handling itlb & dtlb miss
99	DCACHE_TLB_MISS,
100	DCACHE_TLB_PTE1_GET,
101	DCACHE_TLB_PTE1_SELECT,
102	DCACHE_TLB_PTE1_UPDT,
103	DCACHE_TLB_PTE2_GET,
104	DCACHE_TLB_PTE2_SELECT,
105	DCACHE_TLB_PTE2_UPDT,
106	DCACHE_TLB_LR_UPDT,
107	DCACHE_TLB_LR_WAIT,
108	DCACHE_TLB_RETURN,
109	// handling processor XTN requests
110	DCACHE_XTN_SWITCH,
111	DCACHE_XTN_SYNC,
112	DCACHE_XTN_IC_INVAL_VA,
113	DCACHE_XTN_IC_FLUSH,
114	DCACHE_XTN_IC_INVAL_PA,
115	DCACHE_XTN_IT_INVAL,
116	DCACHE_XTN_DC_FLUSH,
117	DCACHE_XTN_DC_FLUSH_DATA,
118	DCACHE_XTN_DC_FLUSH_GO,
119	DCACHE_XTN_DC_INVAL_VA,
120	DCACHE_XTN_DC_INVAL_PA,
121	DCACHE_XTN_DC_INVAL_END,
122	DCACHE_XTN_DC_INVAL_GO,
123	DCACHE_XTN_DC_INVAL_DATA,
124	DCACHE_XTN_DT_INVAL,
125	//handling dirty bit update
126	DCACHE_DIRTY_GET_PTE,
127	DCACHE_DIRTY_WAIT,
128	// handling processor miss requests
129	DCACHE_MISS_SELECT,
130	DCACHE_MISS_CLEAN,
131	DCACHE_MISS_DATA,
132	DCACHE_MISS_WAIT,
133	DCACHE_MISS_DATA_UPDT,
134	DCACHE_MISS_DIR_UPDT,
135	// handling processor unc, ll and sc requests
136	DCACHE_UNC_WAIT,
137	DCACHE_LL_WAIT,
138	DCACHE_SC_WAIT,
139	// handling coherence requests
140	DCACHE_CC_CHECK,
141	DCACHE_CC_UPDT,
142	DCACHE_CC_INVAL,
143	DCACHE_CC_INVAL_DATA,
144	// handling TLB inval (after a coherence or XTN request)
145	DCACHE_INVAL_TLB_SCAN,
146	};
147
148	enum cmd_fsm_state_e
149	{
150	CMD_IDLE,
151	CMD_INS_MISS,
152	CMD_INS_UNC,
153	CMD_DATA_MISS,
154	CMD_DATA_UNC,
155	CMD_DATA_WRITE,
156	CMD_DATA_LL,
157	CMD_DATA_SC,
158	CMD_DATA_CAS,
159	};
160
161	enum rsp_fsm_state_e
162	{
163	RSP_IDLE,
164	RSP_INS_MISS,
165	RSP_INS_UNC,
166	RSP_DATA_MISS,
167	RSP_DATA_UNC,
168	RSP_DATA_LL,
169	RSP_DATA_WRITE,
170	};
171
172	enum cc_receive_fsm_state_e
173	{
174	CC_RECEIVE_IDLE,
175	CC_RECEIVE_BRDCAST_HEADER,
176	CC_RECEIVE_BRDCAST_NLINE,
177	CC_RECEIVE_INS_INVAL_HEADER,
178	CC_RECEIVE_INS_INVAL_NLINE,
179	CC_RECEIVE_INS_UPDT_HEADER,
180	CC_RECEIVE_INS_UPDT_NLINE,
181	CC_RECEIVE_DATA_INVAL_HEADER,
182	CC_RECEIVE_DATA_INVAL_NLINE,
183	CC_RECEIVE_DATA_UPDT_HEADER,
184	CC_RECEIVE_DATA_UPDT_NLINE,
185	CC_RECEIVE_INS_UPDT_DATA,
186	CC_RECEIVE_DATA_UPDT_DATA,
187	};
188
189	enum cc_send_fsm_state_e
190	{
191	CC_SEND_IDLE,
192	CC_SEND_CLEANUP_1,
193	CC_SEND_CLEANUP_2,
194	CC_SEND_CLEANUP_DATA_UPDT,
195	CC_SEND_MULTI_ACK,
196	};
197
198	/* transaction type, pktid field */
199	enum transaction_type_e
200	{
201	// b3 ODCCP/RWT : COHERENT/NO COHERENT
202	// b2 READ / NOT READ
203	// if READ
204	// b1 DATA / INS
205	// b0 UNC / MISS
206	// else
207	// b1 accÃšs table llsc type SW / other
208	// b2 WRITE/CAS/LL/SC
209	TYPE_READ_DATA_UNC = 0x0,
210	TYPE_READ_DATA_MISS = 0x1,
211	TYPE_READ_INS_UNC = 0x2,
212	TYPE_READ_INS_MISS = 0x3,
213	TYPE_WRITE = 0x4,
214	TYPE_CAS = 0x5,
215	TYPE_LL = 0x6,
216	TYPE_SC = 0x7,
217	TYPE_READ_DATA_MISS_NO_COHERENT = 0x9
218	};
219
220	/* SC return values */
221	enum sc_status_type_e
222	{
223	SC_SUCCESS = 0x00000000,
224	SC_FAIL = 0x00000001
225	};
226
227	// cc_send_type
228	typedef enum
229	{
230	CC_TYPE_CLEANUP,
231	CC_TYPE_MULTI_ACK,
232	} cc_send_t;
233
234	// cc_receive_type
235	typedef enum
236	{
237	CC_TYPE_CLACK,
238	CC_TYPE_BRDCAST,
239	CC_TYPE_INVAL,
240	CC_TYPE_UPDT,
241	} cc_receive_t;
242
243	// TLB Mode : ITLB / DTLB / ICACHE / DCACHE
244	enum
245	{
246	INS_TLB_MASK = 0x8,
247	DATA_TLB_MASK = 0x4,
248	INS_CACHE_MASK = 0x2,
249	DATA_CACHE_MASK = 0x1,
250	};
251
252	// Error Type
253	enum mmu_error_type_e
254	{
255	MMU_NONE = 0x0000, // None
256	MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1
257	MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2
258	MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
259	MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page
260	MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write & undefined external access
261	MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write & Bus Error accessing PT1
262	MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2
263	MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
264	MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1
265	MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2
266	MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode
267	MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page
268	MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access
269	MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1
270	MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2
271	MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access
272	};
273
274	// miss types for data cache
275	enum dcache_miss_type_e
276	{
277	PTE1_MISS,
278	PTE2_MISS,
279	PROC_MISS,
280	};
281
282	enum transaction_type_d_e
283	{
284	// b0 : 1 if cached
285	// b1 : 1 if instruction
286	TYPE_DATA_UNC = 0x0,
287	TYPE_DATA_MISS = 0x1,
288	TYPE_INS_UNC = 0x2,
289	TYPE_INS_MISS = 0x3,
290	};
291
292	//////////////////MODIFIED////////////////
293	enum content_line_cache_status_e
294	{
295	LINE_CACHE_DATA_NOT_DIRTY,
296	LINE_CACHE_DATA_DIRTY,
297	LINE_CACHE_IN_TLB,
298	LINE_CACHE_CONTAINS_PTD,
299	};
300	//////////////////////////////////////////
301
302	public:
303	sc_in<bool> p_clk;
304	sc_in<bool> p_resetn;
305	sc_in<bool> p_irq[iss_t::n_irq];
306	soclib::caba::VciInitiator<vci_param> p_vci;
307	soclib::caba::DspinInput<dspin_in_width> p_dspin_m2p;
308	soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
309	soclib::caba::DspinInput<dspin_in_width> p_dspin_clack;
310
311	private:
312
313	// STRUCTURAL PARAMETERS
314	soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
315
316	const size_t m_srcid;
317	const size_t m_cc_global_id;
318	const size_t m_nline_width;
319	const size_t m_itlb_ways;
320	const size_t m_itlb_sets;
321	const size_t m_dtlb_ways;
322	const size_t m_dtlb_sets;
323	const size_t m_icache_ways;
324	const size_t m_icache_sets;
325	const paddr_t m_icache_yzmask;
326	const size_t m_icache_words;
327	const size_t m_dcache_ways;
328	const size_t m_dcache_sets;
329	const paddr_t m_dcache_yzmask;
330	const size_t m_dcache_words;
331	const size_t m_x_width;
332	const size_t m_y_width;
333	const size_t m_proc_id;
334	const uint32_t m_max_frozen_cycles;
335	const size_t m_paddr_nbits;
336	uint32_t m_debug_start_cycle;
337	bool m_debug_ok;
338
339	////////////////////////////////////////
340	// Communication with processor ISS
341	////////////////////////////////////////
342	typename iss_t::InstructionRequest m_ireq;
343	typename iss_t::InstructionResponse m_irsp;
344	typename iss_t::DataRequest m_dreq;
345	typename iss_t::DataResponse m_drsp;
346
347	/////////////////////////////////////////////
348	// debug variables
349	/////////////////////////////////////////////
350	bool m_debug_previous_i_hit;
351	bool m_debug_previous_d_hit;
352	bool m_debug_activated;
353
354	///////////////////////////////
355	// Software visible REGISTERS
356	///////////////////////////////
357	sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register
358	sc_signal<uint32_t> r_mmu_mode; // mmu mode register
359	sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low
360	sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight
361	sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address
362	sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address
363	sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type
364	sc_signal<uint32_t> r_mmu_detr; // mmu data error type
365	uint32_t r_mmu_params; // read-only
366	uint32_t r_mmu_release; // read_only
367
368
369	//////////////////////////////
370	// ICACHE FSM REGISTERS
371	//////////////////////////////
372	sc_signal<int> r_icache_fsm; // state register
373	sc_signal<int> r_icache_fsm_save; // return state for coherence op
374	sc_signal<paddr_t> r_icache_vci_paddr; // physical address
375	sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor
376
377	// icache miss handling
378	sc_signal<size_t> r_icache_miss_way; // selected way for cache update
379	sc_signal<size_t> r_icache_miss_set; // selected set for cache update
380	sc_signal<size_t> r_icache_miss_word; // word index ( cache update)
381	sc_signal<bool> r_icache_miss_inval; // coherence request matching a miss
382	sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge
383
384	// coherence request handling
385	sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval
386	sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval
387	sc_signal<size_t> r_icache_cc_word; // word counter for cc update
388	sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing
389
390	// coherence clack handling
391	sc_signal<bool> r_icache_clack_req; // clack request
392	sc_signal<size_t> r_icache_clack_way; // clack way
393	sc_signal<size_t> r_icache_clack_set; // clack set
394
395	// icache flush handling
396	sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush
397
398	// communication between ICACHE FSM and VCI_CMD FSM
399	sc_signal<bool> r_icache_miss_req; // cached read miss
400	sc_signal<bool> r_icache_unc_req; // uncached read miss
401
402	// communication between ICACHE FSM and DCACHE FSM
403	sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache)
404	sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error
405
406	// Filp-Flop in ICACHE FSM for saving the cleanup victim request
407	sc_signal<bool> r_icache_cleanup_victim_req;
408	sc_signal<paddr_t> r_icache_cleanup_victim_nline;
409
410	// communication between ICACHE FSM and CC_SEND FSM
411	sc_signal<bool> r_icache_cc_send_req; // ICACHE cc_send request
412	sc_signal<int> r_icache_cc_send_type; // ICACHE cc_send request type
413	sc_signal<paddr_t> r_icache_cc_send_nline; // ICACHE cc_send nline
414	sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way
415	sc_signal<size_t> r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index
416
417	///////////////////////////////
418	// DCACHE FSM REGISTERS
419	///////////////////////////////
420	sc_signal<int> r_dcache_fsm; // state register
421	sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence op
422	sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op
423	// registers written in P0 stage (used in P1 stage)
424	sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage
425	sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage
426	sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc)
427	sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc)
428	sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc)
429	sc_signal<paddr_t> r_dcache_save_paddr; // physical address
430	sc_signal<bool> r_dcache_save_cacheable; // address cacheable
431	sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache)
432	sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache)
433	sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache)
434	// registers used by the Dirty bit sub-fsm
435	sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address
436	sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache
437	sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache
438
439	// communication between DCACHE FSM and VCI_CMD FSM
440	sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command
441	sc_signal<bool> r_dcache_vci_miss_req; // read miss request
442	sc_signal<bool> r_dcache_vci_unc_req; // uncacheable read request
443	sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable read byte enable
444	sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS
445	sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS
446	sc_signal<uint32_t> r_dcache_vci_cas_new; // new data value for a CAS
447	sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL
448	sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC
449	sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command)
450
451	// register used for XTN inval
452	sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache)
453	sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache)
454
455	// write buffer state extension
456	sc_signal<bool> r_dcache_pending_unc_write; // pending uncacheable write in WBUF
457
458	// handling dcache miss
459	sc_signal<int> r_dcache_miss_type; // depending on the requester
460	sc_signal<size_t> r_dcache_miss_word; // word index for cache update
461	sc_signal<size_t> r_dcache_miss_way; // selected way for cache update
462	sc_signal<size_t> r_dcache_miss_set; // selected set for cache update
463	sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss
464	sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge
465
466	// handling coherence requests
467	sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval
468	sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval
469	sc_signal<size_t> r_dcache_cc_word; // word counter for cc update
470	sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing
471
472	// coherence clack handling
473	sc_signal<bool> r_dcache_clack_req; // clack request
474	sc_signal<size_t> r_dcache_clack_way; // clack way
475	sc_signal<size_t> r_dcache_clack_set; // clack set
476
477	// dcache flush handling
478	sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush
479
480	// ll response handling
481	sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp
482
483	// used by the TLB miss sub-fsm
484	sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss
485	sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true)
486	sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte
487	sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2
488	sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2
489	sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache
490	sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache
491	sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache
492	sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb
493	sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb
494
495	// ITLB and DTLB invalidation
496	sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index
497	sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter
498
499	// communication between DCACHE FSM and ICACHE FSM
500	sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor)
501	sc_signal<int> r_dcache_xtn_opcode; // xtn request type
502
503	// Filp-Flop in DCACHE FSM for saving the cleanup victim request
504	sc_signal<bool> r_dcache_cleanup_victim_req;
505	sc_signal<paddr_t> r_dcache_cleanup_victim_nline;
506
507	// communication between DCACHE FSM and CC_SEND FSM
508	sc_signal<bool> r_dcache_cc_send_req; // DCACHE cc_send request
509	sc_signal<int> r_dcache_cc_send_type; // DCACHE cc_send request type
510	sc_signal<paddr_t> r_dcache_cc_send_nline; // DCACHE cc_send nline
511	sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way
512	sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index
513
514	// special registers for ODCCP/RWT
515	sc_signal<bool> r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt)
516	sc_signal<bool> r_dcache_cleanup_ncc; // Register for cleanup no coherent
517	//sc_signal<bool> r_miss_cleanup_ncc_pending; // Register for cleanup no coherent
518	sc_signal<bool> r_dcache_cleanup_will_contains_data; // Register for cleanup no coherent
519	sc_signal<bool> r_dcache_cleanup_will_ncc; // Register for cleanup no coherent
520	sc_signal<bool> r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode
521	sc_signal<bool> r_dcache_line_no_coherence; // Register for line current in no coherence mode
522	sc_signal<bool> r_dcache_miss_no_coherent; // Register for miss on NCC line
523	sc_signal<bool> r_vci_rsp_read_data_miss_no_coherent; // Read miss rsp on line NCC
524	sc_signal<uint32_t> r_cc_send_cpt_word;
525
526	sc_signal<uint32_t> r_dcache_miss_data_cpt; // Cpt a word to read for sending Cleanup with data (MISS STATE)
527	sc_signal<paddr_t> r_dcache_miss_data_addr; // Addr for read word for sending Cleanup with data (MISS STATE)
528
529	sc_signal<int> r_dcache_xtn_state;
530	sc_signal<paddr_t> r_dcache_xtn_data_addr; // Cpt a word to read for sending Cleanup with data (XTN DC INVAL STATE)
531	sc_signal<uint32_t> r_dcache_xtn_data_cpt; // Addr for read word for sending Cleanup with data (XTN DC INVAL STATE)
532
533	sc_signal<paddr_t> r_dcache_cc_inval_addr; // Cpt a word to read for sending Cleanup with data (CC INVAL STATE)
534	sc_signal<uint32_t> r_dcache_cc_inval_data_cpt; // Addr for read word for sending Cleanup with data (CC INVAL STATE)
535	sc_signal<int> r_dcache_cc_state;
536
537	sc_signal<paddr_t> r_dcache_xtn_flush_addr_data; // Cpt a word to read for sending Cleanup with data (XTN DC FLUSH STATE)
538	sc_signal<uint32_t> r_dcache_xtn_flush_data_cpt; // Addr for read word for sending Cleanup with data (XTN DC FLUSH STATE)
539
540	/STATS DIRTY/
541	bool *dirty_stats;
542	uint32_t m_cpt_words_dirty; // total number of words dirty when we send a cleanup with data
543
544	//////////////
545	GenericFifo<uint32_t> r_cc_send_data_fifo; // Fifo for save data value (before sending cleanup with data)
546	// dcache directory extension
547	///////////////////////////MODIFIED///////////////////////////////////////////////////
548	//bool *r_dcache_in_tlb; // copy exist in dtlb or itlb
549	//bool *r_dcache_contains_ptd; // cache line contains a PTD
550	int *r_dcache_content_state; // content state of one cache line
551	//////////////////////////////////////////////////////////////////////////////////////
552
553	// Physical address extension for data access
554	sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32)
555
556	///////////////////////////////////
557	// VCI_CMD FSM REGISTERS
558	///////////////////////////////////
559	sc_signal<int> r_vci_cmd_fsm;
560	sc_signal<size_t> r_vci_cmd_min; // used for write bursts
561	sc_signal<size_t> r_vci_cmd_max; // used for write bursts
562	sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts
563	sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss
564
565	///////////////////////////////////
566	// VCI_RSP FSM REGISTERS
567	///////////////////////////////////
568	sc_signal<int> r_vci_rsp_fsm;
569	sc_signal<size_t> r_vci_rsp_cpt;
570	sc_signal<bool> r_vci_rsp_ins_error;
571	sc_signal<bool> r_vci_rsp_data_error;
572	GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM
573	GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM
574
575
576	///////////////////////////////////
577	// CC_SEND FSM REGISTER
578	///////////////////////////////////
579	sc_signal<int> r_cc_send_fsm; // state register
580	sc_signal<bool> r_cc_send_last_client; // 0 dcache / 1 icache
581
582	///////////////////////////////////
583	// CC_RECEIVE FSM REGISTER
584	///////////////////////////////////
585	sc_signal<int> r_cc_receive_fsm; // state register
586	sc_signal<bool> r_cc_receive_data_ins; // request to : 0 dcache / 1 icache
587
588	// communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
589	sc_signal<size_t> r_cc_receive_word_idx; // word index
590	GenericFifo<uint32_t> r_cc_receive_updt_fifo_be;
591	GenericFifo<uint32_t> r_cc_receive_updt_fifo_data;
592	GenericFifo<bool> r_cc_receive_updt_fifo_eop;
593
594	// communication between CC_RECEIVE FSM and ICACHE FSM
595	sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request
596	sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request
597	sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way
598	sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set
599	sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index
600	sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address
601
602	// communication between CC_RECEIVE FSM and DCACHE FSM
603	sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request
604	sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request
605	sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way
606	sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set
607	sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index
608	sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address
609
610	///////////////////////////////////
611	// DSPIN CLACK INTERFACE REGISTER
612	///////////////////////////////////
613	sc_signal<bool> r_dspin_clack_req;
614	sc_signal<uint64_t> r_dspin_clack_flit;
615
616	//////////////////////////////////////////////////////////////////
617	// processor, write buffer, caches , TLBs
618	//////////////////////////////////////////////////////////////////
619
620	iss_t r_iss;
621	MultiWriteBuffer<paddr_t> r_wbuf;
622	GenericCache<paddr_t> r_icache;
623	GenericCache<paddr_t> r_dcache;
624	GenericTlb<paddr_t> r_itlb;
625	GenericTlb<paddr_t> r_dtlb;
626
627	//////////////////////////////////////////////////////////////////
628	// llsc registration buffer
629	//////////////////////////////////////////////////////////////////
630
631	sc_signal<paddr_t> r_dcache_llsc_paddr;
632	sc_signal<uint32_t> r_dcache_llsc_key;
633	sc_signal<uint32_t> r_dcache_llsc_count;
634	sc_signal<bool> r_dcache_llsc_valid;
635
636	////////////////////////////////
637	// Activity counters
638	////////////////////////////////
639	uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ
640	uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE
641	uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ
642	uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE
643
644	uint32_t m_cpt_icache_data_read; // ICACHE DATA READ
645	uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE
646	uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ
647	uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE
648
649	uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen
650	uint32_t m_cpt_total_cycles; // total number of cycles
651
652	// Cache activity counters
653	uint32_t m_cpt_data_read; // total number of read data
654	uint32_t m_cpt_data_write; // total number of write data
655	uint32_t m_cpt_data_write_back; // total number of write NCC
656	uint32_t m_cpt_data_cleanup; // total number of flits cleanup data
657	uint32_t m_cpt_data_cleanup_dirty; // total number of cleanup data dirty
658	uint32_t m_cpt_data_sc;
659	uint32_t m_cpt_data_write_miss_ncc; // total number of write NCC miss
660	uint32_t m_cpt_data_miss; // number of read miss
661	uint32_t m_cpt_ins_miss; // number of instruction miss
662	uint32_t m_cpt_unc_read; // number of read uncached
663	uint32_t m_cpt_write_cached; // number of cached write
664	uint32_t m_cpt_ins_read; // number of instruction read
665	uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss
666
667	uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
668	uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss
669	uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read
670	uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss
671
672	uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
673	uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
674	uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions
675	uint32_t m_cpt_write_transaction; // number of VCI write transactions
676	uint32_t m_cpt_icache_unc_transaction;
677
678	uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions
679	uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions
680	uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions
681	uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions
682	uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
683	uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions
684
685	// TLB activity counters
686	uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read
687	uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss
688	uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update
689	uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line
690	uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache
691
692	uint32_t m_cpt_data_tlb_read; // number of data tlb read
693	uint32_t m_cpt_data_tlb_miss; // number of data tlb miss
694	uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update
695	uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty
696	uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache
697	uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line
698	uint32_t m_cpt_tlb_occup_dcache;
699
700	uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss
701	uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss
702	uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc
703	uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc
704	uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
705	uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache
706	uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache
707
708	uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions
709	uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions
710	uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions
711	uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions
712	uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions
713	uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions
714	uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions
715	uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions
716
717	uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions
718	uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions
719	uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions
720	uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions
721	uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions
722	uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions
723	uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
724	uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
725
726	// coherence activity counters
727	uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands
728	uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands
729	uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands
730	uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands
731	uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands
732
733	uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets
734	uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets
735	uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets
736	uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets
737
738	uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets
739	uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets
740
741	uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions
742	uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions
743	uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions
744	uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions
745
746	uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate
747	uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate
748
749	uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate
750	uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate
751
752	// FSM activity counters
753	uint32_t m_cpt_fsm_icache [64];
754	uint32_t m_cpt_fsm_dcache [64];
755	uint32_t m_cpt_fsm_cmd [64];
756	uint32_t m_cpt_fsm_rsp [64];
757	uint32_t m_cpt_fsm_cc_receive [64];
758	uint32_t m_cpt_fsm_cc_send [64];
759
760	uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen
761	bool m_monitor_ok; // used to debug cache output
762	uint32_t m_monitor_base;
763	uint32_t m_monitor_length;
764
765	protected:
766	SC_HAS_PROCESS(VciCcVCacheWrapper);
767
768	public:
769	VciCcVCacheWrapper(
770	sc_module_name name,
771	const int proc_id,
772	const soclib::common::MappingTable &mtd,
773	const soclib::common::IntTab &srcid,
774	const size_t cc_global_id,
775	const size_t itlb_ways,
776	const size_t itlb_sets,
777	const size_t dtlb_ways,
778	const size_t dtlb_sets,
779	const size_t icache_ways,
780	const size_t icache_sets,
781	const size_t icache_words,
782	const size_t dcache_ways,
783	const size_t dcache_sets,
784	const size_t dcache_words,
785	const size_t wbuf_nlines,
786	const size_t wbuf_nwords,
787	const size_t x_width,
788	const size_t y_width,
789	const uint32_t max_frozen_cycles,
790	const uint32_t debug_start_cycle,
791	const bool debug_ok );
792
793	~VciCcVCacheWrapper();
794
795	void print_cpi();
796	void print_stats();
797	void clear_stats();
798	void print_trace(size_t mode = 0);
799	void cache_monitor(paddr_t addr);
800	void start_monitor(paddr_t,paddr_t);
801	void stop_monitor();
802	inline void iss_set_debug_mask(uint v)
803	{
804	r_iss.set_debug_mask(v);
805	}
806
807	private:
808	void transition();
809	void genMoore();
810
811	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
812	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
813	};
814
815	}}
816
817	#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
818
819	// Local Variables:
820	// tab-width: 4
821	// c-basic-offset: 4
822	// c-file-offsets:((innamespace . 0)(inline-open . 0))
823	// indent-tabs-mode: nil
824	// End:
825
826	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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source: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 494

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