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vci_mem_cache.h @ 545

Last change on this file since 545 was 544, checked in by haoliu, 11 years ago
ODCCP merge the components with the version 543 in trunk.
File size: 49.6 KB

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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain.greiner@lip6.fr
28	* eric.guthmuller@polytechnique.edu
29	* cesar.fuguet-tortolero@lip6.fr
30	* alexandre.joannou@lip6.fr
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_H
34	#define SOCLIB_CABA_MEM_CACHE_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40	#include "arithmetics.h"
41	#include "alloc_elems.h"
42	#include "caba_base_module.h"
43	#include "vci_target.h"
44	#include "vci_initiator.h"
45	#include "generic_fifo.h"
46	#include "mapping_table.h"
47	#include "int_tab.h"
48	#include "generic_llsc_global_table.h"
49	#include "mem_cache_directory.h"
50	#include "xram_transaction.h"
51	#include "update_tab.h"
52	#include "dspin_interface.h"
53	#include "dspin_dhccp_param.h"
54
55	#define TRT_ENTRIES 4 // Number of entries in TRT
56	#define UPT_ENTRIES 4 // Number of entries in UPT
57	#define IVT_ENTRIES 4 // Number of entries in IVT
58	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
59
60	namespace soclib { namespace caba {
61
62	using namespace sc_core;
63
64	template<typename vci_param_int,
65	typename vci_param_ext,
66	size_t dspin_in_width,
67	size_t dspin_out_width>
68	class VciMemCache
69	: public soclib::caba::BaseModule
70	{
71	typedef typename vci_param_int::fast_addr_t addr_t;
72	typedef typename sc_dt::sc_uint<64> wide_data_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e
80	{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_WRITE,
84	TGT_CMD_CAS,
85	TGT_CMD_ERROR,
86	TGT_CMD_CONFIG
87	};
88
89	/* States of the TGT_RSP fsm */
90	enum tgt_rsp_fsm_state_e
91	{
92	TGT_RSP_READ_IDLE,
93	TGT_RSP_WRITE_IDLE,
94	TGT_RSP_CAS_IDLE,
95	TGT_RSP_XRAM_IDLE,
96	TGT_RSP_MULTI_ACK_IDLE,
97	TGT_RSP_CLEANUP_IDLE,
98	TGT_RSP_CONFIG_IDLE,
99	TGT_RSP_TGT_CMD_IDLE,
100	TGT_RSP_READ,
101	TGT_RSP_WRITE,
102	TGT_RSP_CAS,
103	TGT_RSP_XRAM,
104	TGT_RSP_MULTI_ACK,
105	TGT_RSP_CLEANUP,
106	TGT_RSP_CONFIG,
107	TGT_RSP_TGT_CMD
108	};
109
110	/* States of the DSPIN_TGT fsm */
111	enum cc_receive_fsm_state_e
112	{
113	CC_RECEIVE_IDLE,
114	CC_RECEIVE_CLEANUP,
115	CC_RECEIVE_CLEANUP_EOP,
116	CC_RECEIVE_MULTI_ACK
117	};
118
119	/* States of the CC_SEND fsm */
120	enum cc_send_fsm_state_e
121	{
122	CC_SEND_XRAM_RSP_IDLE,
123	CC_SEND_WRITE_IDLE,
124	CC_SEND_CAS_IDLE,
125	CC_SEND_CONFIG_IDLE,
126	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
127	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
128	CC_SEND_XRAM_RSP_INVAL_HEADER,
129	CC_SEND_XRAM_RSP_INVAL_NLINE,
130	CC_SEND_WRITE_BRDCAST_HEADER,
131	CC_SEND_WRITE_BRDCAST_NLINE,
132	CC_SEND_WRITE_UPDT_HEADER,
133	CC_SEND_WRITE_UPDT_NLINE,
134	CC_SEND_WRITE_UPDT_DATA,
135	CC_SEND_CAS_BRDCAST_HEADER,
136	CC_SEND_CAS_BRDCAST_NLINE,
137	CC_SEND_CAS_UPDT_HEADER,
138	CC_SEND_CAS_UPDT_NLINE,
139	CC_SEND_CAS_UPDT_DATA,
140	CC_SEND_CAS_UPDT_DATA_HIGH,
141	CC_SEND_CONFIG_INVAL_HEADER,
142	CC_SEND_CONFIG_INVAL_NLINE,
143	CC_SEND_CONFIG_BRDCAST_HEADER,
144	CC_SEND_CONFIG_BRDCAST_NLINE
145	};
146
147	/* States of the MULTI_ACK fsm */
148	enum multi_ack_fsm_state_e
149	{
150	MULTI_ACK_IDLE,
151	MULTI_ACK_UPT_LOCK,
152	MULTI_ACK_UPT_CLEAR,
153	MULTI_ACK_WRITE_RSP
154	};
155
156	/* States of the CONFIG fsm */
157	enum config_fsm_state_e
158	{
159	CONFIG_IDLE,
160	CONFIG_LOOP,
161	CONFIG_WAIT,
162	CONFIG_RSP,
163	CONFIG_DIR_REQ,
164	CONFIG_DIR_ACCESS,
165	CONFIG_IVT_LOCK,
166	CONFIG_BC_SEND,
167	CONFIG_INVAL_SEND,
168	CONFIG_HEAP_REQ,
169	CONFIG_HEAP_SCAN,
170	CONFIG_HEAP_LAST,
171	CONFIG_TRT_LOCK,
172	CONFIG_TRT_SET,
173	CONFIG_PUT_REQ
174	};
175
176	/* States of the READ fsm */
177	enum read_fsm_state_e
178	{
179	READ_IDLE,
180	READ_DIR_REQ,
181	READ_DIR_LOCK,
182	READ_DIR_HIT,
183	READ_HEAP_REQ,
184	READ_HEAP_LOCK,
185	READ_HEAP_WRITE,
186	READ_HEAP_ERASE,
187	READ_HEAP_LAST,
188	READ_RSP,
189	READ_TRT_LOCK,
190	READ_TRT_SET,
191	READ_TRT_REQ
192	};
193
194	/* States of the WRITE fsm */
195	enum write_fsm_state_e
196	{
197	WRITE_IDLE,
198	WRITE_NEXT,
199	WRITE_DIR_REQ,
200	WRITE_DIR_LOCK,
201	WRITE_DIR_HIT,
202	WRITE_UPT_LOCK,
203	WRITE_UPT_HEAP_LOCK,
204	WRITE_UPT_REQ,
205	WRITE_UPT_NEXT,
206	WRITE_UPT_DEC,
207	WRITE_RSP,
208	WRITE_MISS_TRT_LOCK,
209	WRITE_MISS_TRT_DATA,
210	WRITE_MISS_TRT_SET,
211	WRITE_MISS_XRAM_REQ,
212	WRITE_BC_DIR_READ,
213	WRITE_BC_TRT_LOCK,
214	WRITE_BC_IVT_LOCK,
215	WRITE_BC_DIR_INVAL,
216	WRITE_BC_CC_SEND,
217	WRITE_BC_XRAM_REQ,
218	WRITE_WAIT
219	};
220
221	/* States of the IXR_RSP fsm */
222	enum ixr_rsp_fsm_state_e
223	{
224	IXR_RSP_IDLE,
225	IXR_RSP_ACK,
226	IXR_RSP_TRT_ERASE,
227	IXR_RSP_TRT_READ
228	};
229
230	/* States of the XRAM_RSP fsm */
231	enum xram_rsp_fsm_state_e
232	{
233	XRAM_RSP_IDLE,
234	XRAM_RSP_TRT_COPY,
235	XRAM_RSP_TRT_DIRTY,
236	XRAM_RSP_DIR_LOCK,
237	XRAM_RSP_DIR_UPDT,
238	XRAM_RSP_DIR_RSP,
239	XRAM_RSP_IVT_LOCK,
240	XRAM_RSP_INVAL_WAIT,
241	XRAM_RSP_INVAL,
242	XRAM_RSP_WRITE_DIRTY,
243	XRAM_RSP_HEAP_REQ,
244	XRAM_RSP_HEAP_ERASE,
245	XRAM_RSP_HEAP_LAST,
246	XRAM_RSP_ERROR_ERASE,
247	XRAM_RSP_ERROR_RSP
248	};
249
250	/* States of the IXR_CMD fsm */
251	enum ixr_cmd_fsm_state_e
252	{
253	IXR_CMD_READ_IDLE,
254	IXR_CMD_WRITE_IDLE,
255	IXR_CMD_CAS_IDLE,
256	IXR_CMD_XRAM_IDLE,
257	IXR_CMD_CLEANUP_IDLE,
258	IXR_CMD_CONFIG_IDLE,
259	IXR_CMD_READ_TRT,
260	IXR_CMD_WRITE_TRT,
261	IXR_CMD_CAS_TRT,
262	IXR_CMD_XRAM_TRT,
263	IXR_CMD_CLEANUP_TRT,
264	IXR_CMD_CONFIG_TRT,
265	IXR_CMD_READ_SEND,
266	IXR_CMD_WRITE_SEND,
267	IXR_CMD_CAS_SEND,
268	IXR_CMD_XRAM_SEND,
269	IXR_CMD_CLEANUP_DATA_SEND,
270	IXR_CMD_CONFIG_SEND
271	};
272
273	/* States of the CAS fsm */
274	enum cas_fsm_state_e
275	{
276	CAS_IDLE,
277	CAS_DIR_REQ,
278	CAS_DIR_LOCK,
279	CAS_DIR_HIT_READ,
280	CAS_DIR_HIT_COMPARE,
281	CAS_DIR_HIT_WRITE,
282	CAS_UPT_LOCK,
283	CAS_UPT_HEAP_LOCK,
284	CAS_UPT_REQ,
285	CAS_UPT_NEXT,
286	CAS_BC_TRT_LOCK,
287	CAS_BC_IVT_LOCK,
288	CAS_BC_DIR_INVAL,
289	CAS_BC_CC_SEND,
290	CAS_BC_XRAM_REQ,
291	CAS_RSP_FAIL,
292	CAS_RSP_SUCCESS,
293	CAS_MISS_TRT_LOCK,
294	CAS_MISS_TRT_SET,
295	CAS_MISS_XRAM_REQ,
296	CAS_WAIT
297	};
298
299	/* States of the CLEANUP fsm */
300	enum cleanup_fsm_state_e
301	{
302	CLEANUP_IDLE,
303	CLEANUP_GET_NLINE,
304	CLEANUP_GET_DATA,
305	CLEANUP_DIR_REQ,
306	CLEANUP_DIR_LOCK,
307	CLEANUP_DIR_WRITE,
308	CLEANUP_HEAP_REQ,
309	CLEANUP_HEAP_LOCK,
310	CLEANUP_HEAP_SEARCH,
311	CLEANUP_HEAP_CLEAN,
312	CLEANUP_HEAP_FREE,
313	CLEANUP_IVT_LOCK,
314	CLEANUP_IVT_DECREMENT,
315	CLEANUP_IVT_CLEAR,
316	CLEANUP_WRITE_RSP,
317	CLEANUP_IXR_REQ,
318	CLEANUP_WAIT,
319	CLEANUP_SEND_CLACK
320	};
321
322	/* States of the ALLOC_DIR fsm */
323	enum alloc_dir_fsm_state_e
324	{
325	ALLOC_DIR_RESET,
326	ALLOC_DIR_READ,
327	ALLOC_DIR_WRITE,
328	ALLOC_DIR_CAS,
329	ALLOC_DIR_CLEANUP,
330	ALLOC_DIR_XRAM_RSP,
331	ALLOC_DIR_CONFIG
332	};
333
334	/* States of the ALLOC_TRT fsm */
335	enum alloc_trt_fsm_state_e
336	{
337	ALLOC_TRT_READ,
338	ALLOC_TRT_WRITE,
339	ALLOC_TRT_CAS,
340	ALLOC_TRT_XRAM_RSP,
341	ALLOC_TRT_IXR_RSP,
342	ALLOC_TRT_CLEANUP,
343	ALLOC_TRT_IXR_CMD,
344	ALLOC_TRT_CONFIG
345	};
346
347	/* States of the ALLOC_UPT fsm */
348	enum alloc_upt_fsm_state_e
349	{
350	ALLOC_UPT_WRITE,
351	ALLOC_UPT_CAS,
352	ALLOC_UPT_MULTI_ACK
353	};
354
355	/* States of the ALLOC_IVT fsm */
356	enum alloc_ivt_fsm_state_e
357	{
358	ALLOC_IVT_WRITE,
359	ALLOC_IVT_XRAM_RSP,
360	ALLOC_IVT_CLEANUP,
361	ALLOC_IVT_CAS,
362	ALLOC_IVT_CONFIG
363	};
364
365	/* States of the ALLOC_HEAP fsm */
366	enum alloc_heap_fsm_state_e
367	{
368	ALLOC_HEAP_RESET,
369	ALLOC_HEAP_READ,
370	ALLOC_HEAP_WRITE,
371	ALLOC_HEAP_CAS,
372	ALLOC_HEAP_CLEANUP,
373	ALLOC_HEAP_XRAM_RSP,
374	ALLOC_HEAP_CONFIG
375	};
376
377	/* transaction type, pktid field */
378	enum transaction_type_e
379	{
380	// b3 unused
381	// b2 READ / NOT READ
382	// Si READ
383	// b1 DATA / INS
384	// b0 UNC / MISS
385	// Si NOT READ
386	// b1 accÃšs table llsc type SW / other
387	// b2 WRITE/CAS/LL/SC
388	TYPE_READ_DATA_UNC = 0x0,
389	TYPE_READ_DATA_MISS = 0x1,
390	TYPE_READ_INS_UNC = 0x2,
391	TYPE_READ_INS_MISS = 0x3,
392	TYPE_WRITE = 0x4,
393	TYPE_CAS = 0x5,
394	TYPE_LL = 0x6,
395	TYPE_SC = 0x7
396	};
397
398	/* SC return values */
399	enum sc_status_type_e
400	{
401	SC_SUCCESS = 0x00000000,
402	SC_FAIL = 0x00000001
403	};
404
405	// debug variables
406	bool m_debug;
407	bool m_debug_previous_valid;
408	size_t m_debug_previous_count;
409	bool m_debug_previous_dirty;
410	data_t * m_debug_previous_data;
411	data_t * m_debug_data;
412
413	// instrumentation counters
414	uint32_t m_cpt_cycles; // Counter of cycles
415
416	// Counters accessible in software (not yet but eventually)
417	uint32_t m_cpt_read_local; // Number of local READ transactions
418	uint32_t m_cpt_read_remote; // number of remote READ transactions
419	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs
420
421	uint32_t m_cpt_write_local; // Number of local WRITE transactions
422	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
423	uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs
424	uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
425	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
426
427	uint32_t m_cpt_ll_local; // Number of local LL transactions
428	uint32_t m_cpt_ll_remote; // number of remote LL transactions
429	uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs
430
431	uint32_t m_cpt_sc_local; // Number of local SC transactions
432	uint32_t m_cpt_sc_remote; // number of remote SC transactions
433	uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs
434
435	uint32_t m_cpt_cas_local; // Number of local SC transactions
436	uint32_t m_cpt_cas_remote; // number of remote SC transactions
437	uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs
438
439	uint32_t m_cpt_update; // Number of requests causing an UPDATE
440	uint32_t m_cpt_update_local; // Number of local UPDATE transactions
441	uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions
442	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT
443
444	uint32_t m_cpt_m_inval; // Number of requests causing M_INV
445	uint32_t m_cpt_m_inval_local; // Number of local M_INV transactions
446	uint32_t m_cpt_m_inval_remote; // Number of remote M_INV transactions
447	uint32_t m_cpt_m_inval_cost; // Number of (flits * distance) for M_INV
448
449	uint32_t m_cpt_br_inval; // Number of BROADCAST INVAL
450
451	uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions
452	uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions
453	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs
454
455	// Counters not accessible by software
456	uint32_t m_cpt_read_miss; // Number of MISS READ
457	uint32_t m_cpt_write_miss; // Number of MISS WRITE
458	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
459	uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write
460
461	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
462	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
463	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
464	uint32_t m_cpt_inval; // Number of INVAL transactions
465	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
466	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
467	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
468	uint32_t m_cpt_cleanup_data; // Number of CLEANUP WITH DATA transactions
469	uint32_t m_cpt_ll; // Number of LL transactions
470	uint32_t m_cpt_sc; // Number of SC transactions
471	uint32_t m_cpt_cas; // Number of CAS transactions
472	uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK
473	uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK
474	uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK
475	uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK
476	uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK
477	uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK
478	uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK
479	uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK
480	uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK
481	uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK
482
483	uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused
484	uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used
485	uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used
486	uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used
487	uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
488	uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used
489
490	uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK
491	uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK
492	uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK
493	uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK
494	uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK
495
496	uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK
497	uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK
498	uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK
499	uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK
500	uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK
501
502	uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used
503	uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used
504	uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used
505	uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used
506	uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used
507
508	uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused
509
510	uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK
511	uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK
512	uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK
513	uint32_t m_cpt_cleanup_fsm_upt_lock; // wait UPT LOCK
514	uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK
515
516	uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK
517	uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK
518	uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK
519	uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK
520	uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK
521
522	uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used
523	uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used
524	uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used
525	uint32_t m_cpt_cleanup_fsm_upt_used; // NB cycles UPT LOCK used
526	uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used
527
528	uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused
529
530	uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK
531	uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK
532	uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK
533	uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK
534	uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
535
536	uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK
537	uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK
538	uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK
539	uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK
540	uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
541
542	uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used
543	uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used
544	uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used
545	uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used
546	uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
547
548	uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused
549
550	uint32_t m_cpt_update_flits; // Number of flits for UPDATEs
551	uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs
552
553	uint32_t m_cpt_get;
554	uint32_t m_cpt_put;
555
556	size_t m_prev_count;
557
558	protected:
559
560	SC_HAS_PROCESS(VciMemCache);
561
562	public:
563	sc_in<bool> p_clk;
564	sc_in<bool> p_resetn;
565	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
566	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
567	soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m;
568	soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
569	soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
570
571	#if MONITOR_MEMCACHE_FSM == 1
572	sc_out<int> p_read_fsm;
573	sc_out<int> p_write_fsm;
574	sc_out<int> p_xram_rsp_fsm;
575	sc_out<int> p_cas_fsm;
576	sc_out<int> p_cleanup_fsm;
577	sc_out<int> p_config_fsm;
578	sc_out<int> p_alloc_heap_fsm;
579	sc_out<int> p_alloc_dir_fsm;
580	sc_out<int> p_alloc_trt_fsm;
581	sc_out<int> p_alloc_upt_fsm;
582	sc_out<int> p_alloc_ivt_fsm;
583	sc_out<int> p_tgt_cmd_fsm;
584	sc_out<int> p_tgt_rsp_fsm;
585	sc_out<int> p_ixr_cmd_fsm;
586	sc_out<int> p_ixr_rsp_fsm;
587	sc_out<int> p_cc_send_fsm;
588	sc_out<int> p_cc_receive_fsm;
589	sc_out<int> p_multi_ack_fsm;
590	#endif
591
592	VciMemCache(
593	sc_module_name name, // Instance Name
594	const soclib::common::MappingTable &mtp, // Mapping table INT network
595	const soclib::common::MappingTable &mtx, // Mapping table RAM network
596	const soclib::common::IntTab &srcid_x, // global index RAM network
597	const soclib::common::IntTab &tgtid_d, // global index INT network
598	const size_t cc_global_id, // global index CC network
599	const size_t x_width, // X width in platform
600	const size_t y_width, // Y width in platform
601	const size_t nways, // Number of ways per set
602	const size_t nsets, // Number of sets
603	const size_t nwords, // Number of words per line
604	const size_t max_copies, // max number of copies
605	const size_t heap_size=HEAP_ENTRIES,
606	const size_t trt_lines=TRT_ENTRIES,
607	const size_t upt_lines=UPT_ENTRIES,
608	const size_t ivt_lines=IVT_ENTRIES,
609	const size_t debug_start_cycle=0,
610	const bool debug_ok=false );
611
612	~VciMemCache();
613
614	void print_stats(bool activity_counters, bool stats);
615	void print_trace();
616	void cache_monitor(addr_t addr);
617	void start_monitor(addr_t addr, addr_t length);
618	void stop_monitor();
619
620	private:
621
622	void transition();
623	void genMoore();
624	void check_monitor(addr_t addr, data_t data, bool read);
625	uint32_t req_distance(uint32_t req_srcid);
626	bool is_local_req(uint32_t req_srcid);
627
628	// Component attributes
629	std::list<soclib::common::Segment> m_seglist; // segments allocated
630	size_t m_nseg; // number of segments
631	soclib::common::Segment **m_seg; // array of segments pointers
632	size_t m_seg_config; // config segment index
633	const size_t m_srcid_x; // global index on RAM network
634	const size_t m_initiators; // Number of initiators
635	const size_t m_heap_size; // Size of the heap
636	const size_t m_ways; // Number of ways in a set
637	const size_t m_sets; // Number of cache sets
638	const size_t m_words; // Number of words in a line
639	const size_t m_cc_global_id; // global_index on cc network
640	const size_t m_xwidth; // number of x bits in platform
641	const size_t m_ywidth; // number of y bits in platform
642	size_t m_debug_start_cycle;
643	bool m_debug_ok;
644	uint32_t m_trt_lines;
645	TransactionTab m_trt; // xram transaction table
646	uint32_t m_upt_lines;
647	UpdateTab m_upt; // pending update
648	UpdateTab m_ivt; // pending invalidate
649	CacheDirectory m_cache_directory; // data cache directory
650	CacheData m_cache_data; // data array[set][way][word]
651	HeapDirectory m_heap; // heap for copies
652	size_t m_max_copies; // max number of copies in heap
653	GenericLLSCGlobalTable
654	< 32 , // number of slots
655	4096, // number of processors in the system
656	8000, // registration life (# of LL operations)
657	addr_t > m_llsc_table; // ll/sc registration table
658
659	// adress masks
660	const soclib::common::AddressMaskingTable<addr_t> m_x;
661	const soclib::common::AddressMaskingTable<addr_t> m_y;
662	const soclib::common::AddressMaskingTable<addr_t> m_z;
663	const soclib::common::AddressMaskingTable<addr_t> m_nline;
664
665	// broadcast address
666	uint32_t m_broadcast_boundaries;
667
668	// Fifo between TGT_CMD fsm and READ fsm
669	GenericFifo<addr_t> m_cmd_read_addr_fifo;
670	GenericFifo<size_t> m_cmd_read_length_fifo;
671	GenericFifo<size_t> m_cmd_read_srcid_fifo;
672	GenericFifo<size_t> m_cmd_read_trdid_fifo;
673	GenericFifo<size_t> m_cmd_read_pktid_fifo;
674
675	// Fifo between TGT_CMD fsm and WRITE fsm
676	GenericFifo<addr_t> m_cmd_write_addr_fifo;
677	GenericFifo<bool> m_cmd_write_eop_fifo;
678	GenericFifo<size_t> m_cmd_write_srcid_fifo;
679	GenericFifo<size_t> m_cmd_write_trdid_fifo;
680	GenericFifo<size_t> m_cmd_write_pktid_fifo;
681	GenericFifo<data_t> m_cmd_write_data_fifo;
682	GenericFifo<be_t> m_cmd_write_be_fifo;
683
684	// Fifo between TGT_CMD fsm and CAS fsm
685	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
686	GenericFifo<bool> m_cmd_cas_eop_fifo;
687	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
688	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
689	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
690	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
691
692	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
693	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
694
695	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
696	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
697
698	// Buffer between TGT_CMD fsm and TGT_RSP fsm
699	// (segmentation violation response request)
700	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
701
702	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
703	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
704	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
705	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
706	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
707
708	sc_signal<addr_t> r_tgt_cmd_config_addr;
709	sc_signal<size_t> r_tgt_cmd_config_cmd;
710
711	//////////////////////////////////////////////////
712	// Registers controlled by the TGT_CMD fsm
713	//////////////////////////////////////////////////
714
715	sc_signal<int> r_tgt_cmd_fsm;
716
717	///////////////////////////////////////////////////////
718	// Registers controlled by the CONFIG fsm
719	///////////////////////////////////////////////////////
720
721	sc_signal<int> r_config_fsm; // FSM state
722	sc_signal<bool> r_config_lock; // lock protecting exclusive access
723	sc_signal<int> r_config_cmd; // config request type
724	sc_signal<addr_t> r_config_address; // target buffer physical address
725	sc_signal<size_t> r_config_srcid; // config request srcid
726	sc_signal<size_t> r_config_trdid; // config request trdid
727	sc_signal<size_t> r_config_pktid; // config request pktid
728	sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled
729	sc_signal<size_t> r_config_rsp_lines; // number of lines not completed
730	sc_signal<size_t> r_config_dir_way; // DIR: selected way
731	sc_signal<bool> r_config_dir_lock; // DIR: locked entry
732	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
733	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast)
734	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
735	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
736	sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP
737	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
738	sc_signal<size_t> r_config_trt_index; // selected entry in TRT
739	sc_signal<size_t> r_config_ivt_index; // selected entry in IVT
740
741	// Buffer between CONFIG fsm and IXR_CMD fsm
742	sc_signal<bool> r_config_to_ixr_cmd_req; // valid request
743	sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
744
745	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
746	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
747	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
748	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
749	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
750	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
751
752	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
753	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
754	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
755	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
756	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
757	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
758	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
759
760	///////////////////////////////////////////////////////
761	// Registers controlled by the READ fsm
762	///////////////////////////////////////////////////////
763
764	sc_signal<int> r_read_fsm; // FSM state
765	sc_signal<size_t> r_read_copy; // Srcid of the first copy
766	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
767	sc_signal<bool> r_read_copy_inst; // Type of the first copy
768	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
769	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
770	sc_signal<bool> r_read_lock; // lock bit (in directory)
771	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
772	sc_signal<size_t> r_read_count; // number of copies
773	sc_signal<size_t> r_read_ptr; // pointer to the heap
774	sc_signal<data_t> * r_read_data; // data (one cache line)
775	sc_signal<size_t> r_read_way; // associative way (in cache)
776	sc_signal<size_t> r_read_trt_index; // Transaction Table index
777	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
778	sc_signal<bool> r_read_last_free; // Last free entry
779	sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table
780
781	// Buffer between READ fsm and IXR_CMD fsm
782	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
783	sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index
784
785	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
786	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
787	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
788	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
789	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
790	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
791	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
792	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
793	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
794
795	///////////////////////////////////////////////////////////////
796	// Registers controlled by the WRITE fsm
797	///////////////////////////////////////////////////////////////
798
799	sc_signal<int> r_write_fsm; // FSM state
800	sc_signal<addr_t> r_write_address; // first word address
801	sc_signal<size_t> r_write_word_index; // first word index in line
802	sc_signal<size_t> r_write_word_count; // number of words in line
803	sc_signal<size_t> r_write_srcid; // transaction srcid
804	sc_signal<size_t> r_write_trdid; // transaction trdid
805	sc_signal<size_t> r_write_pktid; // transaction pktid
806	sc_signal<data_t> * r_write_data; // data (one cache line)
807	sc_signal<be_t> * r_write_be; // one byte enable per word
808	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
809	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
810	sc_signal<bool> r_write_lock; // lock bit (in directory)
811	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
812	sc_signal<size_t> r_write_copy; // first owner of the line
813	sc_signal<size_t> r_write_copy_cache; // first owner of the line
814	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
815	sc_signal<size_t> r_write_count; // number of copies
816	sc_signal<size_t> r_write_ptr; // pointer to the heap
817	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
818	sc_signal<bool> r_write_to_dec; // need to decrement update counter
819	sc_signal<size_t> r_write_way; // way of the line
820	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
821	sc_signal<size_t> r_write_upt_index; // index in Update Table
822	sc_signal<bool> r_write_sc_fail; // sc command failed
823	sc_signal<data_t> r_write_sc_key; // sc command key
824	sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer
825
826	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
827	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
828	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
829	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
830	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
831	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
832
833	// Buffer between WRITE fsm and IXR_CMD fsm
834	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
835	sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index
836
837	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
838	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
839	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
840	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
841	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
842	sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line)
843	sc_signal<be_t> * r_write_to_cc_send_be; // word enable
844	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
845	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
846	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
847	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
848
849	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
850	sc_signal<bool> r_write_to_multi_ack_req; // valid request
851	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
852
853	/////////////////////////////////////////////////////////
854	// Registers controlled by MULTI_ACK fsm
855	//////////////////////////////////////////////////////////
856
857	sc_signal<int> r_multi_ack_fsm; // FSM state
858	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
859	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
860	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
861	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
862	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
863
864	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
865	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
866	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
867	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
868	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
869
870	///////////////////////////////////////////////////////
871	// Registers controlled by CLEANUP fsm
872	///////////////////////////////////////////////////////
873
874	sc_signal<int> r_cleanup_fsm; // FSM state
875	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
876	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
877	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
878	sc_signal<addr_t> r_cleanup_nline; // cache line index
879
880
881	sc_signal<copy_t> r_cleanup_copy; // first copy
882	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
883	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
884	sc_signal<copy_t> r_cleanup_count; // number of copies
885	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
886	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
887	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
888	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
889	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
890	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
891	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
892	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
893	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
894	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
895	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
896
897	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp
898	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
899	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
900
901	sc_signal<bool> r_cleanup_need_rsp; // write response required
902	sc_signal<bool> r_cleanup_need_ack; // config acknowledge required
903
904	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
905
906	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
907	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
908	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
909	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
910	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
911
912	///////////////////////////////////////////////////////
913	// Registers controlled by CAS fsm
914	///////////////////////////////////////////////////////
915
916	sc_signal<int> r_cas_fsm; // FSM state
917	sc_signal<data_t> r_cas_wdata; // write data word
918	sc_signal<data_t> * r_cas_rdata; // read data word
919	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
920	sc_signal<size_t> r_cas_cpt; // size of command
921	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
922	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
923	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
924	sc_signal<size_t> r_cas_count; // number of copies
925	sc_signal<size_t> r_cas_ptr; // pointer to the heap
926	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
927	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
928	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
929	sc_signal<size_t> r_cas_way; // way in directory
930	sc_signal<size_t> r_cas_set; // set in directory
931	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
932	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
933	sc_signal<size_t> r_cas_upt_index; // Update Table index
934	sc_signal<data_t> * r_cas_data; // cache line data
935
936	// Buffer between CAS fsm and IXR_CMD fsm
937	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
938	sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index
939
940	// Buffer between CAS fsm and TGT_RSP fsm
941	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
942	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
943	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
944	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
945	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
946
947	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
948	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
949	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
950	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
951	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
952	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
953	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
954	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
955	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
956	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
957	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
958
959	////////////////////////////////////////////////////
960	// Registers controlled by the IXR_RSP fsm
961	////////////////////////////////////////////////////
962
963	sc_signal<int> r_ixr_rsp_fsm; // FSM state
964	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
965	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
966
967	// Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM)
968	sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit
969
970	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
971	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry
972	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_no_coherent; // A xram response is ready and no coherent (ODCCP)
973
974	////////////////////////////////////////////////////
975	// Registers controlled by the XRAM_RSP fsm
976	////////////////////////////////////////////////////
977
978	sc_signal<int> r_xram_rsp_fsm; // FSM state
979	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
980	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
981	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
982	sc_signal<bool> r_xram_rsp_victim_coherent; // victim line coherent
983	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
984	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
985	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
986	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
987	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
988	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
989	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
990	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
991	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
992	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
993	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
994	sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index
995	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
996
997	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
998	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
999	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
1000	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
1001	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
1002	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
1003	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
1004	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
1005	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1006	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1007
1008	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1009	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
1010	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
1011	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
1012	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
1013	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
1014	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
1015
1016	// Buffer between XRAM_RSP fsm and IXR_CMD fsm
1017	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
1018	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index
1019
1020	////////////////////////////////////////////////////
1021	// Registers controlled by the IXR_CMD fsm
1022	////////////////////////////////////////////////////
1023
1024	sc_signal<int> r_ixr_cmd_fsm;
1025	sc_signal<size_t> r_ixr_cmd_word; // word index for a put
1026	sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value
1027	sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM
1028	sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
1029	sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET)
1030
1031	////////////////////////////////////////////////////
1032	// Registers controlled by TGT_RSP fsm
1033	////////////////////////////////////////////////////
1034
1035	sc_signal<int> r_tgt_rsp_fsm;
1036	sc_signal<size_t> r_tgt_rsp_cpt;
1037	sc_signal<bool> r_tgt_rsp_key_sent;
1038
1039	////////////////////////////////////////////////////
1040	// Registers controlled by CC_SEND fsm
1041	////////////////////////////////////////////////////
1042
1043	sc_signal<int> r_cc_send_fsm;
1044	sc_signal<size_t> r_cc_send_cpt;
1045	sc_signal<bool> r_cc_send_inst;
1046
1047	////////////////////////////////////////////////////
1048	// Registers controlled by CC_RECEIVE fsm
1049	////////////////////////////////////////////////////
1050
1051	sc_signal<int> r_cc_receive_fsm;
1052
1053	////////////////////////////////////////////////////
1054	// Registers controlled by ALLOC_DIR fsm
1055	////////////////////////////////////////////////////
1056
1057	sc_signal<int> r_alloc_dir_fsm;
1058	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1059
1060	////////////////////////////////////////////////////
1061	// Registers controlled by ALLOC_TRT fsm
1062	////////////////////////////////////////////////////
1063
1064	sc_signal<int> r_alloc_trt_fsm;
1065
1066	////////////////////////////////////////////////////
1067	// Registers controlled by ALLOC_UPT fsm
1068	////////////////////////////////////////////////////
1069
1070	sc_signal<int> r_alloc_upt_fsm;
1071
1072	////////////////////////////////////////////////////
1073	// Registers controlled by ALLOC_IVT fsm
1074	////////////////////////////////////////////////////
1075
1076	sc_signal<int> r_alloc_ivt_fsm;
1077
1078	////////////////////////////////////////////////////
1079	// Registers controlled by ALLOC_HEAP fsm
1080	////////////////////////////////////////////////////
1081
1082	sc_signal<int> r_alloc_heap_fsm;
1083	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1084
1085
1086	////////////////////////////////////////////////////
1087	// REGISTERS FOR ODCCP
1088	////////////////////////////////////////////////////
1089
1090	sc_signal<uint32_t> r_cleanup_data_index;
1091	sc_signal<uint32_t> r_cleanup_trdid;
1092	sc_signal<uint32_t> r_cleanup_pktid;
1093	sc_signal<data_t> *r_cleanup_data; // buffer for saving data from cleanup
1094	sc_signal<data_t> *r_ixr_cmd_data; // buffer for saving data from cleanup
1095	sc_signal<bool> r_cleanup_contains_data;
1096	sc_signal<bool> r_cleanup_ncc;
1097
1098	sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1099
1100	sc_signal<bool> r_cleanup_to_ixr_cmd_req;
1101	sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
1102	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid;
1103	sc_signal<bool> r_cleanup_to_ixr_cmd_l1_dirty_ncc; // this cleanup was dirty in L1
1104	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index;
1105	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid;
1106	sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
1107	}; // end class VciMemCache
1108
1109	}}
1110
1111	#endif
1112
1113	// Local Variables:
1114	// tab-width: 2
1115	// c-basic-offset: 2
1116	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1117	// indent-tabs-mode: nil
1118	// End:
1119
1120	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1121

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source: branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 545

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