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source: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 477

Last change on this file since 477 was 477, checked in by lgarcia, 12 years ago
Reintroducing RWT branch merging the last modifications of the trunk (CLACK channel) WARNING: bugs remaining (with 1c16p and small caches (L2:1616; L1:44))
File size: 49.8 KB

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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	* cesar.fuguet-tortolero@lip6.fr
29	* alexandre.joannou@lip6.fr
30	*/
31
32	#ifndef SOCLIB_CABA_MEM_CACHE_H
33	#define SOCLIB_CABA_MEM_CACHE_H
34
35	#include <inttypes.h>
36	#include <systemc>
37	#include <list>
38	#include <cassert>
39	#include "arithmetics.h"
40	#include "alloc_elems.h"
41	#include "caba_base_module.h"
42	#include "vci_target.h"
43	#include "vci_initiator.h"
44	#include "generic_fifo.h"
45	#include "mapping_table.h"
46	#include "int_tab.h"
47	#include "generic_llsc_global_table.h"
48	#include "mem_cache_directory.h"
49	#include "xram_transaction.h"
50	#include "update_tab.h"
51	#include "dspin_interface.h"
52	#include "dspin_dhccp_param.h"
53
54	#define TRT_ENTRIES 4 // Number of entries in TRT
55	#define UPT_ENTRIES 4 // Number of entries in UPT
56	#define IVT_ENTRIES 4 // Number of entries in IVT
57	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
58
59	namespace soclib { namespace caba {
60
61	using namespace sc_core;
62
63	template<typename vci_param_int,
64	typename vci_param_ext,
65	size_t dspin_in_width,
66	size_t dspin_out_width>
67	class VciMemCache
68	: public soclib::caba::BaseModule
69	{
70	typedef typename vci_param_int::fast_addr_t addr_t;
71	typedef typename sc_dt::sc_uint<64> wide_data_t;
72	typedef uint32_t data_t;
73	typedef uint32_t tag_t;
74	typedef uint32_t be_t;
75	typedef uint32_t copy_t;
76
77	/* States of the TGT_CMD fsm */
78	enum tgt_cmd_fsm_state_e
79	{
80	TGT_CMD_IDLE,
81	TGT_CMD_ERROR,
82	TGT_CMD_READ,
83	TGT_CMD_WRITE,
84	TGT_CMD_CAS,
85	TGT_CMD_CONFIG
86	};
87
88	/* States of the TGT_RSP fsm */
89	enum tgt_rsp_fsm_state_e
90	{
91	TGT_RSP_CONFIG_IDLE,
92	TGT_RSP_TGT_CMD_IDLE,
93	TGT_RSP_READ_IDLE,
94	TGT_RSP_WRITE_IDLE,
95	TGT_RSP_CAS_IDLE,
96	TGT_RSP_XRAM_IDLE,
97	TGT_RSP_MULTI_ACK_IDLE,
98	TGT_RSP_CLEANUP_IDLE,
99	TGT_RSP_CONFIG,
100	TGT_RSP_TGT_CMD,
101	TGT_RSP_READ,
102	TGT_RSP_WRITE,
103	TGT_RSP_CAS,
104	TGT_RSP_XRAM,
105	TGT_RSP_MULTI_ACK,
106	TGT_RSP_CLEANUP
107	};
108
109	/* States of the DSPIN_TGT fsm */
110	enum cc_receive_fsm_state_e
111	{
112	CC_RECEIVE_IDLE,
113	CC_RECEIVE_CLEANUP,
114	CC_RECEIVE_CLEANUP_EOP,
115	CC_RECEIVE_MULTI_ACK
116	};
117
118	/* States of the CC_SEND fsm */
119	enum cc_send_fsm_state_e
120	{
121	CC_SEND_CONFIG_IDLE,
122	CC_SEND_XRAM_RSP_IDLE,
123	CC_SEND_WRITE_IDLE,
124	CC_SEND_CAS_IDLE,
125	CC_SEND_CONFIG_INVAL_HEADER,
126	CC_SEND_CONFIG_INVAL_NLINE,
127	CC_SEND_CONFIG_BRDCAST_HEADER,
128	CC_SEND_CONFIG_BRDCAST_NLINE,
129	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
130	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
131	CC_SEND_XRAM_RSP_INVAL_HEADER,
132	CC_SEND_XRAM_RSP_INVAL_NLINE,
133	CC_SEND_READ_NCC_INVAL_HEADER,
134	CC_SEND_READ_NCC_INVAL_NLINE,
135	CC_SEND_WRITE_NCC_INVAL_HEADER,
136	CC_SEND_WRITE_NCC_INVAL_NLINE,
137	CC_SEND_WRITE_BRDCAST_HEADER,
138	CC_SEND_WRITE_BRDCAST_NLINE,
139	CC_SEND_WRITE_UPDT_HEADER,
140	CC_SEND_WRITE_UPDT_NLINE,
141	CC_SEND_WRITE_UPDT_DATA,
142	CC_SEND_CAS_BRDCAST_HEADER,
143	CC_SEND_CAS_BRDCAST_NLINE,
144	CC_SEND_CAS_UPDT_HEADER,
145	CC_SEND_CAS_UPDT_NLINE,
146	CC_SEND_CAS_UPDT_DATA,
147	CC_SEND_CAS_UPDT_DATA_HIGH
148	};
149
150	/* States of the MULTI_ACK fsm */
151	enum multi_ack_fsm_state_e
152	{
153	MULTI_ACK_IDLE,
154	MULTI_ACK_UPT_LOCK,
155	MULTI_ACK_UPT_CLEAR,
156	MULTI_ACK_WRITE_RSP,
157	MULTI_ACK_CONFIG_ACK
158	};
159
160	/* States of the CONFIG fsm */
161	enum config_fsm_state_e
162	{
163	CONFIG_IDLE,
164	CONFIG_LOOP,
165	CONFIG_RSP,
166	CONFIG_DIR_REQ,
167	CONFIG_DIR_ACCESS,
168	CONFIG_DIR_IVT_LOCK,
169	CONFIG_BC_SEND,
170	CONFIG_BC_WAIT,
171	CONFIG_INV_SEND,
172	CONFIG_HEAP_REQ,
173	CONFIG_HEAP_SCAN,
174	CONFIG_HEAP_LAST,
175	CONFIG_INV_WAIT
176	};
177
178	/* States of the READ fsm */
179	enum read_fsm_state_e
180	{
181	READ_IDLE,
182	READ_DIR_REQ,
183	READ_DIR_LOCK,
184	READ_IVT_LOCK,
185	READ_WAIT,
186	READ_DIR_HIT,
187	READ_HEAP_REQ,
188	READ_HEAP_LOCK,
189	READ_HEAP_WRITE,
190	READ_HEAP_ERASE,
191	READ_HEAP_LAST,
192	READ_RSP,
193	READ_TRT_LOCK,
194	READ_TRT_SET,
195	READ_TRT_REQ
196	};
197
198	/* States of the WRITE fsm */
199	enum write_fsm_state_e
200	{
201	WRITE_IDLE,
202	WRITE_NEXT,
203	WRITE_DIR_REQ,
204	WRITE_DIR_LOCK,
205	WRITE_IVT_LOCK_HIT_WB,
206	WRITE_DIR_READ,
207	WRITE_DIR_HIT,
208	WRITE_UPT_LOCK,
209	WRITE_UPT_HEAP_LOCK,
210	WRITE_UPT_REQ,
211	WRITE_UPT_NEXT,
212	WRITE_UPT_DEC,
213	WRITE_RSP,
214	WRITE_MISS_IVT_LOCK,
215	WRITE_MISS_TRT_LOCK,
216	WRITE_MISS_TRT_DATA,
217	WRITE_MISS_TRT_SET,
218	WRITE_MISS_XRAM_REQ,
219	WRITE_BC_TRT_LOCK,
220	WRITE_BC_IVT_LOCK,
221	WRITE_BC_DIR_INVAL,
222	WRITE_BC_CC_SEND,
223	WRITE_BC_XRAM_REQ,
224	WRITE_WAIT
225	};
226
227	/* States of the IXR_RSP fsm */
228	enum ixr_rsp_fsm_state_e
229	{
230	IXR_RSP_IDLE,
231	IXR_RSP_ACK,
232	IXR_RSP_TRT_ERASE,
233	IXR_RSP_TRT_READ
234	};
235
236	/* States of the XRAM_RSP fsm */
237	enum xram_rsp_fsm_state_e
238	{
239	XRAM_RSP_IDLE,
240	XRAM_RSP_TRT_COPY,
241	XRAM_RSP_TRT_DIRTY,
242	XRAM_RSP_DIR_LOCK,
243	XRAM_RSP_DIR_UPDT,
244	XRAM_RSP_DIR_RSP,
245	XRAM_RSP_INVAL_LOCK,
246	XRAM_RSP_INVAL_WAIT,
247	XRAM_RSP_INVAL,
248	XRAM_RSP_WRITE_DIRTY,
249	XRAM_RSP_HEAP_REQ,
250	XRAM_RSP_HEAP_ERASE,
251	XRAM_RSP_HEAP_LAST,
252	XRAM_RSP_ERROR_ERASE,
253	XRAM_RSP_ERROR_RSP
254	};
255
256	/* States of the IXR_CMD fsm */
257	enum ixr_cmd_fsm_state_e
258	{
259	IXR_CMD_READ_IDLE,
260	IXR_CMD_WRITE_IDLE,
261	IXR_CMD_CAS_IDLE,
262	IXR_CMD_XRAM_IDLE,
263	IXR_CMD_CLEANUP_IDLE,
264	IXR_CMD_READ,
265	IXR_CMD_WRITE,
266	IXR_CMD_CAS,
267	IXR_CMD_XRAM,
268	IXR_CMD_CLEANUP_DATA
269	};
270
271	/* States of the CAS fsm */
272	enum cas_fsm_state_e
273	{
274	CAS_IDLE,
275	CAS_DIR_REQ,
276	CAS_DIR_LOCK,
277	CAS_DIR_HIT_READ,
278	CAS_DIR_HIT_COMPARE,
279	CAS_DIR_HIT_WRITE,
280	CAS_UPT_LOCK,
281	CAS_UPT_HEAP_LOCK,
282	CAS_UPT_REQ,
283	CAS_UPT_NEXT,
284	CAS_BC_TRT_LOCK,
285	CAS_BC_IVT_LOCK,
286	CAS_BC_DIR_INVAL,
287	CAS_BC_CC_SEND,
288	CAS_BC_XRAM_REQ,
289	CAS_RSP_FAIL,
290	CAS_RSP_SUCCESS,
291	CAS_MISS_TRT_LOCK,
292	CAS_MISS_TRT_SET,
293	CAS_MISS_XRAM_REQ,
294	CAS_WAIT
295	};
296
297	/* States of the CLEANUP fsm */
298	enum cleanup_fsm_state_e
299	{
300	CLEANUP_IDLE,
301	CLEANUP_GET_NLINE,
302	CLEANUP_GET_DATA,
303	CLEANUP_DIR_REQ,
304	CLEANUP_DIR_LOCK,
305	CLEANUP_DIR_WRITE,
306	CLEANUP_IVT_LOCK_DATA,
307	CLEANUP_IVT_CLEAR_DATA,
308	CLEANUP_READ_RSP,
309	CLEANUP_HEAP_REQ,
310	CLEANUP_HEAP_LOCK,
311	CLEANUP_HEAP_SEARCH,
312	CLEANUP_HEAP_CLEAN,
313	CLEANUP_HEAP_FREE,
314	CLEANUP_IVT_LOCK,
315	CLEANUP_IVT_DECREMENT,
316	CLEANUP_IVT_CLEAR,
317	CLEANUP_WRITE_RSP,
318	CLEANUP_IXR_REQ,
319	CLEANUP_WAIT,
320	CLEANUP_CONFIG_ACK,
321	CLEANUP_SEND_CLACK
322	};
323
324	/* States of the ALLOC_DIR fsm */
325	enum alloc_dir_fsm_state_e
326	{
327	ALLOC_DIR_RESET,
328	ALLOC_DIR_CONFIG,
329	ALLOC_DIR_READ,
330	ALLOC_DIR_WRITE,
331	ALLOC_DIR_CAS,
332	ALLOC_DIR_CLEANUP,
333	ALLOC_DIR_XRAM_RSP
334	};
335
336	/* States of the ALLOC_TRT fsm */
337	enum alloc_trt_fsm_state_e
338	{
339	ALLOC_TRT_READ,
340	ALLOC_TRT_WRITE,
341	ALLOC_TRT_CAS,
342	ALLOC_TRT_XRAM_RSP,
343	ALLOC_TRT_IXR_RSP,
344	ALLOC_TRT_CLEANUP
345	};
346
347	/* States of the ALLOC_UPT fsm */
348	enum alloc_upt_fsm_state_e
349	{
350	ALLOC_UPT_WRITE,
351	ALLOC_UPT_CAS,
352	ALLOC_UPT_MULTI_ACK
353	};
354
355	/* States of the ALLOC_IVT fsm */
356	enum alloc_ivt_fsm_state_e
357	{
358	ALLOC_IVT_WRITE,
359	ALLOC_IVT_READ,
360	ALLOC_IVT_XRAM_RSP,
361	ALLOC_IVT_CLEANUP,
362	ALLOC_IVT_CAS,
363	ALLOC_IVT_CONFIG
364	};
365
366	/* States of the ALLOC_HEAP fsm */
367	enum alloc_heap_fsm_state_e
368	{
369	ALLOC_HEAP_RESET,
370	ALLOC_HEAP_READ,
371	ALLOC_HEAP_WRITE,
372	ALLOC_HEAP_CAS,
373	ALLOC_HEAP_CLEANUP,
374	ALLOC_HEAP_XRAM_RSP,
375	ALLOC_HEAP_CONFIG
376	};
377
378	/* transaction type, pktid field */
379	enum transaction_type_e
380	{
381	// b3 unused
382	// b2 READ / NOT READ
383	// Si READ
384	// b1 DATA / INS
385	// b0 UNC / MISS
386	// Si NOT READ
387	// b1 accÃšs table llsc type SW / other
388	// b2 WRITE/CAS/LL/SC
389	TYPE_READ_DATA_UNC = 0x0,
390	TYPE_READ_DATA_MISS = 0x1,
391	TYPE_READ_INS_UNC = 0x2,
392	TYPE_READ_INS_MISS = 0x3,
393	TYPE_WRITE = 0x4,
394	TYPE_CAS = 0x5,
395	TYPE_LL = 0x6,
396	TYPE_SC = 0x7
397	};
398
399	/* SC return values */
400	enum sc_status_type_e
401	{
402	SC_SUCCESS = 0x00000000,
403	SC_FAIL = 0x00000001
404	};
405
406	/* Configuration commands */
407	enum cmd_config_type_e
408	{
409	CMD_CONFIG_INVAL = 0,
410	CMD_CONFIG_SYNC = 1
411	};
412
413	// debug variables (for each FSM)
414	bool m_debug;
415	bool m_debug_previous_valid;
416	size_t m_debug_previous_count;
417	bool m_debug_previous_dirty;
418	sc_signal<data_t>* m_debug_previous_data;
419	sc_signal<data_t>* m_debug_data;
420
421	bool m_monitor_ok;
422	addr_t m_monitor_base;
423	addr_t m_monitor_length;
424
425	// instrumentation counters
426	uint32_t m_cpt_cycles; // Counter of cycles
427
428	uint32_t m_cpt_read; // Number of READ transactions
429	uint32_t m_cpt_read_remote; // number of remote READ transactions
430	uint32_t m_cpt_read_flits; // number of flits for READs
431	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs
432
433	uint32_t m_cpt_read_miss; // Number of MISS READ
434
435	uint32_t m_cpt_write; // Number of WRITE transactions
436	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
437	uint32_t m_cpt_write_flits; // number of flits for WRITEs
438	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
439
440	uint32_t m_cpt_write_miss; // Number of MISS WRITE
441	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
442	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
443	uint32_t m_cpt_update; // Number of UPDATE transactions
444	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
445	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
446	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
447	uint32_t m_cpt_inval; // Number of INVAL transactions
448	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
449	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
450	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
451	uint32_t m_cpt_ll; // Number of LL transactions
452	uint32_t m_cpt_sc; // Number of SC transactions
453	uint32_t m_cpt_cas; // Number of CAS transactions
454
455	uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK
456	uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK
457	uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK
458	uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK
459	uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK
460	uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK
461	uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK
462	uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK
463	uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK
464	uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK
465
466	uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused
467	uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used
468	uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used
469	uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used
470	uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
471	uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used
472
473	uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK
474	uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK
475	uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK
476	uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK
477	uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK
478
479	uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK
480	uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK
481	uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK
482	uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK
483	uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK
484
485	uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used
486	uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used
487	uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used
488	uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used
489	uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used
490
491	uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused
492
493	uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK
494	uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK
495	uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK
496	uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait UPT LOCK
497	uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK
498
499	uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK
500	uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK
501	uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK
502	uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK
503	uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK
504
505	uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used
506	uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used
507	uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used
508	uint32_t m_cpt_cleanup_fsm_ivt_used; // NB cycles UPT LOCK used
509	uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used
510
511	uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused
512	uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused
513
514	uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK
515	uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK
516	uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK
517	uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK
518	uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
519
520	uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK
521	uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK
522	uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK
523	uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK
524	uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
525
526	uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used
527	uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used
528	uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used
529	uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used
530	uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
531
532	uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused
533
534	//RWT
535	uint32_t m_cpt_cleanup_data;
536	uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ
537	uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE
538	uint32_t m_cpt_ncc_to_cc; // NB change from NCC to CC
539
540	uint32_t m_cpt_read_data_unc;
541	uint32_t m_cpt_read_data_miss_CC;
542	uint32_t m_cpt_read_ins_unc;
543	uint32_t m_cpt_read_ins_miss;
544	uint32_t m_cpt_read_ll_CC;
545	uint32_t m_cpt_read_data_miss_NCC;
546	uint32_t m_cpt_read_ll_NCC;
547	uint32_t m_cpt_read_WTF;
548
549	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs
550
551	uint32_t m_cpt_update_flits; // Number of flits for UPDATEs
552	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDATEs
553
554	uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs
555
556	uint32_t m_cpt_get;
557
558	uint32_t m_cpt_put;
559
560	size_t m_prev_count;
561
562	protected:
563
564	SC_HAS_PROCESS(VciMemCache);
565
566	public:
567	sc_in<bool> p_clk;
568	sc_in<bool> p_resetn;
569	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
570	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
571	soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m;
572	soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
573	soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
574
575	VciMemCache(
576	sc_module_name name, // Instance Name
577	const soclib::common::MappingTable &mtp, // Mapping table INT network
578	const soclib::common::MappingTable &mtx, // Mapping table RAM network
579	const soclib::common::IntTab &srcid_x, // global index RAM network
580	const soclib::common::IntTab &tgtid_d, // global index INT network
581	const size_t cc_global_id, // global index CC network
582	const size_t nways, // Number of ways per set
583	const size_t nsets, // Number of sets
584	const size_t nwords, // Number of words per line
585	const size_t max_copies, // max number of copies
586	const size_t heap_size=HEAP_ENTRIES,
587	const size_t trt_lines=TRT_ENTRIES,
588	const size_t upt_lines=UPT_ENTRIES,
589	const size_t ivt_lines=IVT_ENTRIES,
590	const size_t debug_start_cycle=0,
591	const bool debug_ok=false );
592
593	~VciMemCache();
594
595	void clear_stats();
596	void print_stats();
597	void print_trace();
598	void cache_monitor(addr_t addr);
599	void start_monitor(addr_t addr, addr_t length);
600	void stop_monitor();
601
602	private:
603
604	void transition();
605	void genMoore();
606	void check_monitor(addr_t addr, data_t data, bool read);
607
608	// Component attributes
609	std::list<soclib::common::Segment> m_seglist; // segments allocated
610	size_t m_nseg; // number of segments
611	soclib::common::Segment **m_seg; // array of segments pointers
612	size_t m_seg_config; // config segment index
613	const size_t m_srcid_x; // global index on RAM network
614	const size_t m_initiators; // Number of initiators
615	const size_t m_heap_size; // Size of the heap
616	const size_t m_ways; // Number of ways in a set
617	const size_t m_sets; // Number of cache sets
618	const size_t m_words; // Number of words in a line
619	const size_t m_cc_global_id; // global_index on cc network
620	size_t m_debug_start_cycle;
621	bool m_debug_ok;
622	uint32_t m_trt_lines;
623	TransactionTab m_trt; // xram transaction table
624	uint32_t m_upt_lines;
625	UpdateTab m_upt; // pending update
626	UpdateTab m_ivt; // pending invalidate
627	CacheDirectory m_cache_directory; // data cache directory
628	CacheData m_cache_data; // data array[set][way][word]
629	HeapDirectory m_heap; // heap for copies
630	size_t m_max_copies; // max number of copies in heap
631	GenericLLSCGlobalTable
632	< 32 , // number of slots
633	4096, // number of processors in the system
634	8000, // registration life (# of LL operations)
635	addr_t > m_llsc_table; // ll/sc registration table
636
637	// adress masks
638	const soclib::common::AddressMaskingTable<addr_t> m_x;
639	const soclib::common::AddressMaskingTable<addr_t> m_y;
640	const soclib::common::AddressMaskingTable<addr_t> m_z;
641	const soclib::common::AddressMaskingTable<addr_t> m_nline;
642
643	// broadcast address
644	uint32_t m_broadcast_boundaries;
645
646	//////////////////////////////////////////////////
647	// Registers controlled by the TGT_CMD fsm
648	//////////////////////////////////////////////////
649
650	sc_signal<int> r_tgt_cmd_fsm;
651
652	// Fifo between TGT_CMD fsm and READ fsm
653	GenericFifo<addr_t> m_cmd_read_addr_fifo;
654	GenericFifo<size_t> m_cmd_read_length_fifo;
655	GenericFifo<size_t> m_cmd_read_srcid_fifo;
656	GenericFifo<size_t> m_cmd_read_trdid_fifo;
657	GenericFifo<size_t> m_cmd_read_pktid_fifo;
658
659	// Fifo between TGT_CMD fsm and WRITE fsm
660	GenericFifo<addr_t> m_cmd_write_addr_fifo;
661	GenericFifo<bool> m_cmd_write_eop_fifo;
662	GenericFifo<size_t> m_cmd_write_srcid_fifo;
663	GenericFifo<size_t> m_cmd_write_trdid_fifo;
664	GenericFifo<size_t> m_cmd_write_pktid_fifo;
665	GenericFifo<data_t> m_cmd_write_data_fifo;
666	GenericFifo<be_t> m_cmd_write_be_fifo;
667
668	// Fifo between TGT_CMD fsm and CAS fsm
669	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
670	GenericFifo<bool> m_cmd_cas_eop_fifo;
671	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
672	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
673	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
674	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
675
676	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
677	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
678
679	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
680	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
681
682	// Buffer between TGT_CMD fsm and TGT_RSP fsm
683	// (segmentation violation response request)
684	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
685
686	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
687	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
688	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
689	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
690	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
691
692	sc_signal<addr_t> r_tgt_cmd_config_addr;
693	sc_signal<size_t> r_tgt_cmd_config_cmd;
694
695	///////////////////////////////////////////////////////
696	// Registers controlled by the CONFIG fsm
697	///////////////////////////////////////////////////////
698
699	sc_signal<int> r_config_fsm; // FSM state
700	sc_signal<bool> r_config_lock; // lock protecting exclusive access
701	sc_signal<int> r_config_cmd; // config request status
702	sc_signal<addr_t> r_config_address; // target buffer physical address
703	sc_signal<size_t> r_config_srcid; // config request srcid
704	sc_signal<size_t> r_config_trdid; // config request trdid
705	sc_signal<size_t> r_config_pktid; // config request pktid
706	sc_signal<size_t> r_config_nlines; // number of lines covering the buffer
707	sc_signal<size_t> r_config_dir_way; // DIR: selected way
708	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
709	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required)
710	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
711	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
712	sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP
713	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
714
715	sc_signal<size_t> r_config_ivt_index; // IVT index
716
717	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
718	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
719	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
720	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
721	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
722	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
723
724	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
725	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
726	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
727	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
728	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
729	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
730	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
731
732	#if L1_MULTI_CACHE
733	GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
734	#endif
735
736	///////////////////////////////////////////////////////
737	// Registers controlled by the READ fsm
738	///////////////////////////////////////////////////////
739
740	sc_signal<int> r_read_fsm; // FSM state
741	sc_signal<size_t> r_read_copy; // Srcid of the first copy
742	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
743	sc_signal<bool> r_read_copy_inst; // Type of the first copy
744	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
745	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
746	sc_signal<bool> r_read_lock; // lock bit (in directory)
747	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
748	sc_signal<size_t> r_read_count; // number of copies
749	sc_signal<size_t> r_read_ptr; // pointer to the heap
750	sc_signal<data_t> * r_read_data; // data (one cache line)
751	sc_signal<size_t> r_read_way; // associative way (in cache)
752	sc_signal<size_t> r_read_trt_index; // Transaction Table index
753	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
754	sc_signal<bool> r_read_last_free; // Last free entry
755	sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table
756
757	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
758	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
759	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
760	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
761
762	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
763	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
764	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
765	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
766	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
767	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
768	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
769	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
770	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
771
772	//RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
773	sc_signal<bool> r_read_to_cc_send_req;
774	sc_signal<size_t> r_read_to_cc_send_dest;
775	sc_signal<addr_t> r_read_to_cc_send_nline;
776	sc_signal<bool> r_read_to_cc_send_inst;
777
778	//RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
779	sc_signal<bool> r_read_to_cleanup_req; // valid request
780	sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index
781	sc_signal<size_t> r_read_to_cleanup_srcid;
782	sc_signal<size_t> r_read_to_cleanup_length;
783	sc_signal<size_t> r_read_to_cleanup_first_word;
784	sc_signal<bool> r_read_to_cleanup_cached_read;
785	sc_signal<bool> r_read_to_cleanup_is_ll;
786	sc_signal<addr_t> r_read_to_cleanup_addr;
787	sc_signal<addr_t> r_read_to_cleanup_ll_key;
788
789	//RWT:
790	sc_signal<bool> r_read_coherent; // State of the cache slot after transaction
791	sc_signal<bool> r_read_ll_done;
792
793	///////////////////////////////////////////////////////////////
794	// Registers controlled by the WRITE fsm
795	///////////////////////////////////////////////////////////////
796
797	sc_signal<int> r_write_fsm; // FSM state
798	sc_signal<addr_t> r_write_address; // first word address
799	sc_signal<size_t> r_write_word_index; // first word index in line
800	sc_signal<size_t> r_write_word_count; // number of words in line
801	sc_signal<size_t> r_write_srcid; // transaction srcid
802	sc_signal<size_t> r_write_trdid; // transaction trdid
803	sc_signal<size_t> r_write_pktid; // transaction pktid
804	sc_signal<data_t> * r_write_data; // data (one cache line)
805	sc_signal<be_t> * r_write_be; // one byte enable per word
806	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
807	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
808	sc_signal<bool> r_write_lock; // lock bit (in directory)
809	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
810	sc_signal<size_t> r_write_copy; // first owner of the line
811	sc_signal<size_t> r_write_copy_cache; // first owner of the line
812	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
813	sc_signal<size_t> r_write_count; // number of copies
814	sc_signal<size_t> r_write_ptr; // pointer to the heap
815	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
816	sc_signal<bool> r_write_to_dec; // need to decrement update counter
817	sc_signal<size_t> r_write_way; // way of the line
818	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
819	sc_signal<size_t> r_write_upt_index; // index in Update Table
820	sc_signal<bool> r_write_sc_fail; // sc command failed
821	sc_signal<bool> r_write_pending_sc; // sc command pending
822
823	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
824	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
825	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
826	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
827	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
828	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
829
830	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
831	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
832	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
833	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
834	sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data
835	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
836
837	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
838	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
839	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
840	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
841	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
842	sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line)
843	sc_signal<be_t> * r_write_to_cc_send_be; // word enable
844	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
845	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
846	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
847	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
848
849	#if L1_MULTI_CACHE
850	GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
851	#endif
852
853	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
854	sc_signal<bool> r_write_to_multi_ack_req; // valid request
855	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
856
857	// RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
858	sc_signal<bool> r_write_to_cleanup_req; // valid request
859	sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index
860
861	// RWT
862	sc_signal<bool> r_write_coherent; // cache slot state after transaction
863
864	//Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
865	sc_signal<bool> r_write_to_cc_send_req;
866	sc_signal<size_t> r_write_to_cc_send_dest;
867
868
869	/////////////////////////////////////////////////////////
870	// Registers controlled by MULTI_ACK fsm
871	//////////////////////////////////////////////////////////
872
873	sc_signal<int> r_multi_ack_fsm; // FSM state
874	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
875	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
876	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
877	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
878	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
879
880	// signaling completion of multi-inval to CONFIG fsm
881	sc_signal<bool> r_multi_ack_to_config_ack;
882
883	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
884	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
885	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
886	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
887	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
888
889	///////////////////////////////////////////////////////
890	// Registers controlled by CLEANUP fsm
891	///////////////////////////////////////////////////////
892
893	sc_signal<int> r_cleanup_fsm; // FSM state
894	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
895	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
896	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
897	sc_signal<addr_t> r_cleanup_nline; // cache line index
898
899	#if L1_MULTI_CACHE
900	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
901	#endif
902
903	sc_signal<copy_t> r_cleanup_copy; // first copy
904	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
905	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
906	sc_signal<copy_t> r_cleanup_count; // number of copies
907	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
908	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
909	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
910	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
911	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
912	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
913	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
914	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
915	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
916	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
917	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
918
919	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp
920	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
921	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
922
923	sc_signal<bool> r_cleanup_need_rsp; // write response required
924	sc_signal<bool> r_cleanup_need_ack; // config acknowledge required
925
926	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
927
928	// signaling completion of broadcast-inval to CONFIG fsm
929	sc_signal<bool> r_cleanup_to_config_ack;
930
931	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
932	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
933	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
934	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
935	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
936	sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key;
937
938	//RWT
939	sc_signal<size_t> r_cleanup_read_srcid;
940	sc_signal<size_t> r_cleanup_read_trdid;
941	sc_signal<size_t> r_cleanup_read_pktid;
942	sc_signal<bool> r_cleanup_read_need_rsp;
943	sc_signal<bool> r_cleanup_to_tgt_rsp_type;
944	sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
945	sc_signal<size_t> r_cleanup_to_tgt_rsp_length;
946	sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word;
947
948	///////////////////////////////////////////////////////
949	// Registers controlled by CAS fsm
950	///////////////////////////////////////////////////////
951
952	sc_signal<int> r_cas_fsm; // FSM state
953	sc_signal<data_t> r_cas_wdata; // write data word
954	sc_signal<data_t> * r_cas_rdata; // read data word
955	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
956	sc_signal<size_t> r_cas_cpt; // size of command
957	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
958	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
959	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
960	sc_signal<size_t> r_cas_count; // number of copies
961	sc_signal<size_t> r_cas_ptr; // pointer to the heap
962	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
963	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
964	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
965	sc_signal<size_t> r_cas_way; // way in directory
966	sc_signal<size_t> r_cas_set; // set in directory
967	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
968	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
969	sc_signal<size_t> r_cas_upt_index; // Update Table index
970	sc_signal<data_t> * r_cas_data; // cache line data
971
972	sc_signal<bool> r_cas_coherent;
973
974	// Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
975	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
976	sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index
977	sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table
978	sc_signal<bool> r_cas_to_ixr_cmd_write; // write request
979	sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data
980
981
982	// Buffer between CAS fsm and TGT_RSP fsm
983	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
984	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
985	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
986	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
987	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
988
989	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
990	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
991	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
992	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
993	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
994	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
995	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
996	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
997	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
998	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
999	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
1000
1001	#if L1_MULTI_CACHE
1002	GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
1003	#endif
1004
1005	////////////////////////////////////////////////////
1006	// Registers controlled by the IXR_RSP fsm
1007	////////////////////////////////////////////////////
1008
1009	sc_signal<int> r_ixr_rsp_fsm; // FSM state
1010	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
1011	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
1012
1013	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
1014	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
1015
1016	////////////////////////////////////////////////////
1017	// Registers controlled by the XRAM_RSP fsm
1018	////////////////////////////////////////////////////
1019
1020	sc_signal<int> r_xram_rsp_fsm; // FSM state
1021	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
1022	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
1023	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
1024	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
1025	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
1026	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
1027	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
1028	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
1029	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
1030	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
1031	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
1032	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
1033	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
1034	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
1035	sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index
1036	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
1037
1038	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
1039	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
1040	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
1041	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
1042	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
1043	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
1044	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
1045	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
1046	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1047	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1048
1049	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1050	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
1051	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
1052	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
1053	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
1054	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
1055	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
1056
1057	#if L1_MULTI_CACHE
1058	GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
1059	#endif
1060
1061	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
1062	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
1063	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
1064	sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data
1065	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
1066
1067	//RWT
1068	sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state
1069	sc_signal<bool> r_xram_rsp_coherent; // coherence of the read
1070	////////////////////////////////////////////////////
1071	// Registers controlled by the IXR_CMD fsm
1072	////////////////////////////////////////////////////
1073
1074	sc_signal<int> r_ixr_cmd_fsm;
1075	sc_signal<size_t> r_ixr_cmd_cpt;
1076
1077	////////////////////////////////////////////////////
1078	// Registers controlled by TGT_RSP fsm
1079	////////////////////////////////////////////////////
1080
1081	sc_signal<int> r_tgt_rsp_fsm;
1082	sc_signal<size_t> r_tgt_rsp_cpt;
1083	sc_signal<bool> r_tgt_rsp_key_sent;
1084
1085	////////////////////////////////////////////////////
1086	// Registers controlled by CC_SEND fsm
1087	////////////////////////////////////////////////////
1088
1089	sc_signal<int> r_cc_send_fsm;
1090	sc_signal<size_t> r_cc_send_cpt;
1091	sc_signal<bool> r_cc_send_inst;
1092
1093	////////////////////////////////////////////////////
1094	// Registers controlled by CC_RECEIVE fsm
1095	////////////////////////////////////////////////////
1096
1097	sc_signal<int> r_cc_receive_fsm;
1098
1099	////////////////////////////////////////////////////
1100	// Registers controlled by ALLOC_DIR fsm
1101	////////////////////////////////////////////////////
1102
1103	sc_signal<int> r_alloc_dir_fsm;
1104	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1105
1106	////////////////////////////////////////////////////
1107	// Registers controlled by ALLOC_TRT fsm
1108	////////////////////////////////////////////////////
1109
1110	sc_signal<int> r_alloc_trt_fsm;
1111
1112	////////////////////////////////////////////////////
1113	// Registers controlled by ALLOC_UPT fsm
1114	////////////////////////////////////////////////////
1115
1116	sc_signal<int> r_alloc_upt_fsm;
1117
1118	////////////////////////////////////////////////////
1119	// Registers controlled by ALLOC_IVT fsm
1120	////////////////////////////////////////////////////
1121
1122	sc_signal<int> r_alloc_ivt_fsm;
1123
1124	////////////////////////////////////////////////////
1125	// Registers controlled by ALLOC_HEAP fsm
1126	////////////////////////////////////////////////////
1127
1128	sc_signal<int> r_alloc_heap_fsm;
1129	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1130
1131
1132	////////////////////////////////////////////////////
1133	// REGISTERS FOR ODCCP
1134	////////////////////////////////////////////////////
1135
1136	sc_signal<uint32_t> r_cleanup_data_index;
1137	sc_signal<uint32_t> r_cleanup_trdid;
1138	sc_signal<uint32_t> r_cleanup_pktid;
1139	sc_signal<bool> r_cleanup_coherent;
1140	sc_signal<data_t> *r_cleanup_data;
1141	sc_signal<data_t> *r_cleanup_old_data;
1142	sc_signal<bool> r_cleanup_contains_data;
1143
1144	sc_signal<bool> r_cleanup_ncc;
1145	sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty;
1146	sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1147
1148	sc_signal<bool> r_cleanup_to_ixr_cmd_req;
1149	sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
1150	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid;
1151	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_trdid;
1152	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid;
1153	sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
1154	}; // end class VciMemCache
1155
1156	}}
1157
1158	#endif
1159
1160	// Local Variables:
1161	// tab-width: 2
1162	// c-basic-offset: 2
1163	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1164	// indent-tabs-mode: nil
1165	// End:
1166
1167	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1168

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