source: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 814

Last change on this file since 814 was 814, checked in by devigne, 9 years ago

RWT commit : Cosmetic (Remove trailing whitespace)

File size: 48.7 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain.greiner@lip6.fr
28 *              eric.guthmuller@polytechnique.edu
29 *              cesar.fuguet-tortolero@lip6.fr
30 *              alexandre.joannou@lip6.fr
31 */
32
33#ifndef SOCLIB_CABA_MEM_CACHE_H
34#define SOCLIB_CABA_MEM_CACHE_H
35
36#include <inttypes.h>
37#include <systemc>
38#include <list>
39#include <cassert>
40#include "arithmetics.h"
41#include "alloc_elems.h"
42#include "caba_base_module.h"
43#include "vci_target.h"
44#include "vci_initiator.h"
45#include "generic_fifo.h"
46#include "mapping_table.h"
47#include "int_tab.h"
48#include "generic_llsc_global_table.h"
49#include "mem_cache_directory.h"
50#include "xram_transaction.h"
51#include "update_tab.h"
52#include "dspin_interface.h"
53#include "dspin_rwt_param.h"
54
55#define TRT_ENTRIES      4      // Number of entries in TRT
56#define UPT_ENTRIES      4      // Number of entries in UPT
57#define IVT_ENTRIES      4      // Number of entries in IVT
58#define HEAP_ENTRIES     1024   // Number of entries in HEAP
59
60namespace soclib {  namespace caba {
61
62  using namespace sc_core;
63
64  template<typename vci_param_int,
65           typename vci_param_ext,
66           size_t   dspin_in_width,
67           size_t   dspin_out_width>
68    class VciMemCache
69    : public soclib::caba::BaseModule
70    {
71      typedef typename vci_param_int::fast_addr_t  addr_t;
72      typedef typename sc_dt::sc_uint<64>          wide_data_t;
73      typedef uint32_t                             data_t;
74      typedef uint32_t                             tag_t;
75      typedef uint32_t                             be_t;
76      typedef uint32_t                             copy_t;
77
78      /* States of the TGT_CMD fsm */
79      enum tgt_cmd_fsm_state_e
80      {
81        TGT_CMD_IDLE,
82        TGT_CMD_READ,
83        TGT_CMD_WRITE,
84        TGT_CMD_CAS,
85        TGT_CMD_CONFIG,
86        TGT_CMD_ERROR
87      };
88
89      /* States of the TGT_RSP fsm */
90      enum tgt_rsp_fsm_state_e
91      {
92        TGT_RSP_READ_IDLE,
93        TGT_RSP_WRITE_IDLE,
94        TGT_RSP_CAS_IDLE,
95        TGT_RSP_XRAM_IDLE,
96        TGT_RSP_MULTI_ACK_IDLE,
97        TGT_RSP_CLEANUP_IDLE,
98        TGT_RSP_TGT_CMD_IDLE,
99        TGT_RSP_CONFIG_IDLE,
100        TGT_RSP_READ,
101        TGT_RSP_WRITE,
102        TGT_RSP_CAS,
103        TGT_RSP_XRAM,
104        TGT_RSP_MULTI_ACK,
105        TGT_RSP_CLEANUP,
106        TGT_RSP_TGT_CMD,
107        TGT_RSP_CONFIG
108      };
109
110      /* States of the DSPIN_TGT fsm */
111      enum cc_receive_fsm_state_e
112      {
113        CC_RECEIVE_IDLE,
114        CC_RECEIVE_CLEANUP,
115        CC_RECEIVE_CLEANUP_EOP,
116        CC_RECEIVE_MULTI_ACK
117      };
118
119      /* States of the CC_SEND fsm */
120      enum cc_send_fsm_state_e
121      {
122        CC_SEND_XRAM_RSP_IDLE,
123        CC_SEND_WRITE_IDLE,
124        CC_SEND_READ_IDLE,
125        CC_SEND_CAS_IDLE,
126        CC_SEND_CONFIG_IDLE,
127        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
128        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
129        CC_SEND_XRAM_RSP_INVAL_HEADER,
130        CC_SEND_XRAM_RSP_INVAL_NLINE,
131        CC_SEND_READ_NCC_INVAL_HEADER,
132        CC_SEND_READ_NCC_INVAL_NLINE,
133        CC_SEND_WRITE_NCC_INVAL_HEADER,
134        CC_SEND_WRITE_NCC_INVAL_NLINE,
135        CC_SEND_WRITE_BRDCAST_HEADER,
136        CC_SEND_WRITE_BRDCAST_NLINE,
137        CC_SEND_WRITE_UPDT_HEADER,
138        CC_SEND_WRITE_UPDT_NLINE,
139        CC_SEND_WRITE_UPDT_DATA,
140        CC_SEND_CAS_BRDCAST_HEADER,
141        CC_SEND_CAS_BRDCAST_NLINE,
142        CC_SEND_CAS_UPDT_HEADER,
143        CC_SEND_CAS_UPDT_NLINE,
144        CC_SEND_CAS_UPDT_DATA,
145        CC_SEND_CAS_UPDT_DATA_HIGH,
146        CC_SEND_CONFIG_INVAL_HEADER,
147        CC_SEND_CONFIG_INVAL_NLINE,
148        CC_SEND_CONFIG_BRDCAST_HEADER,
149        CC_SEND_CONFIG_BRDCAST_NLINE
150      };
151
152      /* States of the MULTI_ACK fsm */
153      enum multi_ack_fsm_state_e
154      {
155        MULTI_ACK_IDLE,
156        MULTI_ACK_UPT_LOCK,
157        MULTI_ACK_UPT_CLEAR,
158        MULTI_ACK_WRITE_RSP
159      };
160
161      /* States of the CONFIG fsm */
162      enum config_fsm_state_e
163      {
164        CONFIG_IDLE,
165        CONFIG_LOOP,
166        CONFIG_WAIT,
167        CONFIG_RSP,
168        CONFIG_DIR_REQ,
169        CONFIG_DIR_ACCESS,
170        CONFIG_IVT_LOCK,
171        CONFIG_BC_SEND,
172        CONFIG_INVAL_SEND,
173        CONFIG_HEAP_REQ,
174        CONFIG_HEAP_SCAN,
175        CONFIG_HEAP_LAST,
176        CONFIG_TRT_LOCK,
177        CONFIG_TRT_SET,
178        CONFIG_PUT_REQ
179      };
180
181      /* States of the READ fsm */
182      enum read_fsm_state_e
183      {
184        READ_IDLE,
185        READ_DIR_REQ,
186        READ_DIR_LOCK,
187        READ_IVT_LOCK,
188        READ_WAIT,
189        READ_DIR_HIT,
190        READ_HEAP_REQ,
191        READ_HEAP_LOCK,
192        READ_HEAP_WRITE,
193        READ_HEAP_ERASE,
194        READ_HEAP_LAST,
195        READ_RSP,
196        READ_TRT_LOCK,
197        READ_TRT_SET,
198        READ_TRT_REQ
199      };
200
201      /* States of the WRITE fsm */
202      enum write_fsm_state_e
203      {
204        WRITE_IDLE,
205        WRITE_NEXT,
206        WRITE_DIR_REQ,
207        WRITE_DIR_LOCK,
208        WRITE_IVT_LOCK_HIT_WB,
209        WRITE_DIR_HIT,
210        WRITE_UPT_LOCK,
211        WRITE_UPT_HEAP_LOCK,
212        WRITE_UPT_REQ,
213        WRITE_UPT_NEXT,
214        WRITE_UPT_DEC,
215        WRITE_RSP,
216        WRITE_MISS_IVT_LOCK,
217        WRITE_MISS_TRT_LOCK,
218        WRITE_MISS_TRT_DATA,
219        WRITE_MISS_TRT_SET,
220        WRITE_MISS_XRAM_REQ,
221        WRITE_BC_DIR_READ,
222        WRITE_BC_TRT_LOCK,
223        WRITE_BC_IVT_LOCK,
224        WRITE_BC_DIR_INVAL,
225        WRITE_BC_CC_SEND,
226        WRITE_BC_XRAM_REQ,
227        WRITE_WAIT
228      };
229
230      /* States of the IXR_RSP fsm */
231      enum ixr_rsp_fsm_state_e
232      {
233        IXR_RSP_IDLE,
234        IXR_RSP_ACK,
235        IXR_RSP_TRT_ERASE,
236        IXR_RSP_TRT_READ
237      };
238
239      /* States of the XRAM_RSP fsm */
240      enum xram_rsp_fsm_state_e
241      {
242        XRAM_RSP_IDLE,
243        XRAM_RSP_TRT_COPY,
244        XRAM_RSP_TRT_DIRTY,
245        XRAM_RSP_DIR_LOCK,
246        XRAM_RSP_DIR_UPDT,
247        XRAM_RSP_DIR_RSP,
248        XRAM_RSP_IVT_LOCK,
249        XRAM_RSP_INVAL_WAIT,
250        XRAM_RSP_INVAL,
251        XRAM_RSP_WRITE_DIRTY,
252        XRAM_RSP_HEAP_REQ,
253        XRAM_RSP_HEAP_ERASE,
254        XRAM_RSP_HEAP_LAST,
255        XRAM_RSP_ERROR_ERASE,
256        XRAM_RSP_ERROR_RSP
257      };
258
259      /* States of the IXR_CMD fsm */
260      enum ixr_cmd_fsm_state_e
261      {
262        IXR_CMD_READ_IDLE,
263        IXR_CMD_WRITE_IDLE,
264        IXR_CMD_CAS_IDLE,
265        IXR_CMD_XRAM_IDLE,
266        IXR_CMD_CLEANUP_IDLE,
267        IXR_CMD_CONFIG_IDLE,
268        IXR_CMD_READ_TRT,
269        IXR_CMD_WRITE_TRT,
270        IXR_CMD_CAS_TRT,
271        IXR_CMD_XRAM_TRT,
272        IXR_CMD_CLEANUP_TRT,
273        IXR_CMD_CONFIG_TRT,
274        IXR_CMD_READ_SEND,
275        IXR_CMD_WRITE_SEND,
276        IXR_CMD_CAS_SEND,
277        IXR_CMD_XRAM_SEND,
278        IXR_CMD_CLEANUP_DATA_SEND,
279        IXR_CMD_CONFIG_SEND
280      };
281
282      /* States of the CAS fsm */
283      enum cas_fsm_state_e
284      {
285        CAS_IDLE,
286        CAS_DIR_REQ,
287        CAS_DIR_LOCK,
288        CAS_DIR_HIT_READ,
289        CAS_DIR_HIT_COMPARE,
290        CAS_DIR_HIT_WRITE,
291        CAS_UPT_LOCK,
292        CAS_UPT_HEAP_LOCK,
293        CAS_UPT_REQ,
294        CAS_UPT_NEXT,
295        CAS_BC_TRT_LOCK,
296        CAS_BC_IVT_LOCK,
297        CAS_BC_DIR_INVAL,
298        CAS_BC_CC_SEND,
299        CAS_BC_XRAM_REQ,
300        CAS_RSP_FAIL,
301        CAS_RSP_SUCCESS,
302        CAS_MISS_TRT_LOCK,
303        CAS_MISS_TRT_SET,
304        CAS_MISS_XRAM_REQ,
305        CAS_WAIT
306      };
307
308      /* States of the CLEANUP fsm */
309      enum cleanup_fsm_state_e
310      {
311        CLEANUP_IDLE,
312        CLEANUP_GET_NLINE,
313        CLEANUP_GET_DATA,
314        CLEANUP_DIR_REQ,
315        CLEANUP_DIR_LOCK,
316        CLEANUP_DIR_WRITE,
317        CLEANUP_IVT_LOCK_DATA,
318        CLEANUP_IVT_CLEAR_DATA,
319        CLEANUP_READ_RSP,
320        CLEANUP_HEAP_REQ,
321        CLEANUP_HEAP_LOCK,
322        CLEANUP_HEAP_SEARCH,
323        CLEANUP_HEAP_CLEAN,
324        CLEANUP_HEAP_FREE,
325        CLEANUP_IVT_LOCK,
326        CLEANUP_IVT_DECREMENT,
327        CLEANUP_IVT_CLEAR,
328        CLEANUP_WRITE_RSP,
329        CLEANUP_IXR_REQ,
330        CLEANUP_WAIT,
331        CLEANUP_SEND_CLACK
332      };
333
334      /* States of the ALLOC_DIR fsm */
335      enum alloc_dir_fsm_state_e
336      {
337        ALLOC_DIR_RESET,
338        ALLOC_DIR_READ,
339        ALLOC_DIR_WRITE,
340        ALLOC_DIR_CAS,
341        ALLOC_DIR_CLEANUP,
342        ALLOC_DIR_XRAM_RSP,
343        ALLOC_DIR_CONFIG
344      };
345
346      /* States of the ALLOC_TRT fsm */
347      enum alloc_trt_fsm_state_e
348      {
349        ALLOC_TRT_READ,
350        ALLOC_TRT_WRITE,
351        ALLOC_TRT_CAS,
352        ALLOC_TRT_XRAM_RSP,
353        ALLOC_TRT_IXR_RSP,
354        ALLOC_TRT_CLEANUP,
355        ALLOC_TRT_IXR_CMD,
356        ALLOC_TRT_CONFIG
357      };
358
359      /* States of the ALLOC_UPT fsm */
360      enum alloc_upt_fsm_state_e
361      {
362        ALLOC_UPT_WRITE,
363        ALLOC_UPT_CAS,
364        ALLOC_UPT_MULTI_ACK
365      };
366
367      /* States of the ALLOC_IVT fsm */
368      enum alloc_ivt_fsm_state_e
369      {
370        ALLOC_IVT_WRITE,
371        ALLOC_IVT_READ,
372        ALLOC_IVT_XRAM_RSP,
373        ALLOC_IVT_CLEANUP,
374        ALLOC_IVT_CAS,
375        ALLOC_IVT_CONFIG
376      };
377
378      /* States of the ALLOC_HEAP fsm */
379      enum alloc_heap_fsm_state_e
380      {
381        ALLOC_HEAP_RESET,
382        ALLOC_HEAP_READ,
383        ALLOC_HEAP_WRITE,
384        ALLOC_HEAP_CAS,
385        ALLOC_HEAP_CLEANUP,
386        ALLOC_HEAP_XRAM_RSP,
387        ALLOC_HEAP_CONFIG
388      };
389
390      /* transaction type, pktid field */
391      enum transaction_type_e
392      {
393          // b3 unused
394          // b2 READ / NOT READ
395          // Si READ
396          //  b1 DATA / INS
397          //  b0 UNC / MISS
398          // Si NOT READ
399          //  b1 accÚs table llsc type SW / other
400          //  b2 WRITE/CAS/LL/SC
401          TYPE_READ_DATA_UNC   = 0x0,
402          TYPE_READ_DATA_MISS  = 0x1,
403          TYPE_READ_INS_UNC    = 0x2,
404          TYPE_READ_INS_MISS   = 0x3,
405          TYPE_WRITE           = 0x4,
406          TYPE_CAS             = 0x5,
407          TYPE_LL              = 0x6,
408          TYPE_SC              = 0x7
409      };
410
411      /* SC return values */
412      enum sc_status_type_e
413      {
414          SC_SUCCESS = 0x00000000,
415          SC_FAIL    = 0x00000001
416      };
417
418      // debug variables
419      bool     m_debug;
420      bool     m_debug_previous_valid;
421      size_t   m_debug_previous_count;
422      bool     m_debug_previous_dirty;
423      data_t * m_debug_previous_data;
424      data_t * m_debug_data;
425
426      // instrumentation counters
427      uint32_t m_cpt_cycles;        // Counter of cycles
428
429      // Counters accessible in software (not yet but eventually) and tagged
430      uint32_t m_cpt_reset_count;    // Last cycle at which counters have been reset
431      uint32_t m_cpt_read_local;     // Number of local READ transactions
432      uint32_t m_cpt_read_remote;    // number of remote READ transactions
433      uint32_t m_cpt_read_cost;      // Number of (flits * distance) for READs
434
435      uint32_t m_cpt_write_local;    // Number of local WRITE transactions
436      uint32_t m_cpt_write_remote;   // number of remote WRITE transactions
437      uint32_t m_cpt_write_flits_local;  // number of flits for local WRITEs
438      uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
439      uint32_t m_cpt_write_cost;     // Number of (flits * distance) for WRITEs
440      uint32_t m_cpt_write_ncc_miss;   // Number of write on ncc line
441
442      uint32_t m_cpt_ll_local;       // Number of local LL transactions
443      uint32_t m_cpt_ll_remote;      // number of remote LL transactions
444      uint32_t m_cpt_ll_cost;        // Number of (flits * distance) for LLs
445
446      uint32_t m_cpt_sc_local;       // Number of local SC transactions
447      uint32_t m_cpt_sc_remote;      // number of remote SC transactions
448      uint32_t m_cpt_sc_cost;        // Number of (flits * distance) for SCs
449
450      uint32_t m_cpt_cas_local;      // Number of local SC transactions
451      uint32_t m_cpt_cas_remote;     // number of remote SC transactions
452      uint32_t m_cpt_cas_cost;       // Number of (flits * distance) for SCs
453
454      uint32_t m_cpt_update;         // Number of requests causing an UPDATE
455      uint32_t m_cpt_update_local;   // Number of local UPDATE transactions
456      uint32_t m_cpt_update_remote;  // Number of remote UPDATE transactions
457      uint32_t m_cpt_update_cost;    // Number of (flits * distance) for UPDT
458
459      uint32_t m_cpt_minval;         // Number of requests causing M_INV
460      uint32_t m_cpt_minval_local;   // Number of local M_INV transactions
461      uint32_t m_cpt_minval_remote;  // Number of remote M_INV transactions
462      uint32_t m_cpt_minval_cost;    // Number of (flits * distance) for M_INV
463
464      uint32_t m_cpt_binval;         // Number of BROADCAST INVAL
465
466      uint32_t m_cpt_cleanup_local;  // Number of local CLEANUP transactions (all cleanup types)
467      uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (all cleanup types)
468      uint32_t m_cpt_cleanup_cost;   // Number of (flits * distance) for CLEANUPs (all types)
469
470      // Counters not accessible by software, but tagged
471      uint32_t m_cpt_read_miss;       // Number of MISS READ
472      uint32_t m_cpt_write_miss;      // Number of MISS WRITE
473      uint32_t m_cpt_write_dirty;     // Cumulated length for WRITE transactions
474      uint32_t m_cpt_write_broadcast; // Number of BROADCAST INVAL because write
475
476      uint32_t m_cpt_trt_rb;          // Read blocked by a hit in trt
477      uint32_t m_cpt_trt_full;        // Transaction blocked due to a full trt
478
479      uint32_t m_cpt_heap_unused;             // NB cycles HEAP LOCK unused
480      uint32_t m_cpt_heap_slot_available;     // NB HEAP slot available refresh at each cycles
481      uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available
482
483      uint32_t m_cpt_ncc_to_cc_read;         // NB change from NCC to CC caused by a READ
484      uint32_t m_cpt_ncc_to_cc_write;        // NB change from NCC to CC caused by a WRITE
485
486      uint32_t m_cpt_cleanup_data_local;  // Number of local cleanups with data
487      uint32_t m_cpt_cleanup_data_remote; // Number of remote cleanups with data
488      uint32_t m_cpt_cleanup_data_cost;   // Cost for cleanups with data
489
490      uint32_t m_cpt_update_flits;  // Number of flits for UPDATEs
491      uint32_t m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
492
493      uint32_t m_cpt_get;
494      uint32_t m_cpt_put;
495
496      uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused
497      uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused
498      uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused
499      uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused
500
501      // Unused
502      uint32_t m_cpt_read_data_unc;
503      uint32_t m_cpt_read_data_miss_CC;
504      uint32_t m_cpt_read_ins_unc;
505      uint32_t m_cpt_read_ins_miss;
506      uint32_t m_cpt_read_ll_CC;
507      uint32_t m_cpt_read_data_miss_NCC;
508      uint32_t m_cpt_read_ll_NCC;
509
510      size_t   m_prev_count;
511
512      protected:
513
514      SC_HAS_PROCESS(VciMemCache);
515
516      public:
517      sc_in<bool>                                 p_clk;
518      sc_in<bool>                                 p_resetn;
519      sc_out<bool>                                p_irq;
520      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
521      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
522      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
523      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
524      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
525
526#if MONITOR_MEMCACHE_FSM == 1
527      sc_out<int> p_read_fsm;
528      sc_out<int> p_write_fsm;
529      sc_out<int> p_xram_rsp_fsm;
530      sc_out<int> p_cas_fsm;
531      sc_out<int> p_cleanup_fsm;
532      sc_out<int> p_config_fsm;
533      sc_out<int> p_alloc_heap_fsm;
534      sc_out<int> p_alloc_dir_fsm;
535      sc_out<int> p_alloc_trt_fsm;
536      sc_out<int> p_alloc_upt_fsm;
537      sc_out<int> p_alloc_ivt_fsm;
538      sc_out<int> p_tgt_cmd_fsm;
539      sc_out<int> p_tgt_rsp_fsm;
540      sc_out<int> p_ixr_cmd_fsm;
541      sc_out<int> p_ixr_rsp_fsm;
542      sc_out<int> p_cc_send_fsm;
543      sc_out<int> p_cc_receive_fsm;
544      sc_out<int> p_multi_ack_fsm;
545#endif
546
547      VciMemCache(
548          sc_module_name name,                                // Instance Name
549          const soclib::common::MappingTable &mtp,            // Mapping table INT network
550          const soclib::common::MappingTable &mtx,            // Mapping table RAM network
551          const soclib::common::IntTab       &srcid_x,        // global index RAM network
552          const soclib::common::IntTab       &tgtid_d,        // global index INT network
553          const size_t                       x_width,         // X width in platform
554          const size_t                       y_width,         // Y width in platform
555          const size_t                       nways,           // Number of ways per set
556          const size_t                       nsets,           // Number of sets
557          const size_t                       nwords,          // Number of words per line
558          const size_t                       max_copies,      // max number of copies
559          const size_t                       heap_size=HEAP_ENTRIES,
560          const size_t                       trt_lines=TRT_ENTRIES,
561          const size_t                       upt_lines=UPT_ENTRIES,
562          const size_t                       ivt_lines=IVT_ENTRIES,
563          const size_t                       debug_start_cycle=0,
564          const bool                         debug_ok=false );
565
566      ~VciMemCache();
567
568      void reset_counters();
569      void print_stats(bool activity_counters = true, bool stats = false);
570      void print_trace( size_t detailled = 0 );
571      void cache_monitor(addr_t addr);
572      void start_monitor(addr_t addr, addr_t length);
573      void stop_monitor();
574
575      private:
576
577      void transition();
578      void genMoore();
579      void check_monitor(addr_t addr, data_t data, bool read);
580      uint32_t req_distance(uint32_t req_srcid);
581      uint32_t min_value(uint32_t old_value, uint32_t new_value);
582      bool is_local_req(uint32_t req_srcid);
583      int  read_instrumentation(uint32_t regr, uint32_t & rdata);
584
585      // Component attributes
586      std::list<soclib::common::Segment> m_seglist;          // segments allocated
587      size_t                             m_nseg;             // number of segments
588      soclib::common::Segment            **m_seg;            // array of segments pointers
589      size_t                             m_seg_config;       // config segment index
590      const size_t                       m_srcid_x;          // global index on RAM network
591      const size_t                       m_initiators;       // Number of initiators
592      const size_t                       m_heap_size;        // Size of the heap
593      const size_t                       m_ways;             // Number of ways in a set
594      const size_t                       m_sets;             // Number of cache sets
595      const size_t                       m_words;            // Number of words in a line
596      size_t                             m_x_self;           // X self coordinate
597      size_t                             m_y_self;           // Y self coordinate
598      const size_t                       m_x_width;          // number of x bits in platform
599      const size_t                       m_y_width;          // number of y bits in platform
600      size_t                             m_debug_start_cycle;
601      bool                               m_debug_ok;
602      uint32_t                           m_trt_lines;
603      TransactionTab                     m_trt;              // xram transaction table
604      uint32_t                           m_upt_lines;
605      UpdateTab                          m_upt;              // pending update
606      UpdateTab                          m_ivt;              // pending invalidate
607      CacheDirectory                     m_cache_directory;  // data cache directory
608      CacheData                          m_cache_data;       // data array[set][way][word]
609      HeapDirectory                      m_heap;             // heap for copies
610      size_t                             m_max_copies;       // max number of copies in heap
611      GenericLLSCGlobalTable
612      < 32  ,    // number of slots
613        4096,    // number of processors in the system
614        8000,    // registration life (# of LL operations)
615        addr_t >                         m_llsc_table;       // ll/sc registration table
616
617      // adress masks
618      const soclib::common::AddressMaskingTable<addr_t>   m_x;
619      const soclib::common::AddressMaskingTable<addr_t>   m_y;
620      const soclib::common::AddressMaskingTable<addr_t>   m_z;
621      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
622
623      // broadcast address
624      uint32_t                           m_broadcast_boundaries;
625
626      // configuration interface constants
627      const uint32_t m_config_addr_mask;
628      const uint32_t m_config_regr_width;
629      const uint32_t m_config_func_width;
630      const uint32_t m_config_regr_idx_mask;
631      const uint32_t m_config_func_idx_mask;
632
633      // Fifo between TGT_CMD fsm and READ fsm
634      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
635      GenericFifo<size_t>    m_cmd_read_length_fifo;
636      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
637      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
638      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
639
640      // Fifo between TGT_CMD fsm and WRITE fsm
641      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
642      GenericFifo<bool>      m_cmd_write_eop_fifo;
643      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
644      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
645      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
646      GenericFifo<data_t>    m_cmd_write_data_fifo;
647      GenericFifo<be_t>      m_cmd_write_be_fifo;
648
649      // Fifo between TGT_CMD fsm and CAS fsm
650      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
651      GenericFifo<bool>      m_cmd_cas_eop_fifo;
652      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
653      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
654      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
655      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
656
657      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
658      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
659
660      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
661      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
662
663      // Buffer between TGT_CMD fsm and TGT_RSP fsm
664      // (segmentation violation response request)
665      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
666
667      sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
668      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_error;
669      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
670      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
671      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
672
673      sc_signal<addr_t>   r_tgt_cmd_config_addr;
674      sc_signal<size_t>   r_tgt_cmd_config_cmd;
675
676      //////////////////////////////////////////////////
677      // Registers controlled by the TGT_CMD fsm
678      //////////////////////////////////////////////////
679
680      sc_signal<int>         r_tgt_cmd_fsm;
681
682      ///////////////////////////////////////////////////////
683      // Registers controlled by the CONFIG fsm
684      ///////////////////////////////////////////////////////
685
686      sc_signal<int>      r_config_fsm;               // FSM state
687      sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
688      sc_signal<int>      r_config_cmd;               // config request type
689      sc_signal<addr_t>   r_config_address;           // target buffer physical address
690      sc_signal<size_t>   r_config_srcid;             // config request srcid
691      sc_signal<size_t>   r_config_trdid;             // config request trdid
692      sc_signal<size_t>   r_config_pktid;             // config request pktid
693      sc_signal<size_t>   r_config_cmd_lines;         // number of lines to be handled
694      sc_signal<size_t>   r_config_rsp_lines;         // number of lines not completed
695      sc_signal<size_t>   r_config_dir_way;           // DIR: selected way
696      sc_signal<bool>     r_config_dir_lock;          // DIR: locked entry
697      sc_signal<size_t>   r_config_dir_count;         // DIR: number of copies
698      sc_signal<bool>     r_config_dir_is_cnt;        // DIR: counter mode (broadcast)
699      sc_signal<size_t>   r_config_dir_copy_srcid;    // DIR: first copy SRCID
700      sc_signal<bool>     r_config_dir_copy_inst;     // DIR: first copy L1 type
701      sc_signal<size_t>   r_config_dir_ptr;           // DIR: index of next copy in HEAP
702      sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
703      sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
704      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT
705
706      // Buffer between CONFIG fsm and IXR_CMD fsm
707      sc_signal<bool>     r_config_to_ixr_cmd_req;    // valid request
708      sc_signal<size_t>   r_config_to_ixr_cmd_index;  // TRT index
709
710      // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
711      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
712      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
713      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
714      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
715      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
716
717      // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
718      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
719      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
720      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
721      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
722      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
723      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
724
725      ///////////////////////////////////////////////////////
726      // Registers controlled by the READ fsm
727      ///////////////////////////////////////////////////////
728
729      sc_signal<int>      r_read_fsm;                 // FSM state
730      sc_signal<size_t>   r_read_copy;                // Srcid of the first copy
731      sc_signal<size_t>   r_read_copy_cache;          // Srcid of the first copy
732      sc_signal<bool>     r_read_copy_inst;           // Type of the first copy
733      sc_signal<tag_t>    r_read_tag;                 // cache line tag (in directory)
734      sc_signal<bool>     r_read_is_cnt;              // is_cnt bit (in directory)
735      sc_signal<bool>     r_read_lock;                // lock bit (in directory)
736      sc_signal<bool>     r_read_dirty;               // dirty bit (in directory)
737      sc_signal<size_t>   r_read_count;               // number of copies
738      sc_signal<size_t>   r_read_ptr;                 // pointer to the heap
739      sc_signal<data_t> * r_read_data;                // data (one cache line)
740      sc_signal<size_t>   r_read_way;                 // associative way (in cache)
741      sc_signal<size_t>   r_read_trt_index;           // Transaction Table index
742      sc_signal<size_t>   r_read_next_ptr;            // Next entry to point to
743      sc_signal<bool>     r_read_last_free;           // Last free entry
744      sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
745
746      // Buffer between READ fsm and IXR_CMD fsm
747      sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
748      sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
749
750      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
751      sc_signal<bool>     r_read_to_tgt_rsp_req;      // valid request
752      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;    // Transaction srcid
753      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;    // Transaction trdid
754      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;    // Transaction pktid
755      sc_signal<data_t> * r_read_to_tgt_rsp_data;     // data (one cache line)
756      sc_signal<size_t>   r_read_to_tgt_rsp_word;     // first word of the response
757      sc_signal<size_t>   r_read_to_tgt_rsp_length;   // length of the response
758      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key;   // LL key from llsc_global_table
759
760      //RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
761      sc_signal<bool>     r_read_to_cc_send_req;
762      sc_signal<size_t>   r_read_to_cc_send_dest;
763      sc_signal<addr_t>   r_read_to_cc_send_nline;
764      sc_signal<bool>     r_read_to_cc_send_inst;
765
766      //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
767      sc_signal<bool>     r_read_to_cleanup_req;    // valid request
768      sc_signal<addr_t>   r_read_to_cleanup_nline;  // cache line index
769      sc_signal<size_t>   r_read_to_cleanup_srcid;
770      sc_signal<size_t>   r_read_to_cleanup_inst;
771      sc_signal<size_t>   r_read_to_cleanup_length;
772      sc_signal<size_t>   r_read_to_cleanup_first_word;
773      sc_signal<bool>     r_read_to_cleanup_cached_read;
774      sc_signal<bool>     r_read_to_cleanup_is_ll;
775      sc_signal<addr_t>   r_read_to_cleanup_addr;
776      sc_signal<addr_t>   r_read_to_cleanup_ll_key;
777
778      //RWT:
779      sc_signal<bool>     r_read_coherent;          // State of the cache slot after transaction
780      sc_signal<bool>     r_read_ll_done;
781
782      ///////////////////////////////////////////////////////////////
783      // Registers controlled by the WRITE fsm
784      ///////////////////////////////////////////////////////////////
785
786      sc_signal<int>      r_write_fsm;                // FSM state
787      sc_signal<addr_t>   r_write_address;            // first word address
788      sc_signal<size_t>   r_write_word_index;         // first word index in line
789      sc_signal<size_t>   r_write_word_count;         // number of words in line
790      sc_signal<size_t>   r_write_srcid;              // transaction srcid
791      sc_signal<size_t>   r_write_trdid;              // transaction trdid
792      sc_signal<size_t>   r_write_pktid;              // transaction pktid
793      sc_signal<data_t> * r_write_data;               // data (one cache line)
794      sc_signal<be_t>   * r_write_be;                 // one byte enable per word
795      sc_signal<bool>     r_write_byte;               // (BE != 0X0) and (BE != 0xF)
796      sc_signal<bool>     r_write_is_cnt;             // is_cnt bit (in directory)
797      sc_signal<bool>     r_write_lock;               // lock bit (in directory)
798      sc_signal<tag_t>    r_write_tag;                // cache line tag (in directory)
799      sc_signal<size_t>   r_write_copy;               // first owner of the line
800      sc_signal<size_t>   r_write_copy_cache;         // first owner of the line
801      sc_signal<bool>     r_write_copy_inst;          // is this owner a ICache ?
802      sc_signal<size_t>   r_write_count;              // number of copies
803      sc_signal<size_t>   r_write_ptr;                // pointer to the heap
804      sc_signal<size_t>   r_write_next_ptr;           // next pointer to the heap
805      sc_signal<bool>     r_write_to_dec;             // need to decrement update counter
806      sc_signal<size_t>   r_write_way;                // way of the line
807      sc_signal<size_t>   r_write_trt_index;          // index in Transaction Table
808      sc_signal<size_t>   r_write_upt_index;          // index in Update Table
809      sc_signal<bool>     r_write_sc_fail;            // sc command failed
810      sc_signal<data_t>   r_write_sc_key;             // sc command key
811      sc_signal<bool>     r_write_bc_data_we;         // Write enable for data buffer
812
813      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
814      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
815      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
816      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
817      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
818      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
819
820      // Buffer between WRITE fsm and IXR_CMD fsm
821      sc_signal<bool>     r_write_to_ixr_cmd_req;     // valid request
822      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index
823
824      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
825      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
826      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
827      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
828      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
829      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
830      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
831      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
832      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
833      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
834      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
835
836      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
837      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
838      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
839
840      // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
841      sc_signal<bool>     r_write_to_cleanup_req;         // valid request
842      sc_signal<addr_t>   r_write_to_cleanup_nline;       // cache line index
843
844      // RWT
845      sc_signal<bool>     r_write_coherent;               // cache slot state after transaction
846
847      //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
848      sc_signal<bool>     r_write_to_cc_send_req;
849      sc_signal<size_t>   r_write_to_cc_send_dest;
850
851
852      /////////////////////////////////////////////////////////
853      // Registers controlled by MULTI_ACK fsm
854      //////////////////////////////////////////////////////////
855
856      sc_signal<int>      r_multi_ack_fsm;       // FSM state
857      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
858      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
859      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
860      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
861      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
862
863      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
864      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
865      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
866      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
867      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
868
869      ///////////////////////////////////////////////////////
870      // Registers controlled by CLEANUP fsm
871      ///////////////////////////////////////////////////////
872
873      sc_signal<int>      r_cleanup_fsm;           // FSM state
874      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
875      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
876      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
877      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
878
879
880      sc_signal<copy_t>   r_cleanup_copy;          // first copy
881      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
882      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
883      sc_signal<copy_t>   r_cleanup_count;         // number of copies
884      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
885      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
886      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
887      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
888      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
889      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
890      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
891      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
892      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
893      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
894      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
895
896      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write rsp
897      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
898      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
899
900      sc_signal<bool>     r_cleanup_need_rsp;      // write response required
901      sc_signal<bool>     r_cleanup_need_ack;      // config acknowledge required
902
903      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
904
905      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
906      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
907      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
908      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
909      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
910      sc_signal<addr_t>   r_cleanup_to_tgt_rsp_ll_key;
911
912      //RWT
913      sc_signal<size_t>   r_cleanup_read_srcid;
914      sc_signal<size_t>   r_cleanup_read_trdid;
915      sc_signal<size_t>   r_cleanup_read_pktid;
916      sc_signal<bool>     r_cleanup_read_need_rsp;
917      sc_signal<bool>     r_cleanup_to_tgt_rsp_type;
918      sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
919      sc_signal<size_t>   r_cleanup_to_tgt_rsp_length;
920      sc_signal<size_t>   r_cleanup_to_tgt_rsp_first_word;
921
922      ///////////////////////////////////////////////////////
923      // Registers controlled by CAS fsm
924      ///////////////////////////////////////////////////////
925
926      sc_signal<int>      r_cas_fsm;              // FSM state
927      sc_signal<data_t>   r_cas_wdata;            // write data word
928      sc_signal<data_t> * r_cas_rdata;            // read data word
929      sc_signal<uint32_t> r_cas_lfsr;             // lfsr for random introducing
930      sc_signal<size_t>   r_cas_cpt;              // size of command
931      sc_signal<copy_t>   r_cas_copy;             // Srcid of the first copy
932      sc_signal<copy_t>   r_cas_copy_cache;       // Srcid of the first copy
933      sc_signal<bool>     r_cas_copy_inst;        // Type of the first copy
934      sc_signal<size_t>   r_cas_count;            // number of copies
935      sc_signal<size_t>   r_cas_ptr;              // pointer to the heap
936      sc_signal<size_t>   r_cas_next_ptr;         // next pointer to the heap
937      sc_signal<bool>     r_cas_is_cnt;           // is_cnt bit (in directory)
938      sc_signal<bool>     r_cas_dirty;            // dirty bit (in directory)
939      sc_signal<size_t>   r_cas_way;              // way in directory
940      sc_signal<size_t>   r_cas_set;              // set in directory
941      sc_signal<data_t>   r_cas_tag;              // cache line tag (in directory)
942      sc_signal<size_t>   r_cas_trt_index;        // Transaction Table index
943      sc_signal<size_t>   r_cas_upt_index;        // Update Table index
944      sc_signal<data_t> * r_cas_data;             // cache line data
945
946      sc_signal<bool>     r_cas_coherent;
947
948      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
949      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
950      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index
951
952      // Buffer between CAS fsm and TGT_RSP fsm
953      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
954      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
955      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
956      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
957      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
958
959      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
960      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
961      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
962      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
963      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
964      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
965      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
966      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
967      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
968      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
969      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
970
971      ////////////////////////////////////////////////////
972      // Registers controlled by the IXR_RSP fsm
973      ////////////////////////////////////////////////////
974
975      sc_signal<int>      r_ixr_rsp_fsm;                // FSM state
976      sc_signal<size_t>   r_ixr_rsp_trt_index;          // TRT entry index
977      sc_signal<size_t>   r_ixr_rsp_cpt;                // word counter
978
979      // Buffer between IXR_RSP fsm and CONFIG fsm  (response from the XRAM)
980      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit
981
982      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
983      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok;    // one bit per TRT entry
984
985      ////////////////////////////////////////////////////
986      // Registers controlled by the XRAM_RSP fsm
987      ////////////////////////////////////////////////////
988
989      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
990      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
991      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
992      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
993      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
994      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
995      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
996      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
997      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
998      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
999      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
1000      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
1001      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
1002      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
1003      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
1004      sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
1005      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
1006      sc_signal<bool>     r_xram_rsp_rerror_irq;        // WRITE MISS rerror irq
1007      sc_signal<bool>     r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
1008      sc_signal<addr_t>   r_xram_rsp_rerror_address;    // WRITE MISS rerror address
1009      sc_signal<size_t>   r_xram_rsp_rerror_rsrcid;     // WRITE MISS rerror srcid
1010
1011      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
1012      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
1013      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
1014      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
1015      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
1016      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
1017      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
1018      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
1019      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1020      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1021
1022      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1023      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
1024      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
1025      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
1026      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
1027      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
1028      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
1029
1030      // Buffer between XRAM_RSP fsm and IXR_CMD fsm
1031      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
1032      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index
1033
1034      //RWT
1035      sc_signal<bool>     r_xram_rsp_victim_coherent;      // victim's cache slot state
1036      sc_signal<bool>     r_xram_rsp_coherent;             // coherence of the read
1037      ////////////////////////////////////////////////////
1038      // Registers controlled by the IXR_CMD fsm
1039      ////////////////////////////////////////////////////
1040
1041      sc_signal<int>      r_ixr_cmd_fsm;
1042      sc_signal<size_t>   r_ixr_cmd_word;              // word index for a put
1043      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value
1044      sc_signal<addr_t>   r_ixr_cmd_address;           // address to XRAM
1045      sc_signal<data_t> * r_ixr_cmd_wdata;             // cache line buffer
1046      sc_signal<bool>     r_ixr_cmd_get;               // transaction type (PUT/GET)
1047
1048      ////////////////////////////////////////////////////
1049      // Registers controlled by TGT_RSP fsm
1050      ////////////////////////////////////////////////////
1051
1052      sc_signal<int>      r_tgt_rsp_fsm;
1053      sc_signal<size_t>   r_tgt_rsp_cpt;
1054      sc_signal<bool>     r_tgt_rsp_key_sent;
1055
1056      ////////////////////////////////////////////////////
1057      // Registers controlled by CC_SEND fsm
1058      ////////////////////////////////////////////////////
1059
1060      sc_signal<int>      r_cc_send_fsm;
1061      sc_signal<size_t>   r_cc_send_cpt;
1062      sc_signal<bool>     r_cc_send_inst;
1063
1064      ////////////////////////////////////////////////////
1065      // Registers controlled by CC_RECEIVE fsm
1066      ////////////////////////////////////////////////////
1067
1068      sc_signal<int>      r_cc_receive_fsm;
1069
1070      ////////////////////////////////////////////////////
1071      // Registers controlled by ALLOC_DIR fsm
1072      ////////////////////////////////////////////////////
1073
1074      sc_signal<int>      r_alloc_dir_fsm;
1075      sc_signal<unsigned> r_alloc_dir_reset_cpt;
1076
1077      ////////////////////////////////////////////////////
1078      // Registers controlled by ALLOC_TRT fsm
1079      ////////////////////////////////////////////////////
1080
1081      sc_signal<int>      r_alloc_trt_fsm;
1082
1083      ////////////////////////////////////////////////////
1084      // Registers controlled by ALLOC_UPT fsm
1085      ////////////////////////////////////////////////////
1086
1087      sc_signal<int>      r_alloc_upt_fsm;
1088
1089      ////////////////////////////////////////////////////
1090      // Registers controlled by ALLOC_IVT fsm
1091      ////////////////////////////////////////////////////
1092
1093      sc_signal<int>      r_alloc_ivt_fsm;
1094
1095      ////////////////////////////////////////////////////
1096      // Registers controlled by ALLOC_HEAP fsm
1097      ////////////////////////////////////////////////////
1098
1099      sc_signal<int>      r_alloc_heap_fsm;
1100      sc_signal<unsigned> r_alloc_heap_reset_cpt;
1101
1102
1103      ////////////////////////////////////////////////////
1104      // REGISTERS FOR ODCCP
1105      ////////////////////////////////////////////////////
1106
1107      sc_signal<uint32_t>  r_cleanup_data_index;
1108      sc_signal<uint32_t>  r_cleanup_trdid;
1109      sc_signal<uint32_t>  r_cleanup_pktid;
1110      sc_signal<bool>      r_cleanup_coherent;
1111      sc_signal<data_t>    *r_cleanup_data;
1112      sc_signal<data_t>    *r_cleanup_old_data;
1113      sc_signal<bool>      r_cleanup_contains_data;
1114
1115      sc_signal<bool>      r_cleanup_ncc;
1116      sc_signal<bool>      r_cleanup_to_ixr_cmd_ncc_l1_dirty;
1117      sc_signal<bool>      r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1118
1119      sc_signal<bool>      r_cleanup_to_ixr_cmd_req;
1120      sc_signal<data_t>    *r_cleanup_to_ixr_cmd_data;
1121      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_srcid;
1122      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_index;
1123      sc_signal<uint32_t>  r_cleanup_to_ixr_cmd_pktid;
1124      sc_signal<addr_t>    r_cleanup_to_ixr_cmd_nline;
1125    }; // end class VciMemCache
1126
1127}}
1128
1129#endif
1130
1131// Local Variables:
1132// tab-width: 2
1133// c-basic-offset: 2
1134// c-file-offsets:((innamespace . 0)(inline-open . 0))
1135// indent-tabs-mode: nil
1136// End:
1137
1138// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1139
Note: See TracBrowser for help on using the repository browser.