source: branches/RWT/soft/validation/top.cpp@ 887

Last change on this file since 887 was 843, checked in by devigne, 12 years ago

RWT Commit : Add soft directory.
Soft directory contains scripts used to validate the RWT protocol
File size: 43.0 KB
Line 
1/////////////////////////////////////////////////////////////////////////
2// File: top.cpp
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : may 2013
6// This program is released under the GNU public license
7/////////////////////////////////////////////////////////////////////////
8// This file define a generic TSAR architecture.
9// The physical address space is 40 bits.
10//
11// The number of clusters cannot be larger than 256.
12// The number of processors per cluster cannot be larger than 8.
13//
14// - It uses four dspin_local_crossbar per cluster as local interconnect
15// - It uses two virtual_dspin routers per cluster as global interconnect
16// - It uses the vci_cc_vcache_wrapper
17// - It uses the vci_mem_cache
18// - It contains one vci_xicu per cluster.
19// - It contains one vci_multi_dma per cluster.
20// - It contains one vci_simple_ram per cluster to model the L3 cache.
21//
22// The communication between the MemCache and the Xram is 64 bits.
23//
24// All clusters are identical, but the cluster 0 (called io_cluster),
25// contains 6 extra components:
26// - the boot rom (BROM)
27// - the disk controller (BDEV)
28// - the multi-channel network controller (MNIC)
29// - the multi-channel chained buffer dma controller (CDMA)
30// - the multi-channel tty controller (MTTY)
31// - the frame buffer controller (FBUF)
32//
33// It is build with one single component implementing a cluster,
34// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd)
35//
36// The IRQs are connected to XICUs as follow:
37// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
38// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
39// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
40// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
41//
42// Some hardware parameters are used when compiling the OS, and are used
43// by this top.cpp file. They must be defined in the hard_config.h file :
44// - CLUSTER_X : number of clusters in a row (power of 2)
45// - CLUSTER_Y : number of clusters in a column (power of 2)
46// - CLUSTER_SIZE : size of the segment allocated to a cluster
47// - NB_PROCS_MAX : number of processors per cluster (power of 2)
48// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9)
49// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16)
50// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9)
51//
52// Some other hardware parameters are not used when compiling the OS,
53// and can be directly defined in this top.cpp file:
54// - XRAM_LATENCY : external ram latency
55// - MEMC_WAYS : L2 cache number of ways
56// - MEMC_SETS : L2 cache number of sets
57// - L1_IWAYS
58// - L1_ISETS
59// - L1_DWAYS
60// - L1_DSETS
61// - FBUF_X_SIZE : width of frame buffer (pixels)
62// - FBUF_Y_SIZE : heigth of frame buffer (lines)
63// - BDEV_SECTOR_SIZE : block size for block drvice
64// - BDEV_IMAGE_NAME : file pathname for block device
65// - NIC_RX_NAME : file pathname for NIC received packets
66// - NIC_TX_NAME : file pathname for NIC transmited packets
67// - NIC_TIMEOUT : max number of cycles before closing a container
68/////////////////////////////////////////////////////////////////////////
69// General policy for 40 bits physical address decoding:
70// All physical segments base addresses are multiple of 1 Mbytes
71// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
72// The (x_width + y_width) MSB bits (left aligned) define
73// the cluster index, and the LADR bits define the local index:
74// | X_ID | Y_ID |---| LADR | OFFSET |
75// |x_width|y_width|---| 8 | 24 |
76/////////////////////////////////////////////////////////////////////////
77// General policy for 14 bits SRCID decoding:
78// Each component is identified by (x_id, y_id, l_id) tuple.
79// | X_ID | Y_ID |---| L_ID |
80// |x_width|y_width|---| 6 |
81/////////////////////////////////////////////////////////////////////////
82
83#include <systemc>
84#include <sys/time.h>
85#include <iostream>
86#include <sstream>
87#include <cstdlib>
88#include <cstdarg>
89#include <stdint.h>
90
91#include "gdbserver.h"
92#include "mapping_table.h"
93#include "alloc_elems.h"
94#include "tsar_xbar_cluster.h"
95
96#define USE_ALMOS 1
97//#define USE_GIET
98
99#ifdef USE_ALMOS
100#ifdef USE_GIET
101#error "Can't use Two different OS"
102#endif
103#endif
104
105#ifndef USE_ALMOS
106#ifndef USE_GIET
107#error "You need to specify one OS"
108#endif
109#endif
110
111#ifdef USE_ALMOS
112 #define PREFIX_OS "almos/"
113 #include "almos/hard_config.h"
114#endif
115#ifdef USE_GIET
116 #define PREFIX_OS "giet_vm/"
117#endif
118
119///////////////////////////////////////////////////
120// Parallelisation
121///////////////////////////////////////////////////
122
123
124#if USE_OPENMP
125#include <omp.h>
126#endif
127
128// cluster index (computed from x,y coordinates)
129#ifdef USE_ALMOS
130 #define cluster(x,y) (y + x * Y_SIZE)
131#else
132 #define cluster(x,y) (y + (x << Y_WIDTH))
133#endif
134
135
136#define min(x, y) (x < y ? x : y)
137
138///////////////////////////////////////////////////////////
139// DSPIN parameters
140///////////////////////////////////////////////////////////
141
142#define dspin_cmd_width 39
143#define dspin_rsp_width 32
144
145///////////////////////////////////////////////////////////
146// VCI parameters
147///////////////////////////////////////////////////////////
148
149#define vci_cell_width_int 4
150#define vci_cell_width_ext 8
151
152#ifdef USE_ALMOS
153#define vci_address_width 32
154#endif
155#ifdef USE_GIET
156#define vci_address_width 40
157#endif
158#define vci_plen_width 8
159#define vci_rerror_width 1
160#define vci_clen_width 1
161#define vci_rflag_width 1
162#define vci_srcid_width 14
163#define vci_pktid_width 4
164#define vci_trdid_width 4
165#define vci_wrplen_width 1
166
167////////////////////////////////////////////////////////////
168// Secondary Hardware Parameters
169//////////////////////i/////////////////////////////////////
170
171
172#define XRAM_LATENCY 0
173
174#define MEMC_WAYS 16
175#define MEMC_SETS 256
176
177#define L1_IWAYS 4
178#define L1_ISETS 64
179
180#define L1_DWAYS 4
181#define L1_DSETS 64
182
183#ifdef USE_ALMOS
184#define FBUF_X_SIZE 1024
185#define FBUF_Y_SIZE 1024
186#endif
187#ifdef USE_GIET
188#define FBUF_X_SIZE 128
189#define FBUF_Y_SIZE 128
190#endif
191
192#ifdef USE_GIET
193#define BDEV_SECTOR_SIZE 512
194#define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw"
195#endif
196#ifdef USE_ALMOS
197#define BDEV_SECTOR_SIZE 4096
198#define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin"
199#endif
200
201#define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt"
202#define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt"
203#define NIC_TIMEOUT 10000
204
205#define NORTH 0
206#define SOUTH 1
207#define EAST 2
208#define WEST 3
209
210////////////////////////////////////////////////////////////
211// Software to be loaded in ROM & RAM
212//////////////////////i/////////////////////////////////////
213
214#ifdef USE_ALMOS
215#define soft_name PREFIX_OS"bootloader-tsar-mipsel.bin",\
216 PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\
217 PREFIX_OS"arch-info.bib@0xBFC08000:D"
218#endif
219#ifdef USE_GIET
220#define soft_pathname PREFIX_OS"soft.elf"
221#endif
222
223////////////////////////////////////////////////////////////
224// DEBUG Parameters default values
225//////////////////////i/////////////////////////////////////
226
227#define MAX_FROZEN_CYCLES 100000000
228
229
230////////////////////////////////////////////////////////////////////
231// TGTID definition in direct space
232// For all components: global TGTID = global SRCID = cluster_index
233////////////////////////////////////////////////////////////////////
234
235#define MEMC_TGTID 0
236#define XICU_TGTID 1
237#define MDMA_TGTID 2
238#define MTTY_TGTID 3
239#define BDEV_TGTID 4
240#define MNIC_TGTID 5
241#define BROM_TGTID 6
242#define CDMA_TGTID 7
243#define SIMH_TGTID 8
244#define FBUF_TGTID 9
245
246
247/////////////////////////////////////////////////////////
248// Physical segments definition
249/////////////////////////////////////////////////////////
250// There is 3 segments replicated in all clusters
251// and 5 specific segments in the "IO" cluster
252// (containing address 0xBF000000)
253/////////////////////////////////////////////////////////
254
255#ifdef USE_GIET
256 // specific segments in "IO" cluster : absolute physical address
257 #define BROM_BASE 0x00BFC00000
258 #define BROM_SIZE 0x0000100000 // 1 Mbytes
259
260 #define FBUF_BASE 0x00B2000000
261 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2)
262
263 #define BDEV_BASE 0x00B3000000
264 #define BDEV_SIZE 0x0000001000 // 4 Kbytes
265
266 #define MTTY_BASE 0x00B4000000
267 #define MTTY_SIZE 0x0000001000 // 4 Kbytes
268
269 #define MNIC_BASE 0x00B5000000
270 #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels)
271
272 #define CDMA_BASE 0x00B6000000
273 #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS
274
275 // replicated segments : address is incremented by a cluster offset
276 // offset = cluster(x,y) << (address_width-x_width-y_width);
277
278 #define MEMC_BASE 0x0000000000
279 #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster
280
281 #define XICU_BASE 0x00B0000000
282 #define XICU_SIZE 0x0000001000 // 4 Kbytes
283
284 #define MDMA_BASE 0x00B1000000
285 #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel
286
287 #define SIMH_BASE 0x00B7000000
288 #define SIMH_SIZE 0x0000001000
289#endif
290
291#ifdef USE_ALMOS
292 // 2^19 is the offset for the local id (8 bits for global ID :
293 // 1 bit for Memcache or Peripheral, 4 for local peripheral id)
294 // (Almos supports 32 bits physical addresses)
295
296 #define CLUSTER_INC (0x80000000ULL / (X_SIZE * Y_SIZE) * 2)
297
298 #define CLUSTER_IO_INC (cluster_io_id * CLUSTER_INC)
299 #define MEMC_MAX_SIZE (0x40000000 / (X_SIZE * Y_SIZE)) // 0x40000000 : valeur totale souhaitée (ici : 1Go)
300
301 #define BROM_BASE 0x00BFC00000
302 #define BROM_SIZE 0x0000100000 // 1 Mbytes
303
304 #define MEMC_BASE 0x0000000000
305 #define MEMC_SIZE min(0x04000000, MEMC_MAX_SIZE)
306
307 #define XICU_BASE (CLUSTER_INC >> 1) + (XICU_TGTID << 19)
308 #define XICU_SIZE 0x0000001000 // 4 Kbytes
309
310 #define MDMA_BASE (CLUSTER_INC >> 1) + (MDMA_TGTID << 19)
311 #define MDMA_SIZE (0x0000001000 * NB_DMA_CHANNELS) // 4 Kbytes per channel
312
313 #define BDEV_BASE (CLUSTER_INC >> 1) + (BDEV_TGTID << 19) + (CLUSTER_IO_INC)
314 #define BDEV_SIZE 0x0000001000 // 4 Kbytes
315
316 #define MTTY_BASE (CLUSTER_INC >> 1) + (MTTY_TGTID << 19) + (CLUSTER_IO_INC)
317 #define MTTY_SIZE 0x0000001000 // 4 Kbytes
318
319 #define FBUF_BASE (CLUSTER_INC >> 1) + (FBUF_TGTID << 19) + (CLUSTER_IO_INC)
320 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000
321
322 #define MNIC_BASE (CLUSTER_INC >> 1) + (MNIC_TGTID << 19) + (CLUSTER_IO_INC)
323 #define MNIC_SIZE 0x0000080000
324
325 #define CDMA_BASE (CLUSTER_INC >> 1) + (CDMA_TGTID << 19) + (CLUSTER_IO_INC)
326 #define CDMA_SIZE (0x0000004000 * NB_CMA_CHANNELS)
327
328 #define SIMH_BASE (CLUSTER_INC >> 1) + (SIMH_TGTID << 19) + (CLUSTER_IO_INC)
329 #define SIMH_SIZE 0x0000001000
330#endif
331
332bool stop_called = false;
333
334/////////////////////////////////
335int _main(int argc, char *argv[])
336{
337 using namespace sc_core;
338 using namespace soclib::caba;
339 using namespace soclib::common;
340
341#ifdef USE_GIET
342 char soft_name[256] = soft_pathname; // pathname to binary code
343#endif
344 const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call
345 int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles
346 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
347 char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
348 char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
349 ssize_t threads_nr = 1; // simulator's threads number
350 bool debug_ok = false; // trace activated
351 size_t debug_period = 1; // trace period
352 size_t debug_memc_id = 0; // index of memc to be traced
353 size_t debug_proc_id = 0; // index of proc to be traced
354 int64_t debug_from = 0; // trace start cycle
355 int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
356 size_t cluster_io_id; // index of cluster containing IOs
357 int64_t reset_counters = -1;
358 int64_t dump_counters = -1;
359 bool do_reset_counters = false;
360 bool do_dump_counters = false;
361 struct timeval t1, t2;
362 uint64_t ms1, ms2;
363
364 ////////////// command line arguments //////////////////////
365 if (argc > 1)
366 {
367 for (int n = 1; n < argc; n = n + 2)
368 {
369 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
370 {
371 ncycles = (int64_t) strtol(argv[n + 1], NULL, 0);
372 }
373 else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc))
374 {
375#ifdef USE_ALMOS
376 assert( 0 && "Can't define almos soft name" );
377#endif
378#ifdef USE_GIET
379 strcpy(soft_name, argv[n + 1]);
380#endif
381 }
382 else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc))
383 {
384 strcpy(disk_name, argv[n + 1]);
385 }
386 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
387 {
388 debug_ok = true;
389 debug_from = (int64_t) strtol(argv[n + 1], NULL, 0);
390 }
391 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
392 {
393 debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
394#ifdef USE_ALMOS
395 assert((debug_memc_id < (X_SIZE * Y_SIZE)) &&
396 "debug_memc_id larger than X_SIZE * Y_SIZE" );
397#else
398 size_t x = debug_memc_id >> Y_WIDTH;
399 size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1);
400
401 assert( (x <= X_SIZE) and (y <= Y_SIZE) &&
402 "MEMCID parameter refers a not valid memory cache");
403#endif
404 }
405 else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
406 {
407 debug_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
408#ifdef USE_ALMOS
409 assert((debug_proc_id < (X_SIZE * Y_SIZE * NB_PROCS_MAX)) &&
410 "debug_proc_id larger than X_SIZE * Y_SIZE * NB_PROCS");
411#else
412 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ;
413 size_t x = cluster_xy >> Y_WIDTH;
414 size_t y = cluster_xy & ((1 << Y_WIDTH) - 1);
415
416 assert( (x <= X_SIZE) and (y <= Y_SIZE) &&
417 "PROCID parameter refers a not valid processor");
418#endif
419 }
420 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
421 {
422 threads_nr = (ssize_t) strtol(argv[n + 1], NULL, 0);
423 threads_nr = (threads_nr < 1) ? 1 : threads_nr;
424 }
425 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
426 {
427 frozen_cycles = (int64_t) strtol(argv[n + 1], NULL, 0);
428 }
429 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc))
430 {
431 debug_period = (size_t) strtol(argv[n + 1], NULL, 0);
432 }
433 else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc))
434 {
435 reset_counters = (int64_t) strtol(argv[n + 1], NULL, 0);
436 do_reset_counters = true;
437 }
438 else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc))
439 {
440 dump_counters = (int64_t) strtol(argv[n + 1], NULL, 0);
441 do_dump_counters = true;
442 }
443 else
444 {
445 std::cout << " Arguments are (key,value) couples." << std::endl;
446 std::cout << " The order is not important." << std::endl;
447 std::cout << " Accepted arguments are :" << std::endl << std::endl;
448 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
449 std::cout << " -DISK pathname_for_disk_image" << std::endl;
450 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
451 std::cout << " -DEBUG debug_start_cycle" << std::endl;
452 std::cout << " -THREADS simulator's threads number" << std::endl;
453 std::cout << " -FROZEN max_number_of_lines" << std::endl;
454 std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
455 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
456 std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
457 exit(0);
458 }
459 }
460 }
461
462 // checking hardware parameters
463 assert( ( (X_SIZE == 1) or (X_SIZE == 2) or (X_SIZE == 4) or
464 (X_SIZE == 8) or (X_SIZE == 16) ) and
465 "The X_SIZE parameter must be 1, 2, 4, 8 or 16" );
466
467 assert( ( (Y_SIZE == 1) or (Y_SIZE == 2) or (Y_SIZE == 4) or
468 (Y_SIZE == 8) or (Y_SIZE == 16) ) and
469 "The Y_SIZE parameter must be 1, 2, 4, 8 or 16" );
470
471 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
472 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
473 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
474
475 assert( (NB_DMA_CHANNELS < 9) and
476 "The NB_DMA_CHANNELS parameter must be smaller than 9" );
477
478 assert( (NB_TTY_CHANNELS < 15) and
479 "The NB_TTY_CHANNELS parameter must be smaller than 15" );
480
481 assert( (NB_NIC_CHANNELS < 9) and
482 "The NB_NIC_CHANNELS parameter must be smaller than 9" );
483
484#ifdef USE_GIET
485 assert( (vci_address_width == 40) and
486 "VCI address width with the GIET must be 40 bits" );
487#endif
488
489#ifdef USE_ALMOS
490 assert( (vci_address_width == 32) and
491 "VCI address width with ALMOS must be 32 bits" );
492#endif
493
494
495 std::cout << std::endl;
496 std::cout << " - X_SIZE = " << X_SIZE << std::endl;
497 std::cout << " - Y_SIZE = " << Y_SIZE << std::endl;
498 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
499 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
500 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
501 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
502 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
503 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
504 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
505 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
506
507 std::cout << std::endl;
508 // Internal and External VCI parameters definition
509 typedef soclib::caba::VciParams<vci_cell_width_int,
510 vci_plen_width,
511 vci_address_width,
512 vci_rerror_width,
513 vci_clen_width,
514 vci_rflag_width,
515 vci_srcid_width,
516 vci_pktid_width,
517 vci_trdid_width,
518 vci_wrplen_width> vci_param_int;
519
520 typedef soclib::caba::VciParams<vci_cell_width_ext,
521 vci_plen_width,
522 vci_address_width,
523 vci_rerror_width,
524 vci_clen_width,
525 vci_rflag_width,
526 vci_srcid_width,
527 vci_pktid_width,
528 vci_trdid_width,
529 vci_wrplen_width> vci_param_ext;
530
531#if USE_OPENMP
532 omp_set_dynamic(false);
533 omp_set_num_threads(threads_nr);
534 std::cerr << "Built with openmp version " << _OPENMP << std::endl;
535#endif
536
537 // Define parameters depending on mesh size
538 size_t x_width;
539 size_t y_width;
540
541#ifdef USE_ALMOS
542 if (X_SIZE == 1) x_width = 0;
543 else if (X_SIZE == 2) x_width = 1;
544 else if (X_SIZE <= 4) x_width = 2;
545 else if (X_SIZE <= 8) x_width = 3;
546 else x_width = 4;
547
548 if (Y_SIZE == 1) y_width = 0;
549 else if (Y_SIZE == 2) y_width = 1;
550 else if (Y_SIZE <= 4) y_width = 2;
551 else if (Y_SIZE <= 8) y_width = 3;
552 else y_width = 4;
553
554#else
555 size_t x_width = X_WIDTH;
556 size_t y_width = Y_WIDTH;
557
558 assert( (X_WIDTH <= 4) and (Y_WIDTH <= 4) and
559 "Up to 256 clusters");
560
561 assert( (X_SIZE <= (1 << X_WIDTH)) and (Y_SIZE <= (1 << Y_WIDTH)) and
562 "The X_WIDTH and Y_WIDTH parameter are insufficient");
563
564#endif
565
566 // index of cluster containing IOs
567 cluster_io_id = 0x00bfc00000ULL >> (vci_address_width - x_width - y_width);
568
569
570 /////////////////////
571 // Mapping Tables
572 /////////////////////
573
574 // internal network
575 MappingTable maptabd(vci_address_width,
576 IntTab(x_width + y_width, 16 - x_width - y_width),
577 IntTab(x_width + y_width, vci_srcid_width - x_width - y_width),
578 0x00FF800000);
579
580 for (size_t x = 0; x < X_SIZE; x++)
581 {
582 for (size_t y = 0; y < Y_SIZE; y++)
583 {
584 sc_uint<vci_address_width> offset;
585 offset = (sc_uint<vci_address_width>)cluster(x,y)
586 << (vci_address_width-x_width-y_width);
587
588 std::ostringstream si;
589 si << "seg_xicu_" << x << "_" << y;
590 maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE,
591 IntTab(cluster(x,y),XICU_TGTID), false));
592
593 std::ostringstream sd;
594 sd << "seg_mdma_" << x << "_" << y;
595 maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE,
596 IntTab(cluster(x,y),MDMA_TGTID), false));
597
598 std::ostringstream sh;
599 sh << "seg_memc_" << x << "_" << y;
600 maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE,
601 IntTab(cluster(x,y),MEMC_TGTID), true));
602
603 if ( cluster(x,y) == cluster_io_id )
604 {
605 maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE,
606 IntTab(cluster(x,y),MTTY_TGTID), false));
607 maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE,
608 IntTab(cluster(x,y),FBUF_TGTID), false));
609 maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE,
610 IntTab(cluster(x,y),BDEV_TGTID), false));
611 maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE,
612 IntTab(cluster(x,y),BROM_TGTID), true));
613 maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE,
614 IntTab(cluster(x,y),MNIC_TGTID), false));
615 maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE,
616 IntTab(cluster(x,y),CDMA_TGTID), false));
617 maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE,
618 IntTab(cluster(x,y),SIMH_TGTID), false));
619 }
620 }
621 }
622 std::cout << maptabd << std::endl;
623
624 // external network
625 MappingTable maptabx(vci_address_width,
626 IntTab(x_width+y_width),
627 IntTab(x_width+y_width),
628 0xFFFF000000ULL);
629
630 for (size_t x = 0; x < X_SIZE; x++)
631 {
632 for (size_t y = 0; y < Y_SIZE ; y++)
633 {
634
635 sc_uint<vci_address_width> offset;
636 offset = (sc_uint<vci_address_width>)cluster(x,y)
637 << (vci_address_width - x_width - y_width);
638
639 std::ostringstream sh;
640 sh << "x_seg_memc_" << x << "_" << y;
641
642 maptabx.add(Segment(sh.str(), MEMC_BASE + offset,
643 MEMC_SIZE, IntTab(cluster(x,y)), false));
644 }
645 }
646 std::cout << maptabx << std::endl;
647
648 ////////////////////
649 // Signals
650 ///////////////////
651
652 sc_clock signal_clk("clk");
653 sc_signal<bool> signal_resetn("resetn");
654
655 // Horizontal inter-clusters DSPIN signals
656 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc =
657 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE, 3);
658 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec =
659 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE, 3);
660 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc =
661 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE, 2);
662 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec =
663 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE, 2);
664
665 // Vertical inter-clusters DSPIN signals
666 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc =
667 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1, 3);
668 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec =
669 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1, 3);
670 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc =
671 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1, 2);
672 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec =
673 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1, 2);
674
675 // Mesh boundaries DSPIN signals
676 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in =
677 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , X_SIZE, Y_SIZE, 4, 3);
678 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out =
679 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", X_SIZE, Y_SIZE, 4, 3);
680 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in =
681 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , X_SIZE, Y_SIZE, 4, 2);
682 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out =
683 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", X_SIZE, Y_SIZE, 4, 2);
684
685 ////////////////////////////
686 // Loader
687 ////////////////////////////
688
689 soclib::common::Loader loader(soft_name);
690
691 typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
692 proc_iss::set_loader(loader);
693
694 ////////////////////////////
695 // Clusters construction
696 ////////////////////////////
697
698 TsarXbarCluster<dspin_cmd_width,
699 dspin_rsp_width,
700 vci_param_int,
701 vci_param_ext> * clusters[X_SIZE][Y_SIZE];
702
703#if USE_OPENMP
704#pragma omp parallel
705 {
706#pragma omp for
707#endif
708 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++)
709 {
710 size_t x = i / Y_SIZE;
711 size_t y = i % Y_SIZE;
712
713#if USE_OPENMP
714#pragma omp critical
715 {
716#endif
717 std::cout << std::endl;
718 std::cout << "Cluster_" << x << "_" << y << std::endl;
719 std::cout << std::endl;
720
721 std::ostringstream sc;
722 sc << "cluster_" << x << "_" << y;
723 clusters[x][y] = new TsarXbarCluster<dspin_cmd_width,
724 dspin_rsp_width,
725 vci_param_int,
726 vci_param_ext>
727 (
728 sc.str().c_str(),
729 NB_PROCS_MAX,
730 NB_TTY_CHANNELS,
731 NB_DMA_CHANNELS,
732 x,
733 y,
734 cluster(x,y),
735 maptabd,
736 maptabx,
737 x_width,
738 y_width,
739 vci_srcid_width - x_width - y_width, // l_id width,
740 MEMC_TGTID,
741 XICU_TGTID,
742 MDMA_TGTID,
743 FBUF_TGTID,
744 MTTY_TGTID,
745 BROM_TGTID,
746 MNIC_TGTID,
747 CDMA_TGTID,
748 BDEV_TGTID,
749 SIMH_TGTID,
750 MEMC_WAYS,
751 MEMC_SETS,
752 L1_IWAYS,
753 L1_ISETS,
754 L1_DWAYS,
755 L1_DSETS,
756 IRQ_PER_PROCESSOR,
757 XRAM_LATENCY,
758 (cluster(x,y) == cluster_io_id),
759 FBUF_X_SIZE,
760 FBUF_Y_SIZE,
761 disk_name,
762 BDEV_SECTOR_SIZE,
763 NB_NIC_CHANNELS,
764 nic_rx_name,
765 nic_tx_name,
766 NIC_TIMEOUT,
767 NB_CMA_CHANNELS,
768 loader,
769 frozen_cycles,
770 debug_from,
771 debug_ok,
772 debug_ok
773 );
774
775#if USE_OPENMP
776 } // end critical
777#endif
778 } // end for
779#if USE_OPENMP
780 }
781#endif
782
783 ///////////////////////////////////////////////////////////////
784 // Net-list
785 ///////////////////////////////////////////////////////////////
786
787 // Clock & RESET
788 for (size_t x = 0; x < (X_SIZE); x++){
789 for (size_t y = 0; y < Y_SIZE; y++){
790 clusters[x][y]->p_clk (signal_clk);
791 clusters[x][y]->p_resetn (signal_resetn);
792 }
793 }
794
795 // Inter Clusters horizontal connections
796 if (X_SIZE > 1){
797 for (size_t x = 0; x < (X_SIZE-1); x++){
798 for (size_t y = 0; y < Y_SIZE; y++){
799 for (size_t k = 0; k < 3; k++){
800 clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]);
801 clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]);
802 clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]);
803 clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]);
804 }
805
806 for (size_t k = 0; k < 2; k++){
807 clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]);
808 clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]);
809 clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]);
810 clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]);
811 }
812 }
813 }
814 }
815 std::cout << std::endl << "Horizontal connections established" << std::endl;
816
817 // Inter Clusters vertical connections
818 if (Y_SIZE > 1) {
819 for (size_t y = 0; y < (Y_SIZE-1); y++){
820 for (size_t x = 0; x < X_SIZE; x++){
821 for (size_t k = 0; k < 3; k++){
822 clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]);
823 clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]);
824 clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]);
825 clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]);
826 }
827
828 for (size_t k = 0; k < 2; k++){
829 clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]);
830 clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]);
831 clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]);
832 clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]);
833 }
834 }
835 }
836 }
837 std::cout << "Vertical connections established" << std::endl;
838
839 // East & West boundary cluster connections
840 for (size_t y = 0; y < Y_SIZE; y++)
841 {
842 for (size_t k = 0; k < 3; k++)
843 {
844 clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in [0][y][WEST][k]);
845 clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]);
846 clusters[X_SIZE-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in [X_SIZE-1][y][EAST][k]);
847 clusters[X_SIZE-1][y]->p_cmd_out[EAST][k](signal_dspin_false_cmd_out[X_SIZE-1][y][EAST][k]);
848 }
849
850 for (size_t k = 0; k < 2; k++)
851 {
852 clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in [0][y][WEST][k]);
853 clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]);
854 clusters[X_SIZE-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in [X_SIZE-1][y][EAST][k]);
855 clusters[X_SIZE-1][y]->p_rsp_out[EAST][k](signal_dspin_false_rsp_out[X_SIZE-1][y][EAST][k]);
856 }
857 }
858
859 // North & South boundary clusters connections
860 for (size_t x = 0; x < X_SIZE; x++)
861 {
862 for (size_t k = 0; k < 3; k++)
863 {
864 clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in [x][0][SOUTH][k]);
865 clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]);
866 clusters[x][Y_SIZE-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in [x][Y_SIZE-1][NORTH][k]);
867 clusters[x][Y_SIZE-1]->p_cmd_out[NORTH][k](signal_dspin_false_cmd_out[x][Y_SIZE-1][NORTH][k]);
868 }
869
870 for (size_t k = 0; k < 2; k++)
871 {
872 clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in [x][0][SOUTH][k]);
873 clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]);
874 clusters[x][Y_SIZE-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in [x][Y_SIZE-1][NORTH][k]);
875 clusters[x][Y_SIZE-1]->p_rsp_out[NORTH][k](signal_dspin_false_rsp_out[x][Y_SIZE-1][NORTH][k]);
876 }
877 }
878 std::cout << "North, South, West, East connections established" << std::endl;
879 std::cout << std::endl;
880
881
882#ifdef WT_IDL
883 std::list<VciCcVCacheWrapper<vci_param_int,
884 dspin_cmd_width,
885 dspin_rsp_width,
886 GdbServer<Mips32ElIss> > * > l1_caches;
887
888 for (size_t x = 0; x < X_SIZE; x++) {
889 for (size_t y = 0; y < Y_SIZE; y++) {
890 for (int proc = 0; proc < NB_PROCS_MAX; proc++) {
891 l1_caches.push_back(clusters[x][y]->proc[proc]);
892 }
893 }
894 }
895
896 for (size_t x = 0; x < X_SIZE; x++) {
897 for (size_t y = 0; y < Y_SIZE; y++) {
898 clusters[x][y]->memc->set_vcache_list(l1_caches);
899 }
900 }
901#endif
902
903
904//#define SC_TRACE
905#ifdef SC_TRACE
906 sc_trace_file * tf = sc_create_vcd_trace_file("my_trace_file");
907
908 if (X_SIZE > 1){
909 for (size_t x = 0; x < (X_SIZE-1); x++){
910 for (size_t y = 0; y < Y_SIZE; y++){
911 for (size_t k = 0; k < 3; k++){
912 signal_dspin_h_cmd_inc[x][y][k].trace(tf, "dspin_h_cmd_inc");
913 signal_dspin_h_cmd_dec[x][y][k].trace(tf, "dspin_h_cmd_dec");
914 }
915
916 for (size_t k = 0; k < 2; k++){
917 signal_dspin_h_rsp_inc[x][y][k].trace(tf, "dspin_h_rsp_inc");
918 signal_dspin_h_rsp_dec[x][y][k].trace(tf, "dspin_h_rsp_dec");
919 }
920 }
921 }
922 }
923
924 if (Y_SIZE > 1) {
925 for (size_t y = 0; y < (Y_SIZE-1); y++){
926 for (size_t x = 0; x < X_SIZE; x++){
927 for (size_t k = 0; k < 3; k++){
928 signal_dspin_v_cmd_inc[x][y][k].trace(tf, "dspin_v_cmd_inc");
929 signal_dspin_v_cmd_dec[x][y][k].trace(tf, "dspin_v_cmd_dec");
930 }
931
932 for (size_t k = 0; k < 2; k++){
933 signal_dspin_v_rsp_inc[x][y][k].trace(tf, "dspin_v_rsp_inc");
934 signal_dspin_v_rsp_dec[x][y][k].trace(tf, "dspin_v_rsp_dec");
935 }
936 }
937 }
938 }
939
940 for (size_t x = 0; x < (X_SIZE); x++){
941 for (size_t y = 0; y < Y_SIZE; y++){
942 std::ostringstream signame;
943 signame << "cluster" << x << "_" << y;
944 clusters[x][y]->trace(tf, signame.str());
945 }
946 }
947#endif
948
949
950 ////////////////////////////////////////////////////////
951 // Simulation
952 ///////////////////////////////////////////////////////
953
954 sc_start(sc_core::sc_time(0, SC_NS));
955 signal_resetn = false;
956
957 // network boundaries signals
958 for (size_t x = 0; x < X_SIZE ; x++){
959 for (size_t y = 0; y < Y_SIZE ; y++){
960 for (size_t a = 0; a < 4; a++){
961 for (size_t k = 0; k < 3; k++){
962 signal_dspin_false_cmd_in [x][y][a][k].write = false;
963 signal_dspin_false_cmd_in [x][y][a][k].read = true;
964 signal_dspin_false_cmd_out[x][y][a][k].write = false;
965 signal_dspin_false_cmd_out[x][y][a][k].read = true;
966 }
967 for (size_t k = 0; k < 2; k++){
968 signal_dspin_false_rsp_in [x][y][a][k].write = false;
969 signal_dspin_false_rsp_in [x][y][a][k].read = true;
970 signal_dspin_false_rsp_out[x][y][a][k].write = false;
971 signal_dspin_false_rsp_out[x][y][a][k].read = true;
972 }
973 }
974 }
975 }
976
977 sc_start(sc_core::sc_time(1, SC_NS));
978 signal_resetn = true;
979
980 if (debug_ok) {
981 #if USE_OPENMP
982 assert(false && "OPEN MP should not be used with debug because of its traces");
983 #endif
984
985 if (gettimeofday(&t1, NULL) != 0) {
986 perror("gettimeofday");
987 return EXIT_FAILURE;
988 }
989
990 for (int64_t n = 1; n < ncycles && !stop_called; n++)
991 {
992 if ((n % max_cycles) == 0)
993 {
994
995 if (gettimeofday(&t2, NULL) != 0)
996 {
997 perror("gettimeofday");
998 return EXIT_FAILURE;
999 }
1000
1001 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
1002 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
1003 std::cerr << "platform clock frequency " << (double) max_cycles / (double) (ms2 - ms1) << "Khz" << std::endl;
1004
1005 if (gettimeofday(&t1, NULL) != 0)
1006 {
1007 perror("gettimeofday");
1008 return EXIT_FAILURE;
1009 }
1010 }
1011
1012
1013 if (n == reset_counters) {
1014 for (size_t x = 0; x < (X_SIZE); x++) {
1015 for (size_t y = 0; y < Y_SIZE; y++) {
1016 clusters[x][y]->memc->reset_counters();
1017 }
1018 }
1019 }
1020
1021 if (n == dump_counters) {
1022 for (size_t x = 0; x < (X_SIZE); x++) {
1023 for (size_t y = 0; y < Y_SIZE; y++) {
1024 clusters[x][y]->memc->print_stats(true, false);
1025 }
1026 }
1027 }
1028
1029 if ((n > debug_from) and (n % debug_period == 0))
1030 {
1031 std::cout << "****************** cycle " << std::dec << n ;
1032 std::cout << "************************************************" << std::endl;
1033
1034 for (size_t x = 0; x < X_SIZE ; x++){
1035 for (size_t y = 0; y < Y_SIZE ; y++){
1036 for (int proc = 0; proc < NB_PROCS_MAX; proc++) {
1037 std::ostringstream proc_signame;
1038 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc ;
1039 std::ostringstream p2m_signame;
1040 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " P2M";
1041 std::ostringstream m2p_signame;
1042 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " M2P";
1043
1044 clusters[x][y]->signal_vci_ini_proc[proc].print_trace(proc_signame.str());
1045 clusters[x][y]->signal_dspin_p2m_proc[proc].print_trace(p2m_signame.str());
1046 clusters[x][y]->signal_dspin_m2p_proc[proc].print_trace(m2p_signame.str());
1047 clusters[x][y]->proc[proc]->print_trace();
1048 }
1049 std::ostringstream smemc;
1050 smemc << "[SIG]MEMC_" << x << "_" << y;
1051 std::ostringstream sxram;
1052 sxram << "[SIG]XRAM_" << x << "_" << y;
1053 std::ostringstream sm2p;
1054 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P";
1055 std::ostringstream sp2m;
1056 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M";
1057
1058 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
1059 clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
1060 clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());
1061 clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());
1062 clusters[x][y]->memc->print_trace();
1063 }
1064 }
1065 }
1066 sc_start(sc_core::sc_time(1, SC_NS));
1067 }
1068 }
1069 else {
1070 int64_t n = 0;
1071 while (!stop_called && n != ncycles) {
1072 if (gettimeofday(&t1, NULL) != 0) {
1073 perror("gettimeofday");
1074 return EXIT_FAILURE;
1075 }
1076 int64_t nb_cycles = min(max_cycles, ncycles - n);
1077 if (do_reset_counters) {
1078 nb_cycles = min(nb_cycles, reset_counters - n);
1079 }
1080 if (do_dump_counters) {
1081 nb_cycles = min(nb_cycles, dump_counters - n);
1082 }
1083
1084 sc_start(sc_core::sc_time(nb_cycles, SC_NS));
1085 n += nb_cycles;
1086
1087 if (do_reset_counters && n == reset_counters) {
1088 // Reseting counters
1089 for (size_t x = 0; x < (X_SIZE); x++) {
1090 for (size_t y = 0; y < Y_SIZE; y++) {
1091 clusters[x][y]->memc->reset_counters();
1092 }
1093 }
1094 do_reset_counters = false;
1095 }
1096
1097 if (do_dump_counters && n == dump_counters) {
1098 // Dumping counters
1099 for (size_t x = 0; x < (X_SIZE); x++) {
1100 for (size_t y = 0; y < Y_SIZE; y++) {
1101 clusters[x][y]->memc->print_stats(true, false);
1102 }
1103 }
1104 do_dump_counters = false;
1105 }
1106
1107
1108 if (gettimeofday(&t2, NULL) != 0) {
1109 perror("gettimeofday");
1110 return EXIT_FAILURE;
1111 }
1112 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
1113 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
1114 std::cerr << std::dec << "cycle " << n << " platform clock frequency " << (double) nb_cycles / (double) (ms2 - ms1) << "Khz" << std::endl;
1115 }
1116 }
1117
1118
1119 // Free memory
1120 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++)
1121 {
1122 size_t x = i / Y_SIZE;
1123 size_t y = i % Y_SIZE;
1124 delete clusters[x][y];
1125 }
1126
1127 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE, 3);
1128 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE, 3);
1129 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE, 2);
1130 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE, 2);
1131 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1, 3);
1132 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1, 3);
1133 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1, 2);
1134 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1, 2);
1135 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_in, X_SIZE, Y_SIZE, 4, 3);
1136 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_out, X_SIZE, Y_SIZE, 4, 3);
1137 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_in, X_SIZE, Y_SIZE, 4, 2);
1138 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_out, X_SIZE, Y_SIZE, 4, 2);
1139
1140 return EXIT_SUCCESS;
1141}
1142
1143
1144void handler(int dummy = 0) {
1145 stop_called = true;
1146 sc_stop();
1147}
1148
1149void voidhandler(int dummy = 0) {}
1150
1151int sc_main (int argc, char *argv[])
1152{
1153 signal(SIGINT, handler);
1154 signal(SIGPIPE, voidhandler);
1155
1156 try {
1157 return _main(argc, argv);
1158 } catch (std::exception &e) {
1159 std::cout << e.what() << std::endl;
1160 } catch (...) {
1161 std::cout << "Unknown exception occured" << std::endl;
1162 throw;
1163 }
1164 return 1;
1165}
1166
1167
1168// Local Variables:
1169// tab-width: 3
1170// c-basic-offset: 3
1171// c-file-offsets:((innamespace . 0)(inline-open . 0))
1172// indent-tabs-mode: nil
1173// End:
1174
1175// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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