1 | /* -*- c++ -*- |
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2 | * |
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3 | * File : dspin_router_tsar.cpp |
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4 | * Copyright (c) UPMC, Lip6 |
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5 | * Authors : Alain Greiner, Abbas Sheibanyrad, Ivan Miro, Zhen Zhang |
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6 | * |
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7 | * SOCLIB_LGPL_HEADER_BEGIN |
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8 | * |
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9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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10 | * |
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11 | * SoCLib is free software; you can redistribute it and/or modify it |
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12 | * under the terms of the GNU Lesser General Public License as published |
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13 | * by the Free Software Foundation; version 2.1 of the License. |
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14 | * |
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15 | * SoCLib is distributed in the hope that it will be useful, but |
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16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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18 | * Lesser General Public License for more details. |
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19 | * |
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20 | * You should have received a copy of the GNU Lesser General Public |
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21 | * License along with SoCLib; if not, write to the Free Software |
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22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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23 | * 02110-1301 USA |
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24 | * |
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25 | * SOCLIB_LGPL_HEADER_END |
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26 | * |
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27 | */ |
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28 | |
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29 | //////////////////////////////////////////////////////////////////////////////// |
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30 | // This component implements a variant of the standard (SocLib) DSPIN router: |
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31 | // The routing function has been modified to handle the special case of |
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32 | // cluster_iob0 (containing component IOB0) and cluster_iob1 (containing |
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33 | // component IOB1). In those two cluster, the response router must decode |
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34 | // both the SRCID global bits AND the SRCID local bits to distinguish |
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35 | // between the IOB and MEMC initiators. |
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36 | // This component contains the following modifications: |
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37 | // - 4 new constructor arguments |
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38 | // - 6 new member variables |
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39 | // - a modified routing function |
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40 | //////////////////////////////////////////////////////////////////////////////// |
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41 | |
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42 | #include "../include/dspin_router_tsar.h" |
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43 | |
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44 | namespace soclib { namespace caba { |
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45 | |
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46 | using namespace soclib::common; |
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47 | using namespace soclib::caba; |
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48 | |
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49 | #define tmpl(x) template<int flit_width> x DspinRouterTsar<flit_width> |
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50 | |
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51 | //////////////////////////////////////////////// |
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52 | // constructor |
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53 | //////////////////////////////////////////////// |
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54 | tmpl(/**/)::DspinRouterTsar( |
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55 | sc_module_name name, |
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56 | const size_t x, // x coordinate |
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57 | const size_t y, // y cordinate |
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58 | const size_t x_width, // x field width in first flit |
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59 | const size_t y_width, // y field width in first flit |
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60 | const size_t in_fifo_depth, // input fifo depth |
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61 | const size_t out_fifo_depth, // output fifo depth |
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62 | |
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63 | const bool is_iob0, // cluster contains iob0 |
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64 | const bool is_iob1, // cluster contains iob1 |
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65 | const bool is_rsp, // only response router is modified |
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66 | const size_t l_width) // local field srcid width |
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67 | : soclib::caba::BaseModule(name), |
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68 | |
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69 | p_clk( "p_clk" ), |
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70 | p_resetn( "p_resetn" ), |
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71 | p_in( alloc_elems<DspinInput<flit_width> >("p_in", 5) ), |
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72 | p_out( alloc_elems<DspinOutput<flit_width> >("p_out", 5) ), |
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73 | |
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74 | r_alloc_out( alloc_elems<sc_signal<bool> >("r_alloc_out", 5)), |
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75 | r_index_out( soclib::common::alloc_elems<sc_signal<size_t> >("r_index_out", 5)), |
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76 | r_fsm_in( alloc_elems<sc_signal<int> >("r_fsm_in", 5)), |
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77 | r_index_in( alloc_elems<sc_signal<size_t> >("r_index_in", 5)), |
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78 | |
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79 | m_local_x( x ), |
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80 | m_local_y( y ), |
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81 | |
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82 | m_x_width( x_width ), |
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83 | m_x_shift( flit_width - x_width ), |
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84 | m_x_mask( (0x1 << x_width) - 1 ), |
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85 | |
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86 | m_y_width( y_width ), |
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87 | m_y_shift( flit_width - x_width - y_width ), |
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88 | m_y_mask( (0x1 << y_width) - 1 ), |
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89 | |
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90 | m_l_width( l_width ), |
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91 | m_l_shift( flit_width - x_width - y_width - l_width ), |
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92 | m_l_mask( (0x1 << l_width) - 1 ), |
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93 | |
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94 | m_is_iob0( is_iob0 ), |
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95 | m_is_iob1( is_iob1 ), |
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96 | m_is_rsp( is_rsp ) |
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97 | |
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98 | { |
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99 | std::cout << " - Building DspinRouterTsar : " << name << std::endl; |
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100 | |
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101 | SC_METHOD (transition); |
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102 | dont_initialize(); |
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103 | sensitive << p_clk.pos(); |
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104 | |
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105 | SC_METHOD (genMoore); |
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106 | dont_initialize(); |
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107 | sensitive << p_clk.neg(); |
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108 | |
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109 | r_fifo_in = (GenericFifo<internal_flit_t>*) |
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110 | malloc(sizeof(GenericFifo<internal_flit_t>)*5); |
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111 | r_fifo_out = (GenericFifo<internal_flit_t>*) |
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112 | malloc(sizeof(GenericFifo<internal_flit_t>)*5); |
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113 | |
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114 | for( size_t i = 0 ; i < 5 ; i++ ) |
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115 | { |
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116 | std::ostringstream stri; |
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117 | stri << "r_in_fifo_" << i; |
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118 | new(&r_fifo_in[i]) |
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119 | GenericFifo<internal_flit_t >(stri.str(), in_fifo_depth); |
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120 | |
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121 | std::ostringstream stro; |
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122 | stro << "r_out_fifo_" << i; |
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123 | new(&r_fifo_out[i]) |
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124 | GenericFifo<internal_flit_t >(stro.str(), out_fifo_depth); |
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125 | } |
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126 | } // end constructor |
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127 | |
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128 | ////////////////////////////////////////////////// |
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129 | tmpl(size_t)::route( sc_uint<flit_width> data ) |
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130 | { |
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131 | size_t xdest = (size_t)(data >> m_x_shift) & m_x_mask; |
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132 | size_t ydest = (size_t)(data >> m_y_shift) & m_y_mask; |
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133 | size_t ldest = (size_t)(data >> m_l_shift) & m_l_mask; |
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134 | |
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135 | if (xdest < m_local_x ) return DSPIN_WEST; |
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136 | else if (xdest > m_local_x ) return DSPIN_EAST; |
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137 | else if (ydest < m_local_y ) return DSPIN_SOUTH; |
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138 | else if (ydest > m_local_y ) return DSPIN_NORTH; |
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139 | else // handling IOB0 & IOB1 special cases |
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140 | { |
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141 | if (m_is_rsp and m_is_iob0 and (ldest > 0xA)) return DSPIN_WEST; |
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142 | else if (m_is_rsp and m_is_iob1 and (ldest > 0xA)) return DSPIN_EAST; |
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143 | else return DSPIN_LOCAL; |
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144 | } |
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145 | } // end route() |
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146 | |
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147 | ///////////////////////// |
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148 | tmpl(void)::print_trace() |
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149 | { |
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150 | const char* port_name[] = {"NORTH","SOUTH","EAST ","WEST ","LOCAL"}; |
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151 | |
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152 | std::cout << "DSPIN_ROUTER " << name() << std::hex; |
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153 | for ( size_t out=0 ; out<5 ; out++) // loop on output ports |
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154 | { |
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155 | if ( r_alloc_out[out].read() ) |
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156 | { |
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157 | int in = r_index_out[out]; |
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158 | std::cout << " / " << port_name[in] << " -> " << port_name[out] ; |
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159 | } |
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160 | } |
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161 | std::cout << std::endl; |
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162 | } |
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163 | |
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164 | //////////////////////// |
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165 | tmpl(void)::transition() |
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166 | { |
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167 | // Long wires connecting input and output ports |
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168 | size_t req_in[5]; // input ports -> output ports |
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169 | size_t get_out[5]; // output ports -> input ports |
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170 | bool put_in[5]; // input ports -> output ports |
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171 | internal_flit_t flit_in[5]; // input ports -> output ports |
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172 | |
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173 | // control signals for the input fifos |
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174 | bool fifo_in_write[5]; |
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175 | bool fifo_in_read[5]; |
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176 | internal_flit_t fifo_in_wdata[5]; |
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177 | |
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178 | // control signals for the output fifos |
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179 | bool fifo_out_write[5]; |
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180 | bool fifo_out_read[5]; |
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181 | internal_flit_t fifo_out_wdata[5]; |
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182 | |
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183 | // Reset |
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184 | if ( p_resetn == false ) |
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185 | { |
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186 | for(size_t i = 0 ; i < 5 ; i++) |
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187 | { |
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188 | r_alloc_out[i] = false; |
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189 | r_index_out[i] = 0; |
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190 | r_index_in[i] = 0; |
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191 | r_fsm_in[i] = INFSM_IDLE; |
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192 | r_fifo_in[i].init(); |
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193 | r_fifo_out[i].init(); |
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194 | } |
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195 | return; |
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196 | } |
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197 | |
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198 | // fifos signals default values |
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199 | for(size_t i = 0 ; i < 5 ; i++) |
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200 | { |
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201 | fifo_in_read[i] = false; |
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202 | fifo_in_write[i] = p_in[i].write.read(); |
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203 | fifo_in_wdata[i].data = p_in[i].data.read(); |
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204 | fifo_in_wdata[i].eop = p_in[i].eop.read(); |
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205 | |
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206 | fifo_out_read[i] = p_out[i].read.read(); |
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207 | fifo_out_write[i] = false; |
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208 | } |
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209 | |
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210 | // loop on the output ports: |
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211 | // compute get_out[j] depending on the output port state |
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212 | // and combining fifo_out[j].wok and r_alloc_out[j] |
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213 | for ( size_t j = 0 ; j < 5 ; j++ ) |
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214 | { |
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215 | if( r_alloc_out[j].read() and (r_fifo_out[j].wok()) ) |
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216 | { |
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217 | get_out[j] = r_index_out[j].read(); |
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218 | } |
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219 | else |
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220 | { |
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221 | get_out[j] = 0xFFFFFFFF; |
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222 | } |
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223 | } |
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224 | |
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225 | // loop on the input ports : |
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226 | // The port state is defined by r_fsm_in[i], r_index_in[i] |
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227 | // The req_in[i] computation implements the X-FIRST algorithm. |
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228 | // Both put_in[i] and req_in[i] depend on the input port state. |
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229 | |
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230 | for ( size_t i = 0 ; i < 5 ; i++ ) |
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231 | { |
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232 | switch ( r_fsm_in[i].read() ) |
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233 | { |
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234 | case INFSM_IDLE: // no output port allocated |
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235 | { |
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236 | put_in[i] = false; |
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237 | if ( r_fifo_in[i].rok() ) // packet available in input fifo |
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238 | { |
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239 | req_in[i] = route( r_fifo_in[i].read().data ); |
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240 | r_index_in[i] = req_in[i]; |
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241 | r_fsm_in[i] = INFSM_REQ; |
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242 | } |
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243 | else |
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244 | { |
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245 | req_in[i] = 0xFFFFFFFF; // no request |
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246 | } |
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247 | break; |
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248 | } |
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249 | case INFSM_REQ: // waiting output port allocation |
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250 | { |
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251 | flit_in[i] = r_fifo_in[i].read(); |
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252 | put_in[i] = r_fifo_in[i].rok(); |
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253 | req_in[i] = r_index_in[i]; |
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254 | if ( get_out[r_index_in[i].read()] == i ) // first flit transfered |
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255 | { |
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256 | if ( r_fifo_in[i].read().eop ) r_fsm_in[i] = INFSM_IDLE; |
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257 | else r_fsm_in[i] = INFSM_ALLOC; |
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258 | } |
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259 | break; |
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260 | } |
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261 | case INFSM_ALLOC: // output port allocated |
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262 | { |
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263 | flit_in[i] = r_fifo_in[i].read(); |
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264 | put_in[i] = r_fifo_in[i].rok(); |
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265 | req_in[i] = 0xFFFFFFFF; // no request |
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266 | if ( r_fifo_in[i].read().eop and r_fifo_in[i].rok() and |
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267 | (get_out[r_index_in[i].read()] == i) ) // last flit transfered |
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268 | { |
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269 | r_fsm_in[i] = INFSM_IDLE; |
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270 | } |
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271 | break; |
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272 | } |
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273 | } // end switch |
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274 | } // end for input ports |
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275 | |
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276 | // loop on the output ports : |
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277 | // The r_alloc_out[j] and r_index_out[j] computation |
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278 | // implements the round-robin allocation policy. |
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279 | // These two registers implement a 10 states FSM. |
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280 | for( size_t j = 0 ; j < 5 ; j++ ) |
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281 | { |
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282 | if( not r_alloc_out[j].read() ) // not allocated: possible new allocation |
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283 | { |
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284 | for( size_t k = r_index_out[j].read() + 1 ; |
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285 | k < (r_index_out[j] + 6) ; k++) |
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286 | { |
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287 | size_t i = k % 5; |
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288 | |
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289 | if( req_in[i] == j ) |
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290 | { |
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291 | r_alloc_out[j] = true; |
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292 | r_index_out[j] = i; |
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293 | break; |
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294 | } |
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295 | } // end loop on input ports |
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296 | } |
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297 | else // allocated: possible desallocation |
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298 | { |
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299 | if ( flit_in[r_index_out[j]].eop and |
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300 | r_fifo_out[j].wok() and |
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301 | put_in[r_index_out[j]] ) |
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302 | { |
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303 | r_alloc_out[j] = false; |
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304 | } |
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305 | } |
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306 | } // end loop on output ports |
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307 | |
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308 | // loop on input ports : |
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309 | // fifo_in_read[i] computation (get data from fifo_in[i] |
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310 | // (computed here because it depends on get_out[]) |
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311 | for( size_t i = 0 ; i < 5 ; i++ ) |
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312 | { |
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313 | if ( r_fsm_in[i].read() != INFSM_IDLE ) |
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314 | { |
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315 | fifo_in_read[i] = (get_out[r_index_in[i].read()] == i); |
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316 | } |
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317 | else |
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318 | { |
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319 | fifo_in_read[i] = false; |
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320 | } |
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321 | } // end loop on input ports |
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322 | |
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323 | // loop on the output ports : |
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324 | // The fifo_out_write[j] and fifo_out_wdata[j] computation |
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325 | // implements the output port mux. |
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326 | for( size_t j = 0 ; j < 5 ; j++ ) |
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327 | { |
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328 | if( r_alloc_out[j] ) // output port allocated |
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329 | { |
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330 | fifo_out_write[j] = put_in[r_index_out[j]]; |
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331 | fifo_out_wdata[j] = flit_in[r_index_out[j]]; |
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332 | } |
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333 | } // end loop on the output ports |
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334 | |
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335 | // FIFOS update |
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336 | for(size_t i = 0 ; i < 5 ; i++) |
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337 | { |
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338 | r_fifo_in[i].update(fifo_in_read[i], |
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339 | fifo_in_write[i], |
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340 | fifo_in_wdata[i]); |
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341 | r_fifo_out[i].update(fifo_out_read[i], |
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342 | fifo_out_write[i], |
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343 | fifo_out_wdata[i]); |
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344 | } |
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345 | } // end transition |
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346 | |
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347 | //////////////////////////////// |
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348 | // genMoore |
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349 | //////////////////////////////// |
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350 | tmpl(void)::genMoore() |
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351 | { |
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352 | for(size_t i = 0 ; i < 5 ; i++) |
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353 | { |
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354 | // input ports : READ signals |
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355 | p_in[i].read = r_fifo_in[i].wok(); |
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356 | |
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357 | // output ports : DATA & WRITE signals |
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358 | p_out[i].data = r_fifo_out[i].read().data; |
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359 | p_out[i].eop = r_fifo_out[i].read().eop; |
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360 | p_out[i].write = r_fifo_out[i].rok(); |
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361 | } |
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362 | } // end genMoore |
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363 | |
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364 | }} // end namespace |
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365 | |
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366 | // Local Variables: |
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367 | // tab-width: 4 |
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368 | // c-basic-offset: 4 |
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369 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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370 | // indent-tabs-mode: nil |
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371 | // End: |
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372 | |
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373 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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