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source: branches/fault_tolerance/platform/tsar_generic_iob/top.cpp @ 698

Last change on this file since 698 was 695, checked in by cfuguet, 12 years ago

branches/fault-tolerance/tsar_generic_iob:

Introducing multi-tty component in all clusters for debug. Number of channels is set by a proprocessor contant in the tsar_iob_cluster.h file. Number of channels can be 0 if tty isn't needed.

Reducing number of parameters for cluster class. Using constants defined in hard_config.h instead.

File size: 59.8 KB

Line
1	///////////////////////////////////////////////////////////////////////////////
2	// File: top.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : august 2013
6	// This program is released under the GNU public license
7	//
8	// Modified by: Cesar Fuguet
9	// Modified on: mars 2014
10	///////////////////////////////////////////////////////////////////////////////
11	// This file define a generic TSAR architecture with an IO network emulating
12	// an external bus (i.e. Hypertransport) to access external peripherals:
13	//
14	// - BROM : boot ROM
15	// - FBUF : Frame Buffer
16	// - MTTY : multi TTY (up to 15 channels)
17	// - MNIC : Network controller (up to 2 channels)
18	// - CDMA : Chained Buffer DMA controller (up to 4 channels)
19	// - BDEV : Dlock Device controler (1 channel)
20	//
21	// The internal physical address space is 40 bits.
22	//
23	// It contains a 2D mesh of XMAX*YMAX clusters, and the cluster index
24	// is encoded on 8 bits (X_WIDTH = 4 / Y_WIDTH = 4) whatever the mesh size.
25	//
26	// It contains 3 networks:
27	//
28	// 1) the INT network supports Read/Write transactions
29	// between processors and L2 caches or peripherals.
30	// (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits)
31	// It supports also coherence transactions between L1 & L2 caches.
32	// 3) the RAM network is emulating the 3D network between L2 caches
33	// and L3 caches, and is implemented as a 2D mesh between the L2 caches,
34	// the two IO bridges and the physical RAMs disributed in all clusters.
35	// (VCI ADDRESS = 40 bits / VCI DATA = 64 bits)
36	// 4) the IOX network connects the two IO bridge components to the
37	// 6 external peripheral controllers.
38	// (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits)
39	//
40	// The external peripherals IRQs are connected to the XICU component
41	// in cluster(0,0): therefore, the number of channels for the external
42	// peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports...
43	//
44	// In cluster(0,0), the XICU HWI input ports are connected as follow:
45	// - IRQ_IN[0] to IRQ_IN[7] grounded (reserved for PTI or SWI)
46	// - IRQ_IN[8] to IRQ_IN[9] are connected to 2 NIC_RX channels.
47	// - IRQ_IN[10] to IRQ_IN[11] are connected to 2 NIC_TX channels.
48	// - IRQ_IN[12] to IRQ_IN[15] are connected to 4 CDMA channels
49	// - IRQ_IN[16] to IRQ_IN[30] are connected to 15 TTY channels
50	// - IRQ_IN[31] is connected to BDEV
51	// In other clusters, the XICU HWI input ports are grounded.
52	//
53	// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1)
54	// contain an extra IO bridge component. These IOB0 & IOB1 components are
55	// connected to the three networks (INT, RAM, IOX).
56	// The number of clusters cannot be larger than 256.
57	// The number of processors per cluster cannot be larger than 4.
58	//
59	// - It uses two dspin_local_crossbar per cluster to implement the
60	// local interconnect correponding to the INT network.
61	// - It uses two dspin_local_crossbar per cluster to implement the
62	// local interconnect correponding to the coherence INT network.
63	// - It uses two virtual_dspin_router per cluster to implement
64	// the INT network (routing both the direct and coherence trafic).
65	// - It uses two dspin_router per cluster to implement the RAM network.
66	// - It uses the vci_cc_vcache_wrapper.
67	// - It uses the vci_mem_cache.
68	// - It contains one vci_xicu and one vci_multi_dma per cluster.
69	// - It contains one vci_simple ram per cluster to model the L3 cache.
70	//
71	// The TsarIobCluster component is defined in files
72	// tsar_iob_cluster.* (with * = cpp, h, sd)
73	//
74	// The main hardware parameters must be defined in the hard_config.h file :
75	// - XMAX : number of clusters in a row (power of 2)
76	// - YMAX : number of clusters in a column (power of 2)
77	// - CLUSTER_SIZE : size of the segment allocated to a cluster
78	// - NB_PROCS_MAX : number of processors per cluster (power of 2)
79	// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9)
80	// - NB_TTY_CHANNELS : number of TTY channels in I/O network (< 16)
81	// - NB_NIC_CHANNELS : number of NIC channels in I/O network (< 9)
82	//
83	// Some secondary hardware parameters must be defined in this top.cpp file:
84	// - XRAM_LATENCY : external ram latency
85	// - MEMC_WAYS : L2 cache number of ways
86	// - MEMC_SETS : L2 cache number of sets
87	// - L1_IWAYS
88	// - L1_ISETS
89	// - L1_DWAYS
90	// - L1_DSETS
91	// - FBUF_X_SIZE : width of frame buffer (pixels)
92	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
93	// - BDEV_SECTOR_SIZE : block size for block drvice
94	// - BDEV_IMAGE_NAME : file pathname for block device
95	// - NIC_RX_NAME : file pathname for NIC received packets
96	// - NIC_TX_NAME : file pathname for NIC transmited packets
97	// - NIC_TIMEOUT : max number of cycles before closing a container
98	//
99	// General policy for 40 bits physical address decoding:
100	// All physical segments base addresses are multiple of 1 Mbytes
101	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
102	// The (x_width + y_width) MSB bits (left aligned) define
103	// the cluster index, and the LADR bits define the local index:
104	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
105	// \|x_width\|y_width\|---\| 8 \| 24 \|
106	//
107	// General policy for 14 bits SRCID decoding:
108	// Each component is identified by (x_id, y_id, l_id) tuple.
109	// \| X_ID \| Y_ID \|---\| L_ID \|
110	// \|x_width\|y_width\|---\| 6 \|
111	/////////////////////////////////////////////////////////////////////////
112
113	#include <systemc>
114	#include <sys/time.h>
115	#include <iostream>
116	#include <sstream>
117	#include <cstdlib>
118	#include <cstdarg>
119	#include <stdint.h>
120	#include <string>
121
122	#include "gdbserver.h"
123	#include "mapping_table.h"
124
125	#include "tsar_iob_cluster.h"
126	#include "vci_chbuf_dma.h"
127	#include "vci_multi_tty.h"
128	#include "vci_multi_nic.h"
129	#include "vci_block_device_tsar.h"
130	#include "vci_framebuffer.h"
131	#include "vci_iox_network.h"
132
133	#include "alloc_elems.h"
134	#include "hard_config.h"
135
136	////////////////////////////////////////////////////////////////////////
137	// Parallelization
138	////////////////////////////////////////////////////////////////////////
139
140	#define USE_OPENMP 0
141
142	#if USE_OPENMP
143	#include <omp.h>
144	#endif
145
146	////////////////////////////////////////////////////////////////////////
147	// DSPIN parameters
148	////////////////////////////////////////////////////////////////////////
149
150	#define dspin_int_cmd_width 39
151	#define dspin_int_rsp_width 32
152
153	#define dspin_ram_cmd_width 64
154	#define dspin_ram_rsp_width 64
155
156	////////////////////////////////////////////////////////////////////////
157	// VCI fields width for the 3 VCI networks
158	////////////////////////////////////////////////////////////////////////
159
160	#define vci_cell_width_int 4
161	#define vci_cell_width_ext 8
162
163	#define vci_plen_width 8
164	#define vci_address_width 40
165	#define vci_rerror_width 1
166	#define vci_clen_width 1
167	#define vci_rflag_width 1
168	#define vci_srcid_width 14
169	#define vci_pktid_width 4
170	#define vci_trdid_width 4
171	#define vci_wrplen_width 1
172
173	////////////////////////////////////////////////////////////////////////
174	// Secondary Hardware Parameters values
175	////////////////////////////////////////////////////////////////////////
176
177	#define XRAM_LATENCY 0
178
179	#define MEMC_WAYS 16
180	#define MEMC_SETS 256
181
182	#define L1_IWAYS 4
183	#define L1_ISETS 64
184
185	#define L1_DWAYS 4
186	#define L1_DSETS 64
187
188	#define FBUF_X_SIZE 128
189	#define FBUF_Y_SIZE 128
190
191	#define BDEV_SECTOR_SIZE 512
192	#define BDEV_IMAGE_NAME "/dev/null"
193
194	#define NIC_RX_NAME "/dev/null"
195	#define NIC_TX_NAME "/dev/null"
196	#define NIC_TIMEOUT 10000
197
198	#define cluster(x,y) TsarIobClusterType::clusterId((x),(y))
199
200	////////////////////////////////////////////////////////////////////////
201	// Software to be loaded in ROM & RAM
202	////////////////////////////////////////////////////////////////////////
203
204	#define BOOT_SOFT_NAME "/dev/null"
205
206	////////////////////////////////////////////////////////////////////////
207	// DEBUG Parameters default values
208	////////////////////////////////////////////////////////////////////////
209
210	#define MAX_FROZEN_CYCLES 10000
211
212	////////////////////////////////////////////////////////////////////////
213	// SRCID definition
214	////////////////////////////////////////////////////////////////////////
215	// All initiators are in the same indexing space (14 bits).
216	// The SRCID is structured in two fields:
217	// - The 10 MSB bits define the cluster index (left aligned)
218	// - The 4 LSB bits define the local index.
219	// Two different initiators cannot have the same SRCID, but a given
220	// initiator can have two alias SRCIDs:
221	// - Internal initiators (procs, mdma) are replicated in all clusters,
222	// and each initiator has one single SRCID.
223	// - External initiators (bdev, cdma) are not replicated, but can be
224	// accessed in 2 clusters : cluster_iob0 and cluster_iob1.
225	// They have the same local index, but two different cluster indexes.
226	// As cluster_iob0 and cluster_iob1 contain both internal initiators
227	// and external initiators, they must have different local indexes.
228	// Consequence: For a local interconnect, the INI_ID port index
229	// is NOT equal to the SRCID local index, and the local interconnect
230	// must make a translation: SRCID => INI_ID (port index)
231	////////////////////////////////////////////////////////////////////////
232
233	#define PROC_LOCAL_SRCID 0x0 // from 0 to 7
234	#define MDMA_LOCAL_SRCID 0x8
235	#define IOBX_LOCAL_SRCID 0x9
236	#define MEMC_LOCAL_SRCID 0xA
237	#define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar
238	#define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar
239
240	///////////////////////////////////////////////////////////////////////
241	// TGT_ID and INI_ID port indexing for I0X local interconnect
242	///////////////////////////////////////////////////////////////////////
243
244	#define IOX_IOB0_TGT_ID 0 // don't change this value
245	#define IOX_IOB1_TGT_ID 1 // don't change this value
246	#define IOX_FBUF_TGT_ID 2
247	#define IOX_BDEV_TGT_ID 3
248	#define IOX_MNIC_TGT_ID 4
249	#define IOX_CDMA_TGT_ID 5
250	#define IOX_MTTY_TGT_ID 6
251
252	#define IOX_IOB0_INI_ID 0 // Don't change this value
253	#define IOX_IOB1_INI_ID 1 // Don't change this value
254	#define IOX_BDEV_INI_ID 2
255	#define IOX_CDMA_INI_ID 3
256
257	////////////////////////////////////////////////////////////////////////
258	int _main(int argc, char *argv[]) {
259	using namespace sc_core;
260	using namespace soclib::caba;
261	using namespace soclib::common;
262
263	char soft_name[256] = BOOT_SOFT_NAME; // path: binary code
264	uint64_t ncycles = 1000000000; // simulated cycles
265	char disk_name[256] = BDEV_IMAGE_NAME; // path: disk image
266	char nic_rx_name[256] = NIC_RX_NAME; // path: rx packets file
267	char nic_tx_name[256] = NIC_TX_NAME; // path: tx packets file
268	ssize_t threads_nr = 1; // simulator's threads
269	bool debug_ok = false; // trace activated
270	size_t debug_period = 1; // trace period
271	size_t debug_memc_id = 0xFFFFFFFF; // idx of traced memc
272	size_t debug_proc_id = 0xFFFFFFFF; // idx of traced proc
273	bool debug_iob = false; // trace iobs when true
274	uint32_t debug_from = 0; // trace start cycle
275	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen procs
276	const size_t block_size = BDEV_SECTOR_SIZE; // disk block size
277	const size_t x_size = X_SIZE;
278	const size_t y_size = Y_SIZE;
279
280	assert((X_WIDTH == 4) and (Y_WIDTH == 4));
281
282	////////////// command line arguments //////////////////////
283	if (argc > 1) {
284	for (int n = 1; n < argc; n = n + 2) {
285	if ((strcmp(argv[n],"-NCYCLES") == 0) && ((n+1) < argc)) {
286	ncycles = strtoll(argv[n+1], NULL, 0);
287	continue;
288	}
289	if ((strcmp(argv[n],"-SOFT") == 0) && ((n+1) < argc) ) {
290	strcpy(soft_name, argv[n+1]);
291	continue;
292	}
293	if ((strcmp(argv[n],"-DISK") == 0) && ((n+1) < argc) ) {
294	strcpy(disk_name, argv[n+1]);
295	continue;
296	}
297	if ((strcmp(argv[n],"-DEBUG") == 0) && ((n+1) < argc) ) {
298	debug_ok = true;
299	debug_from = strtol(argv[n+1], NULL, 0);
300	continue;
301	}
302	if ((strcmp(argv[n],"-MEMCID") == 0) && ((n+1) < argc) ) {
303	debug_memc_id = strtol(argv[n+1], NULL, 0);
304	size_t x = debug_memc_id >> Y_WIDTH;
305	size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1);
306	assert((x < x_size) && (y < y_size));
307	continue;
308	}
309	if ((strcmp(argv[n],"-IOB") == 0) && ((n+1) < argc) ) {
310	debug_iob = (strtol(argv[n+1], NULL, 0) != 0) ? 1 : 0;
311	continue;
312	}
313	if ((strcmp(argv[n],"-PROCID") == 0) && ((n+1) < argc) ) {
314	debug_proc_id = strtol(argv[n+1], NULL, 0);
315	size_t cluster_xy = debug_proc_id / NB_PROCS ;
316	size_t x = cluster_xy >> Y_WIDTH;
317	size_t y = cluster_xy & ((1 << Y_WIDTH) - 1);
318	assert((x < x_size) && (y < y_size));
319	continue;
320	}
321	if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) {
322	threads_nr = strtol(argv[n+1], NULL, 0);
323	assert(threads_nr > 0);
324	continue;
325	}
326	if ((strcmp(argv[n], "-FROZEN") == 0) && ((n+1) < argc)) {
327	frozen_cycles = strtol(argv[n+1], NULL, 0);
328	assert(frozen_cycles > 0);
329	continue;
330	}
331	if ((strcmp(argv[n], "-PERIOD") == 0) && ((n+1) < argc)) {
332	debug_period = strtol(argv[n+1], NULL, 0);
333	assert(debug_period > 0);
334	continue;
335	}
336
337	std::cout << " Arguments are (key,value) couples.\n"
338	<< " The order is not important.\n"
339	<< " Accepted arguments are :\n\n"
340	<< " -NCYCLES number of simulated_cycles\n"
341	<< " -SOFT pathname for embedded soft\n"
342	<< " -DISK pathname for disk image\n"
343	<< " -DEBUG debug start cycle\n"
344	<< " -MEMCID index of memc to trace\n"
345	<< " -IOB debug IOBs if non_zero_value\n\n"
346	<< " -PROCID index of proc to trace\n"
347	<< " -THREADS simulator's threads number\n"
348	<< " -FROZEN max number of frozen cycles\n"
349	<< " -PERIOD number of cycles between trace\n\n";
350	exit(0);
351	}
352	}
353
354	assert( (NB_TTY_CHANNELS < 16) and
355	"The NB_TTY_CHANNELS parameter must be smaller than 16" );
356
357	assert( (NB_NIC_CHANNELS == 1) and
358	"The NB_NIC_CHANNELS parameter must be 1" );
359
360	std::cout << std::endl;
361	std::cout << " - X_SIZE = " << x_size << std::endl;
362	std::cout << " - Y_SIZE = " << y_size << std::endl;
363	std::cout << " - NB_PROCS = " << NB_PROCS << std::endl;
364	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
365	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
366	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
367	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
368	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
369	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
370	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
371
372	std::cout << std::endl;
373
374	#if USE_OPENMP
375	omp_set_dynamic(false);
376	omp_set_num_threads(threads_nr);
377	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
378	#endif
379
380	// Define VciParams objects
381	typedef soclib::caba::VciParams<vci_cell_width_int,
382	vci_plen_width,
383	vci_address_width,
384	vci_rerror_width,
385	vci_clen_width,
386	vci_rflag_width,
387	vci_srcid_width,
388	vci_pktid_width,
389	vci_trdid_width,
390	vci_wrplen_width> vci_param_int;
391
392	typedef soclib::caba::VciParams<vci_cell_width_ext,
393	vci_plen_width,
394	vci_address_width,
395	vci_rerror_width,
396	vci_clen_width,
397	vci_rflag_width,
398	vci_srcid_width,
399	vci_pktid_width,
400	vci_trdid_width,
401	vci_wrplen_width> vci_param_ext;
402
403	// Clusters
404	typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width,
405	dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width>
406	TsarIobClusterType;
407
408	// clusters containing IOB0 and IOB1
409	size_t cluster_iob0 = cluster(0, 0);
410	size_t cluster_iob1 = cluster(x_size - 1, y_size - 1);
411
412	/////////////////////////////////////////////////////////////////////
413	// INT network mapping table
414	// - two levels address decoding for commands
415	// - two levels srcid decoding for responses
416	// - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster
417	// - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster
418	/////////////////////////////////////////////////////////////////////
419	MappingTable maptab_int(
420	vci_address_width,
421	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
422	IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH),
423	0x00FF000000);
424
425	for (size_t x = 0; x < x_size; x++) {
426	for (size_t y = 0; y < y_size; y++) {
427	uint64_t offset = ((uint64_t)cluster(x,y))
428	<< (vci_address_width - X_WIDTH - Y_WIDTH);
429	const bool config = true;
430	const bool cacheable = true;
431
432	// the five following segments are defined in all clusters
433
434	std::ostringstream smemc_conf;
435	smemc_conf << "int_seg_memc_conf_" << x << "_" << y;
436	maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE,
437	IntTab(cluster(x,y),INT_MEMC_TGT_ID),
438	not cacheable, config ));
439
440	std::ostringstream smemc_xram;
441	smemc_xram << "int_seg_memc_xram_" << x << "_" << y;
442	maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE,
443	IntTab(cluster(x,y),INT_MEMC_TGT_ID),
444	cacheable));
445
446	std::ostringstream sxicu;
447	sxicu << "int_seg_xicu_" << x << "_" << y;
448	maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE,
449	IntTab(cluster(x,y),INT_XICU_TGT_ID),
450	not cacheable));
451
452	std::ostringstream sbrom;
453	sbrom << "int_seg_brom_" << x << "_" << y;
454	maptab_int.add(Segment(sbrom.str(), BROM_BASE+offset, BROM_SIZE,
455	IntTab(cluster(x,y),INT_BROM_TGT_ID),
456	cacheable));
457
458	std::ostringstream smtty;
459	smtty << "int_seg_mtty_" << x << "_" << y;
460	maptab_int.add(Segment(smtty.str(), MTTY_BASE+offset, MTTY_SIZE,
461	IntTab(cluster(x,y),INT_MTTY_TGT_ID),
462	not cacheable));
463
464	std::ostringstream smdma;
465	smdma << "int_seg_mdma_" << x << "_" << y;
466	maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE,
467	IntTab(cluster(x,y),INT_MDMA_TGT_ID),
468	not cacheable));
469
470	// the following segments are only defined in cluster_iob0 or in
471	// cluster_iob1
472	if ((cluster(x,y) == cluster_iob0) \|\|
473	(cluster(x,y) == cluster_iob1)) {
474	std::ostringstream siobx;
475	siobx << "int_seg_iobx_" << x << "_" << y;
476	maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE,
477	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
478	not cacheable, config ));
479
480	std::ostringstream stty;
481	stty << "int_seg_mtty_" << x << "_" << y;
482	maptab_int.add(Segment(stty.str(), XTTY_BASE+offset, XTTY_SIZE,
483	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
484	not cacheable));
485
486	std::ostringstream sfbf;
487	sfbf << "int_seg_fbuf_" << x << "_" << y;
488	maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE,
489	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
490	not cacheable));
491
492	std::ostringstream sbdv;
493	sbdv << "int_seg_bdev_" << x << "_" << y;
494	maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE,
495	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
496	not cacheable));
497
498	std::ostringstream snic;
499	snic << "int_seg_mnic_" << x << "_" << y;
500	maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE,
501	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
502	not cacheable));
503
504	std::ostringstream sdma;
505	sdma << "int_seg_cdma_" << x << "_" << y;
506	maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE,
507	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
508	not cacheable));
509	}
510
511	// This define the mapping between the SRCIDs
512	// and the port index on the local interconnect.
513
514	maptab_int.srcid_map(IntTab(cluster(x,y), MDMA_LOCAL_SRCID),
515	IntTab(cluster(x,y), INT_MDMA_INI_ID));
516	maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID),
517	IntTab(cluster(x,y), INT_IOBX_INI_ID));
518
519	for ( size_t p = 0 ; p < NB_PROCS ; p++ ) {
520	maptab_int.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p),
521	IntTab(cluster(x,y), INT_PROC_INI_ID + p));
522	}
523	}
524	}
525	std::cout << "INT network " << maptab_int << std::endl;
526
527	/////////////////////////////////////////////////////////////////////////
528	// RAM network mapping table
529	// - two levels address decoding for commands
530	// - two levels srcid decoding for responses
531	// - 2 local initiators (MEMC, IOBX) per cluster
532	// (IOBX component only in cluster_iob0 and cluster_iob1)
533	// - 1 local target (XRAM) per cluster
534	////////////////////////////////////////////////////////////////////////
535	MappingTable maptab_ram(
536	vci_address_width,
537	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
538	IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH),
539	0x00FF000000);
540
541	for (size_t x = 0; x < x_size; x++) {
542	for (size_t y = 0; y < y_size ; y++) {
543	uint64_t offset = ((uint64_t)cluster(x,y))
544	<< (vci_address_width - X_WIDTH - Y_WIDTH);
545
546	std::ostringstream sxram;
547	sxram << "ext_seg_xram_" << x << "_" << y;
548	maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, XRAM_SIZE,
549	IntTab(cluster(x,y), 0), false));
550	}
551	}
552
553	// This define the mapping between the initiators SRCID
554	// and the port index on the RAM local interconnect.
555	// External initiator have two alias SRCID (iob0 / iob1)
556
557	maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
558	IntTab(cluster_iob0, RAM_IOBX_INI_ID));
559	maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
560	IntTab(cluster_iob1, RAM_IOBX_INI_ID));
561	maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
562	IntTab(cluster_iob0, RAM_IOBX_INI_ID));
563	maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
564	IntTab(cluster_iob1, RAM_IOBX_INI_ID));
565	maptab_ram.srcid_map(IntTab(cluster_iob1, MEMC_LOCAL_SRCID),
566	IntTab(cluster_iob1, RAM_MEMC_INI_ID));
567
568	std::cout << "RAM network " << maptab_ram << std::endl;
569
570	///////////////////////////////////////////////////////////////////////
571	// IOX network mapping table
572	// - two levels address decoding for commands
573	// - two levels srcid decoding for responses
574	// - 4 initiators (IOB0, IOB1, BDEV, CDMA)
575	// - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC)
576	///////////////////////////////////////////////////////////////////////
577	MappingTable maptab_iox(
578	vci_address_width,
579	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
580	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
581	0x00FF000000);
582
583	// compute base addresses for cluster_iob0 and cluster_iob1
584	uint64_t iob0_base = ((uint64_t)cluster_iob0)
585	<< (vci_address_width - X_WIDTH - Y_WIDTH);
586	uint64_t iob1_base = ((uint64_t)cluster_iob1)
587	<< (vci_address_width - X_WIDTH - Y_WIDTH);
588
589	// Each peripheral can be accessed through two segments,
590	// depending on the used IOB (IOB0 or IOB1).
591	maptab_iox.add(Segment("iox_seg_mtty_0", XTTY_BASE + iob0_base, XTTY_SIZE,
592	IntTab(cluster_iob0, IOX_MTTY_TGT_ID), false));
593	maptab_iox.add(Segment("iox_seg_mtty_1", XTTY_BASE + iob1_base, XTTY_SIZE,
594	IntTab(cluster_iob1, IOX_MTTY_TGT_ID), false));
595	maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE,
596	IntTab(cluster_iob0, IOX_FBUF_TGT_ID), false));
597	maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE,
598	IntTab(cluster_iob1, IOX_FBUF_TGT_ID), false));
599	maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE,
600	IntTab(cluster_iob0, IOX_BDEV_TGT_ID), false));
601	maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE,
602	IntTab(cluster_iob1, IOX_BDEV_TGT_ID), false));
603	maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE,
604	IntTab(cluster_iob0, IOX_MNIC_TGT_ID), false));
605	maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE,
606	IntTab(cluster_iob1, IOX_MNIC_TGT_ID), false));
607	maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE,
608	IntTab(cluster_iob0, IOX_CDMA_TGT_ID), false));
609	maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE,
610	IntTab(cluster_iob1, IOX_CDMA_TGT_ID), false));
611
612	// Each physical RAM can be accessed through IOB0, or through IOB1.
613	// if IOMMU is not activated, addresses are 40 bits (physical addresses),
614	// and the choice depends on on address bit A[39].
615	// if IOMMU is activated the addresses use only 32 bits (virtual
616	// addresses), and the choice depends on address bit A[31].
617	for (size_t x = 0; x < x_size; x++) {
618	for (size_t y = 0; y < y_size ; y++) {
619	uint64_t offset = static_cast<uint64_t>(cluster(x,y))
620	<< (vci_address_width - X_WIDTH - Y_WIDTH);
621
622	// send command to XRAM through IOB0
623	if ( x < (x_size/2) ) {
624	std::ostringstream siob0;
625	siob0 << "iox_seg_xram_" << x << "_" << y;
626	maptab_iox.add(Segment(siob0.str(),
627	XRAM_BASE + offset, XRAM_SIZE,
628	IntTab(cluster_iob0,IOX_IOB0_TGT_ID),
629	false));
630	}
631	// send command to XRAM through IOB1
632	else {
633	std::ostringstream siob1;
634	siob1 << "iox_seg_xram_" << x << "_" << y;
635	maptab_iox.add(Segment(siob1.str(),
636	XRAM_BASE + offset, XRAM_SIZE,
637	IntTab(cluster_iob1,IOX_IOB1_TGT_ID),
638	false));
639	}
640	}
641	}
642	// useful when IOMMU activated
643	//maptab_iox.add(Segment("iox_seg_xram", 0xc0000000, 0x40000000,
644	// IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false));
645
646	// This define the mapping between the initiators (identified by the SRCID)
647	// and the port index on the IOX local interconnect.
648	// External initiator have two alias SRCID (iob0 / iob1 access)
649
650	maptab_iox.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
651	IntTab(cluster_iob0, IOX_CDMA_INI_ID));
652	maptab_iox.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
653	IntTab(cluster_iob1, IOX_CDMA_INI_ID));
654	maptab_iox.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
655	IntTab(cluster_iob0, IOX_BDEV_INI_ID));
656	maptab_iox.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
657	IntTab(cluster_iob0, IOX_BDEV_INI_ID));
658
659	for (size_t x = 0; x < x_size; x++) {
660	for (size_t y = 0; y < y_size ; y++) {
661	size_t iob = (x < (x_size / 2)) ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID;
662
663	for (size_t p = 0 ; p < NB_PROCS ; p++) {
664	maptab_iox.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p),
665	IntTab(cluster(x,y), iob));
666	}
667	maptab_iox.srcid_map(IntTab( cluster(x,y), MDMA_LOCAL_SRCID),
668	IntTab( cluster(x,y), IOX_IOB0_INI_ID));
669	}
670	}
671
672	std::cout << "IOX network " << maptab_iox << std::endl;
673
674	////////////////////
675	// Signals
676	////////////////////
677
678	sc_clock signal_clk("clk");
679	sc_signal<bool> signal_resetn("resetn");
680
681	sc_signal<bool> signal_irq_false;
682	sc_signal<bool> signal_irq_bdev;
683	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
684	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
685	sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS];
686	sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2];
687
688	// DSPIN signals for loopback in cluster_iob0 & cluster_iob1
689	DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback;
690	DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback;
691	DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback;
692	DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback;
693
694	// VCI signals for IOX network
695	VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0");
696	VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1");
697	VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev");
698	VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma");
699
700	VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0");
701	VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1");
702	VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
703	VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
704	VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
705	VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
706	VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
707
708	// Horizontal inter-clusters INT network DSPIN
709	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc =
710	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
711	"signal_dspin_int_cmd_h_inc", x_size-1, y_size, 3);
712	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec =
713	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
714	"signal_dspin_int_cmd_h_dec", x_size-1, y_size, 3);
715	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc =
716	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
717	"signal_dspin_int_rsp_h_inc", x_size-1, y_size, 2);
718	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec =
719	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
720	"signal_dspin_int_rsp_h_dec", x_size-1, y_size, 2);
721
722	// Vertical inter-clusters INT network DSPIN
723	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc =
724	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
725	"signal_dspin_int_cmd_v_inc", x_size, y_size-1, 3);
726	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec =
727	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
728	"signal_dspin_int_cmd_v_dec", x_size, y_size-1, 3);
729	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc =
730	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
731	"signal_dspin_int_rsp_v_inc", x_size, y_size-1, 2);
732	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec =
733	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
734	"signal_dspin_int_rsp_v_dec", x_size, y_size-1, 2);
735
736	// Mesh boundaries INT network DSPIN
737	DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in =
738	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
739	"signal_dspin_false_int_cmd_in", x_size, y_size, 4, 3);
740	DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out =
741	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
742	"signal_dspin_false_int_cmd_out", x_size, y_size, 4, 3);
743	DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in =
744	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
745	"signal_dspin_false_int_rsp_in", x_size, y_size, 4, 2);
746	DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out =
747	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
748	"signal_dspin_false_int_rsp_out", x_size, y_size, 4, 2);
749
750
751	// Horizontal inter-clusters RAM network DSPIN
752	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc =
753	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
754	"signal_dspin_ram_cmd_h_inc", x_size-1, y_size);
755	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec =
756	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
757	"signal_dspin_ram_cmd_h_dec", x_size-1, y_size);
758	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc =
759	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
760	"signal_dspin_ram_rsp_h_inc", x_size-1, y_size);
761	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec =
762	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
763	"signal_dspin_ram_rsp_h_dec", x_size-1, y_size);
764
765	// Vertical inter-clusters RAM network DSPIN
766	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc =
767	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
768	"signal_dspin_ram_cmd_v_inc", x_size, y_size-1);
769	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec =
770	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
771	"signal_dspin_ram_cmd_v_dec", x_size, y_size-1);
772	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc =
773	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
774	"signal_dspin_ram_rsp_v_inc", x_size, y_size-1);
775	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec =
776	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
777	"signal_dspin_ram_rsp_v_dec", x_size, y_size-1);
778
779	// Mesh boundaries RAM network DSPIN
780	DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in =
781	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
782	"signal_dspin_false_ram_cmd_in", x_size, y_size, 4);
783	DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out =
784	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
785	"signal_dspin_false_ram_cmd_out", x_size, y_size, 4);
786	DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in =
787	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
788	"signal_dspin_false_ram_rsp_in", x_size, y_size, 4);
789	DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out =
790	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
791	"signal_dspin_false_ram_rsp_out", x_size, y_size, 4);
792
793	////////////////////////////
794	// Loader
795	////////////////////////////
796
797	soclib::common::Loader loader(soft_name);
798
799	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
800	proc_iss::set_loader(loader);
801
802	////////////////////////////////////////
803	// Instanciated Hardware Components
804	////////////////////////////////////////
805
806	std::cout << std::endl << "External Bus and Peripherals" << std::endl
807	<< std::endl;
808
809	// IOX network
810	VciIoxNetwork<vci_param_ext>* iox_network;
811	iox_network = new VciIoxNetwork<vci_param_ext>("iox_network",
812	maptab_iox,
813	7, // number of targets
814	4 ); // number of initiators
815
816	// Network Controller
817	VciMultiNic<vci_param_ext>* mnic;
818	mnic = new VciMultiNic<vci_param_ext>("mnic",
819	IntTab(0, IOX_MNIC_TGT_ID),
820	maptab_iox,
821	NB_NIC_CHANNELS,
822	0, // mac_4 address
823	0, // mac_2 address
824	nic_rx_name,
825	nic_tx_name);
826
827	// Frame Buffer
828	VciFrameBuffer<vci_param_ext>* fbuf;
829	fbuf = new VciFrameBuffer<vci_param_ext>("fbuf",
830	IntTab(0, IOX_FBUF_TGT_ID),
831	maptab_iox,
832	FBUF_X_SIZE, FBUF_Y_SIZE );
833
834	// Block Device
835	// for AHCI
836	// std::vector<std::string> filenames;
837	// filenames.push_back(disk_name); // one single disk
838	VciBlockDeviceTsar<vci_param_ext>* bdev;
839	bdev = new VciBlockDeviceTsar<vci_param_ext>("bdev",
840	maptab_iox,
841	IntTab(0, BDEV_LOCAL_SRCID),
842	IntTab(0, IOX_BDEV_TGT_ID),
843	disk_name,
844	block_size,
845	64, // burst size (bytes)
846	0 ); // disk latency
847
848	// Chained Buffer DMA controller
849	VciChbufDma<vci_param_ext>* cdma;
850	cdma = new VciChbufDma<vci_param_ext>("cdma",
851	maptab_iox,
852	IntTab(0, CDMA_LOCAL_SRCID),
853	IntTab(0, IOX_CDMA_TGT_ID),
854	64, // burst size (bytes)
855	2 * NB_NIC_CHANNELS);
856	// Multi-TTY controller
857	std::vector<std::string> vect_names;
858	for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ )
859	{
860	std::ostringstream term_name;
861	term_name << "mtty_iox_" << tid;
862	vect_names.push_back(term_name.str().c_str());
863	}
864	VciMultiTty<vci_param_ext>* mtty;
865	mtty = new VciMultiTty<vci_param_ext>("mtty_iox",
866	IntTab(0, IOX_MTTY_TGT_ID),
867	maptab_iox,
868	vect_names);
869
870	TsarIobClusterType* clusters[x_size][y_size];
871
872	#if USE_OPENMP
873	#pragma omp parallel
874	{
875	#pragma omp for
876	#endif
877
878	for(size_t i = 0; i < (x_size * y_size); i++) {
879	size_t x = i / y_size;
880	size_t y = i % y_size;
881
882	#if USE_OPENMP
883	#pragma omp critical
884	{
885	#endif
886	std::cout << std::endl;
887	std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl;
888	std::cout << std::endl;
889
890	std::ostringstream sc;
891	sc << "cluster_" << x << "_" << y;
892
893	bool memc_debug =
894	debug_ok && (cluster(x,y) == debug_memc_id);
895	bool proc_debug =
896	debug_ok && (cluster(x,y) == (debug_proc_id / NB_PROCS));
897
898	TsarIobClusterType::ClusterParams params = {
899	.insname = sc.str().c_str(),
900
901	.x_id = x,
902	.y_id = y,
903
904	.mt_int = maptab_int,
905	.mt_ext = maptab_ram,
906	.mt_iox = maptab_iox,
907
908	.memc_ways = MEMC_WAYS,
909	.memc_sets = MEMC_SETS,
910	.l1_i_ways = L1_IWAYS,
911	.l1_i_sets = L1_ISETS,
912	.l1_d_ways = L1_DWAYS,
913	.l1_d_sets = L1_DSETS,
914	.xram_latency = XRAM_LATENCY,
915
916	.loader = loader,
917
918	.frozen_cycles = frozen_cycles,
919	.debug_start_cycle = debug_from,
920	.memc_debug_ok = memc_debug,
921	.proc_debug_ok = proc_debug,
922	.iob_debug_ok = debug_ok and debug_iob
923	};
924
925	clusters[x][y] = new TsarIobClusterType(params);
926
927	#if USE_OPENMP
928	} // end critical
929	#endif
930	} // end for
931	#if USE_OPENMP
932	}
933	#endif
934
935	std::cout << std::endl;
936
937	///////////////////////////////////////////////////////////////////////////
938	// Net-list
939	///////////////////////////////////////////////////////////////////////////
940
941	// IOX network connexion
942	iox_network->p_clk (signal_clk);
943	iox_network->p_resetn (signal_resetn);
944	iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0);
945	iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1);
946	iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev);
947	iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma);
948	iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0);
949	iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1);
950	iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty);
951	iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf);
952	iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic);
953	iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev);
954	iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma);
955
956	// BDEV connexion
957	bdev->p_clk (signal_clk);
958	bdev->p_resetn (signal_resetn);
959	bdev->p_irq (signal_irq_bdev);
960
961	// For AHCI
962	// bdev->p_channel_irq[0] (signal_irq_bdev);
963
964	bdev->p_vci_target (signal_vci_tgt_bdev);
965	bdev->p_vci_initiator (signal_vci_ini_bdev);
966
967	std::cout << " - BDEV connected" << std::endl;
968
969	// FBUF connexion
970	fbuf->p_clk (signal_clk);
971	fbuf->p_resetn (signal_resetn);
972	fbuf->p_vci (signal_vci_tgt_fbuf);
973
974	std::cout << " - FBUF connected" << std::endl;
975
976	// MNIC connexion
977	mnic->p_clk (signal_clk);
978	mnic->p_resetn (signal_resetn);
979	mnic->p_vci (signal_vci_tgt_mnic);
980	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
981	{
982	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
983	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
984	}
985
986	std::cout << " - MNIC connected" << std::endl;
987
988	// MTTY connexion
989	mtty->p_clk (signal_clk);
990	mtty->p_resetn (signal_resetn);
991	mtty->p_vci (signal_vci_tgt_mtty);
992	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) {
993	mtty->p_irq[i] (signal_irq_mtty[i]);
994	}
995
996	std::cout << " - MTTY connected" << std::endl;
997
998	// CDMA connexion
999	cdma->p_clk (signal_clk);
1000	cdma->p_resetn (signal_resetn);
1001	cdma->p_vci_target (signal_vci_tgt_cdma);
1002	cdma->p_vci_initiator (signal_vci_ini_cdma);
1003	for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) {
1004	cdma->p_irq[i] (signal_irq_cdma[i]);
1005	}
1006
1007	std::cout << " - CDMA connected" << std::endl;
1008
1009	// IRQ connexions from external peripherals (cluster_iob0 only)
1010	// IRQ_MNIC_RX -> IRQ[08] to IRQ[09]
1011	// IRQ_MNIC_TX -> IRQ[10] to IRQ[11]
1012	// IRQ_CDMA -> IRQ[12] to IRQ[15]
1013	// IRQ_MTTY -> IRQ[16] to IRQ[30]
1014	// IRQ_BDEV -> IRQ[31]
1015
1016	size_t mx = 16 + NB_TTY_CHANNELS;
1017	for ( size_t n=0 ; n<32 ; n++ ) {
1018	if ( n < 8 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
1019	else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
1020	else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
1021	else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
1022	else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]);
1023	else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
1024	else (*clusters[0][0]->p_irq[n]) (signal_irq_bdev);
1025	}
1026
1027	// IOB0 cluster connexion to IOX network
1028	(*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0);
1029	(*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0);
1030
1031	// IOB1 cluster connexion to IOX network
1032	(*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1);
1033	(*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1);
1034
1035	// All clusters Clock & RESET connexions
1036	for ( size_t x = 0; x < (x_size); x++ ) {
1037	for (size_t y = 0; y < y_size; y++) {
1038	clusters[x][y]->p_clk (signal_clk);
1039	clusters[x][y]->p_resetn (signal_resetn);
1040	}
1041	}
1042
1043	const int& NORTH = VirtualDspinRouter<dspin_int_cmd_width>::NORTH;
1044	const int& SOUTH = VirtualDspinRouter<dspin_int_cmd_width>::SOUTH;
1045	const int& EAST = VirtualDspinRouter<dspin_int_cmd_width>::EAST;
1046	const int& WEST = VirtualDspinRouter<dspin_int_cmd_width>::WEST;
1047
1048	// Inter Clusters horizontal connections
1049	if (x_size > 1) {
1050	for (size_t x = 0; x < (x_size-1); x++) {
1051	for (size_t y = 0; y < y_size; y++) {
1052	for (size_t k = 0; k < 3; k++) {
1053	clusters[x][y]->p_dspin_int_cmd_out[EAST][k](
1054	signal_dspin_int_cmd_h_inc[x][y][k]);
1055	clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k](
1056	signal_dspin_int_cmd_h_inc[x][y][k]);
1057	clusters[x][y]->p_dspin_int_cmd_in[EAST][k](
1058	signal_dspin_int_cmd_h_dec[x][y][k]);
1059	clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k](
1060	signal_dspin_int_cmd_h_dec[x][y][k]);
1061	}
1062
1063	for (size_t k = 0; k < 2; k++) {
1064	clusters[x][y]->p_dspin_int_rsp_out[EAST][k](
1065	signal_dspin_int_rsp_h_inc[x][y][k]);
1066	clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k](
1067	signal_dspin_int_rsp_h_inc[x][y][k]);
1068	clusters[x][y]->p_dspin_int_rsp_in[EAST][k](
1069	signal_dspin_int_rsp_h_dec[x][y][k]);
1070	clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k](
1071	signal_dspin_int_rsp_h_dec[x][y][k]);
1072	}
1073
1074	clusters[x][y]->p_dspin_ram_cmd_out[EAST](
1075	signal_dspin_ram_cmd_h_inc[x][y]);
1076	clusters[x+1][y]->p_dspin_ram_cmd_in[WEST](
1077	signal_dspin_ram_cmd_h_inc[x][y]);
1078	clusters[x][y]->p_dspin_ram_cmd_in[EAST](
1079	signal_dspin_ram_cmd_h_dec[x][y]);
1080	clusters[x+1][y]->p_dspin_ram_cmd_out[WEST](
1081	signal_dspin_ram_cmd_h_dec[x][y]);
1082	clusters[x][y]->p_dspin_ram_rsp_out[EAST](
1083	signal_dspin_ram_rsp_h_inc[x][y]);
1084	clusters[x+1][y]->p_dspin_ram_rsp_in[WEST](
1085	signal_dspin_ram_rsp_h_inc[x][y]);
1086	clusters[x][y]->p_dspin_ram_rsp_in[EAST](
1087	signal_dspin_ram_rsp_h_dec[x][y]);
1088	clusters[x+1][y]->p_dspin_ram_rsp_out[WEST](
1089	signal_dspin_ram_rsp_h_dec[x][y]);
1090	}
1091	}
1092	}
1093
1094	std::cout << std::endl << "Horizontal connections established"
1095	<< std::endl;
1096
1097	// Inter Clusters vertical connections
1098	if (y_size > 1) {
1099	for (size_t y = 0; y < (y_size-1); y++) {
1100	for (size_t x = 0; x < x_size; x++) {
1101	for (size_t k = 0; k < 3; k++) {
1102	clusters[x][y]->p_dspin_int_cmd_out[NORTH][k](
1103	signal_dspin_int_cmd_v_inc[x][y][k]);
1104	clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k](
1105	signal_dspin_int_cmd_v_inc[x][y][k]);
1106	clusters[x][y]->p_dspin_int_cmd_in[NORTH][k](
1107	signal_dspin_int_cmd_v_dec[x][y][k]);
1108	clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k](
1109	signal_dspin_int_cmd_v_dec[x][y][k]);
1110	}
1111
1112	for (size_t k = 0; k < 2; k++) {
1113	clusters[x][y]->p_dspin_int_rsp_out[NORTH][k](
1114	signal_dspin_int_rsp_v_inc[x][y][k]);
1115	clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k](
1116	signal_dspin_int_rsp_v_inc[x][y][k]);
1117	clusters[x][y]->p_dspin_int_rsp_in[NORTH][k](
1118	signal_dspin_int_rsp_v_dec[x][y][k]);
1119	clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k](
1120	signal_dspin_int_rsp_v_dec[x][y][k]);
1121	}
1122
1123	clusters[x][y]->p_dspin_ram_cmd_out[NORTH](
1124	signal_dspin_ram_cmd_v_inc[x][y]);
1125	clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH](
1126	signal_dspin_ram_cmd_v_inc[x][y]);
1127	clusters[x][y]->p_dspin_ram_cmd_in[NORTH](
1128	signal_dspin_ram_cmd_v_dec[x][y]);
1129	clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH](
1130	signal_dspin_ram_cmd_v_dec[x][y]);
1131	clusters[x][y]->p_dspin_ram_rsp_out[NORTH](
1132	signal_dspin_ram_rsp_v_inc[x][y]);
1133	clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH](
1134	signal_dspin_ram_rsp_v_inc[x][y]);
1135	clusters[x][y]->p_dspin_ram_rsp_in[NORTH](
1136	signal_dspin_ram_rsp_v_dec[x][y]);
1137	clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH](
1138	signal_dspin_ram_rsp_v_dec[x][y]);
1139	}
1140	}
1141	}
1142
1143	std::cout << "Vertical connections established" << std::endl;
1144
1145	// East & West boundary cluster connections
1146	for (size_t y = 0; y < y_size; y++) {
1147	for (size_t k = 0; k < 3; k++) {
1148	clusters[0][y]->p_dspin_int_cmd_in[WEST][k](
1149	signal_dspin_false_int_cmd_in[0][y][WEST][k]);
1150	clusters[0][y]->p_dspin_int_cmd_out[WEST][k](
1151	signal_dspin_false_int_cmd_out[0][y][WEST][k]);
1152	clusters[x_size-1][y]->p_dspin_int_cmd_in[EAST][k](
1153	signal_dspin_false_int_cmd_in[x_size-1][y][EAST][k]);
1154	clusters[x_size-1][y]->p_dspin_int_cmd_out[EAST][k](
1155	signal_dspin_false_int_cmd_out[x_size-1][y][EAST][k]);
1156	}
1157
1158	for (size_t k = 0; k < 2; k++) {
1159	clusters[0][y]->p_dspin_int_rsp_in[WEST][k](
1160	signal_dspin_false_int_rsp_in[0][y][WEST][k]);
1161	clusters[0][y]->p_dspin_int_rsp_out[WEST][k](
1162	signal_dspin_false_int_rsp_out[0][y][WEST][k]);
1163	clusters[x_size-1][y]->p_dspin_int_rsp_in[EAST][k](
1164	signal_dspin_false_int_rsp_in[x_size-1][y][EAST][k]);
1165	clusters[x_size-1][y]->p_dspin_int_rsp_out[EAST][k](
1166	signal_dspin_false_int_rsp_out[x_size-1][y][EAST][k]);
1167	}
1168
1169	// handling IOB to RAM network connection in cluster_iob0
1170	if( y == 0 ) {
1171	(*clusters[0][0]->p_dspin_iob_cmd_out)(
1172	signal_dspin_cmd_iob0_loopback);
1173	clusters[0][0]->p_dspin_ram_cmd_in[WEST](
1174	signal_dspin_cmd_iob0_loopback);
1175	clusters[0][0]->p_dspin_ram_cmd_out[WEST](
1176	signal_dspin_false_ram_cmd_out[0][0][WEST]);
1177	clusters[0][0]->p_dspin_ram_rsp_in[WEST](
1178	signal_dspin_false_ram_rsp_in[0][0][WEST]);
1179	clusters[0][0]->p_dspin_ram_rsp_out[WEST](
1180	signal_dspin_rsp_iob0_loopback);
1181	(*clusters[0][0]->p_dspin_iob_rsp_in)(
1182	signal_dspin_rsp_iob0_loopback);
1183	}
1184	else {
1185	clusters[0][y]->p_dspin_ram_cmd_in[WEST](
1186	signal_dspin_false_ram_cmd_in[0][y][WEST]);
1187	clusters[0][y]->p_dspin_ram_cmd_out[WEST](
1188	signal_dspin_false_ram_cmd_out[0][y][WEST]);
1189	clusters[0][y]->p_dspin_ram_rsp_in[WEST](
1190	signal_dspin_false_ram_rsp_in[0][y][WEST]);
1191	clusters[0][y]->p_dspin_ram_rsp_out[WEST](
1192	signal_dspin_false_ram_rsp_out[0][y][WEST]);
1193	}
1194
1195	// handling IOB to RAM network connection in cluster_iob1
1196	if( y == y_size-1 ) {
1197	(*clusters[x_size-1][y_size-1]->p_dspin_iob_cmd_out)(
1198	signal_dspin_cmd_iob1_loopback);
1199	clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_in[EAST](
1200	signal_dspin_cmd_iob1_loopback);
1201
1202	clusters[x_size-1][y_size-1]->p_dspin_ram_cmd_out[EAST](
1203	signal_dspin_false_ram_cmd_out[x_size-1][y_size-1][EAST]);
1204	clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_in[EAST](
1205	signal_dspin_false_ram_rsp_in[x_size-1][y_size-1][EAST]);
1206
1207	clusters[x_size-1][y_size-1]->p_dspin_ram_rsp_out[EAST](
1208	signal_dspin_rsp_iob1_loopback);
1209	(*clusters[x_size-1][y_size-1]->p_dspin_iob_rsp_in)(
1210	signal_dspin_rsp_iob1_loopback);
1211	}
1212	else {
1213	clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST](
1214	signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]);
1215	clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST](
1216	signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]);
1217	clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST](
1218	signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]);
1219	clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST](
1220	signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]);
1221	}
1222	}
1223
1224	std::cout << "East & West boundaries established" << std::endl;
1225
1226	// North & South boundary clusters connections
1227	for (size_t x = 0; x < x_size; x++) {
1228	for (size_t k = 0; k < 3; k++) {
1229	clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k](
1230	signal_dspin_false_int_cmd_in[x][0][SOUTH][k]);
1231	clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k](
1232	signal_dspin_false_int_cmd_out[x][0][SOUTH][k]);
1233	clusters[x][y_size-1]->p_dspin_int_cmd_in[NORTH][k](
1234	signal_dspin_false_int_cmd_in[x][y_size-1][NORTH][k]);
1235	clusters[x][y_size-1]->p_dspin_int_cmd_out[NORTH][k](
1236	signal_dspin_false_int_cmd_out[x][y_size-1][NORTH][k]);
1237	}
1238
1239	for (size_t k = 0; k < 2; k++) {
1240	clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k](
1241	signal_dspin_false_int_rsp_in[x][0][SOUTH][k]);
1242	clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k](
1243	signal_dspin_false_int_rsp_out[x][0][SOUTH][k]);
1244	clusters[x][y_size-1]->p_dspin_int_rsp_in[NORTH][k](
1245	signal_dspin_false_int_rsp_in[x][y_size-1][NORTH][k]);
1246	clusters[x][y_size-1]->p_dspin_int_rsp_out[NORTH][k](
1247	signal_dspin_false_int_rsp_out[x][y_size-1][NORTH][k]);
1248	}
1249
1250	clusters[x][0]->p_dspin_ram_cmd_in[SOUTH](
1251	signal_dspin_false_ram_cmd_in[x][0][SOUTH]);
1252	clusters[x][0]->p_dspin_ram_cmd_out[SOUTH](
1253	signal_dspin_false_ram_cmd_out[x][0][SOUTH]);
1254	clusters[x][0]->p_dspin_ram_rsp_in[SOUTH](
1255	signal_dspin_false_ram_rsp_in[x][0][SOUTH]);
1256	clusters[x][0]->p_dspin_ram_rsp_out[SOUTH](
1257	signal_dspin_false_ram_rsp_out[x][0][SOUTH]);
1258
1259	clusters[x][y_size-1]->p_dspin_ram_cmd_in[NORTH](
1260	signal_dspin_false_ram_cmd_in[x][y_size-1][NORTH]);
1261	clusters[x][y_size-1]->p_dspin_ram_cmd_out[NORTH](
1262	signal_dspin_false_ram_cmd_out[x][y_size-1][NORTH]);
1263	clusters[x][y_size-1]->p_dspin_ram_rsp_in[NORTH](
1264	signal_dspin_false_ram_rsp_in[x][y_size-1][NORTH]);
1265	clusters[x][y_size-1]->p_dspin_ram_rsp_out[NORTH](
1266	signal_dspin_false_ram_rsp_out[x][y_size-1][NORTH]);
1267	}
1268
1269	std::cout << "North & South boundaries established" << std::endl
1270	<< std::endl;
1271
1272	////////////////////////////////////////////////////////
1273	// Simulation
1274	///////////////////////////////////////////////////////
1275
1276	sc_start(sc_core::sc_time(0, SC_NS));
1277
1278	signal_resetn = false;
1279
1280	signal_irq_false = false;
1281
1282	// network boundaries signals
1283	for (size_t x = 0; x < x_size ; x++) {
1284	for (size_t y = 0; y < y_size ; y++) {
1285	for (size_t a = 0; a < 4; a++) {
1286	for (size_t k = 0; k < 3; k++) {
1287	signal_dspin_false_int_cmd_in[x][y][a][k].write = false;
1288	signal_dspin_false_int_cmd_in[x][y][a][k].read = true;
1289	signal_dspin_false_int_cmd_out[x][y][a][k].write = false;
1290	signal_dspin_false_int_cmd_out[x][y][a][k].read = true;
1291	}
1292
1293	for (size_t k = 0; k < 2; k++) {
1294	signal_dspin_false_int_rsp_in[x][y][a][k].write = false;
1295	signal_dspin_false_int_rsp_in[x][y][a][k].read = true;
1296	signal_dspin_false_int_rsp_out[x][y][a][k].write = false;
1297	signal_dspin_false_int_rsp_out[x][y][a][k].read = true;
1298	}
1299
1300	signal_dspin_false_ram_cmd_in[x][y][a].write = false;
1301	signal_dspin_false_ram_cmd_in[x][y][a].read = true;
1302	signal_dspin_false_ram_cmd_out[x][y][a].write = false;
1303	signal_dspin_false_ram_cmd_out[x][y][a].read = true;
1304
1305	signal_dspin_false_ram_rsp_in[x][y][a].write = false;
1306	signal_dspin_false_ram_rsp_in[x][y][a].read = true;
1307	signal_dspin_false_ram_rsp_out[x][y][a].write = false;
1308	signal_dspin_false_ram_rsp_out[x][y][a].read = true;
1309	}
1310	}
1311	}
1312
1313	sc_start(sc_core::sc_time(1, SC_NS));
1314	signal_resetn = true;
1315
1316	struct timeval t1, t2;
1317	const uint64_t stats_period = 100000;
1318	gettimeofday(&t1, NULL);
1319	for (uint64_t n = 1; n < ncycles; n++) {
1320	// stats display
1321	if((n % stats_period) == 0) {
1322	gettimeofday(&t2, NULL);
1323
1324	uint64_t ms1 = (uint64_t) t1.tv_sec * 1000 +
1325	(uint64_t) t1.tv_usec / 1000;
1326	uint64_t ms2 = (uint64_t) t2.tv_sec * 1000 +
1327	(uint64_t) t2.tv_usec / 1000;
1328	double freq = (double) stats_period / (ms2 - ms1);
1329
1330	std::cerr << "Platform Clock Frequency: " << freq << " Khz"
1331	<< std::endl;
1332
1333	gettimeofday(&t1, NULL);
1334	}
1335
1336	if (debug_ok and (n > debug_from) and ((n % debug_period) == 0)) {
1337	std::cout << " ***********************"
1338	<< " cycle " << std::dec << n
1339	<< " ***********************"
1340	<< std::endl;
1341
1342	// trace proc[debug_proc_id]
1343	if ( debug_proc_id != 0xFFFFFFFF ) {
1344	size_t l = debug_proc_id % NB_PROCS ;
1345	size_t cluster_xy = debug_proc_id / NB_PROCS ;
1346	size_t x = cluster_xy >> Y_WIDTH;
1347	size_t y = cluster_xy & ((1 << Y_WIDTH) - 1);
1348
1349	clusters[x][y]->proc[l]->print_trace(1);
1350
1351	std::ostringstream proc_signame;
1352	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
1353	clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(
1354	proc_signame.str());
1355
1356	clusters[x][y]->xicu->print_trace(l);
1357
1358	std::ostringstream xicu_signame;
1359	xicu_signame << "[SIG]XICU_" << x << "_" << y;
1360	clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(
1361	xicu_signame.str());
1362
1363	if( clusters[x][y]->signal_proc_it[l].read() ) {
1364	std::cout << "### IRQ_PROC_" << std::dec
1365	<< x << "_" << y << "_" << l
1366	<< " ACTIVE" << std::endl;
1367	}
1368	}
1369
1370	// trace INT network
1371	// clusters[0][0]->int_xbar_d->print_trace();
1372
1373	// clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace(
1374	// "[SIG] INT_CMD_L2G_D_0_0");
1375	// clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace(
1376	// "[SIG] INT_RSP_G2L_D_0_0");
1377
1378	// clusters[0][0]->int_router_cmd->print_trace(0);
1379	// clusters[0][0]->int_router_rsp->print_trace(0);
1380
1381	// trace INT_CMD_D xbar and router in cluster 0_1
1382	// clusters[0][1]->int_router_cmd->print_trace(0);
1383	// clusters[0][1]->int_router_rsp->print_trace(0);
1384
1385	// clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace(
1386	// "[SIG] INT_CMD_G2L_D_0_0");
1387	// clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace(
1388	// "[SIG] INT_RSP_L2G_D_0_0");
1389
1390	// clusters[0][1]->int_xbar_cmd_d->print_trace();
1391
1392	// trace memc[debug_memc_id]
1393	if ( debug_memc_id != 0xFFFFFFFF ) {
1394	size_t x = debug_memc_id >> Y_WIDTH;
1395	size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1);
1396
1397	clusters[x][y]->memc->print_trace(0);
1398	std::ostringstream smemc_tgt;
1399	smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y;
1400	clusters[x][y]->signal_int_vci_tgt_memc.print_trace(
1401	smemc_tgt.str());
1402	std::ostringstream smemc_ini;
1403	smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y;
1404	clusters[x][y]->signal_ram_vci_ini_memc.print_trace(
1405	smemc_ini.str());
1406	clusters[x][y]->xram->print_trace();
1407	std::ostringstream sxram_tgt;
1408	sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y;
1409	clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(
1410	sxram_tgt.str());
1411	}
1412
1413	// trace iob, iox and external peripherals
1414	if ( debug_iob ) {
1415	clusters[0][0]->iob->print_trace();
1416	clusters[0][0]->signal_int_vci_tgt_iobx.print_trace(
1417	"[SIG]IOB0_INT_TGT");
1418	clusters[0][0]->signal_int_vci_ini_iobx.print_trace(
1419	"[SIG]IOB0_INT_INI");
1420	clusters[0][0]->signal_ram_vci_ini_iobx.print_trace(
1421	"[SIG]IOB0_RAM_INI");
1422
1423	signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
1424	signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
1425
1426	cdma->print_trace();
1427	signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT");
1428	signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI");
1429
1430	iox_network->print_trace();
1431
1432	// interrupts
1433	if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED"
1434	<< std::endl;
1435	}
1436	}
1437	sc_start(sc_core::sc_time(1, SC_NS));
1438	}
1439
1440	delete iox_network;
1441	delete mnic;
1442	delete fbuf;
1443	delete bdev;
1444	delete cdma;
1445	delete mtty;
1446
1447	for(size_t x = 0; x < x_size; x++) {
1448	for(size_t y = 0; y < y_size; y++) {
1449	delete clusters[x][y];
1450	}
1451	}
1452	return EXIT_SUCCESS;
1453	}
1454
1455	int sc_main (int argc, char *argv[]) {
1456	try {
1457	return _main(argc, argv);
1458	} catch (std::exception &e) {
1459	std::cout << e.what() << std::endl;
1460	} catch (...) {
1461	std::cout << "Unknown exception occured" << std::endl;
1462	throw;
1463	}
1464	return 1;
1465	}
1466
1467
1468	// Local Variables:
1469	// tab-width: 3
1470	// c-basic-offset: 3
1471	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1472	// indent-tabs-mode: nil
1473	// End:
1474
1475	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
1476

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Project-Id-Version: Trac 0.12
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