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top.cpp@ 722

Last change on this file since 722 was 717, checked in by cfuguet, 12 years ago

fault_tolerance/tsar_generic_iob:

introducing the vci_iopic component on the IOX interconnect.

the input hardware interrupts on cluster(0,0) from the external peripherals have been removed because they are connected to the vci_iopic component.

Replacing "ad-hoc" dspin_tsar router by standard dspin_router on the RAM interconnect. To do so, in IO clusters (clusters with IOB) two crossbars are implemented:

+ One for commands which interconnects MEMC and IOB to the

local interface of RAM CMD dspin_router.

+ One for responses which interconnects local interface of RAM

RSP dspin_router to MEMC and IOB.

Considering case of mono cluster platform: Only one IOB must be instantiated.

Modifying IOX memory segments used by IOX network for routing:

+ bugfix: all segments of IOX interconnect must have

global id = 0.

+ Adding XICU segments with special attribute. This

attribute is used by IOB to determine if a command coming
from external DMA peripheral should be routed
through INT or RAM networks.

+ Using bit 32 of physical address to determine if an

external DMA command should be routed through IOB0
or IOB1.

File size: 60.2 KB

Line
1	///////////////////////////////////////////////////////////////////////////////
2	// File: top.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : august 2013
6	// This program is released under the GNU public license
7	//
8	// Modified by: Cesar Fuguet
9	// Modified on: mars 2014
10	///////////////////////////////////////////////////////////////////////////////
11	// This file define a generic TSAR architecture with an IO network emulating
12	// an external bus (i.e. Hypertransport) to access external peripherals:
13	//
14	// - BROM : boot ROM
15	// - FBUF : Frame Buffer
16	// - MTTY : multi TTY (up to 15 channels)
17	// - MNIC : Network controller (up to 2 channels)
18	// - CDMA : Chained Buffer DMA controller (up to 4 channels)
19	// - BDEV : Dlock Device controler (1 channel)
20	//
21	// The internal physical address space is 40 bits.
22	//
23	// It contains a 2D mesh of XMAX*YMAX clusters, and the cluster index
24	// is encoded on 8 bits (X_WIDTH = 4 / Y_WIDTH = 4) whatever the mesh size.
25	//
26	// It contains 3 networks:
27	//
28	// 1) the INT network supports Read/Write transactions
29	// between processors and L2 caches or peripherals.
30	// (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits)
31	// It supports also coherence transactions between L1 & L2 caches.
32	// 3) the RAM network is emulating the 3D network between L2 caches
33	// and L3 caches, and is implemented as a 2D mesh between the L2 caches,
34	// the two IO bridges and the physical RAMs disributed in all clusters.
35	// (VCI ADDRESS = 40 bits / VCI DATA = 64 bits)
36	// 4) the IOX network connects the two IO bridge components to the
37	// 6 external peripheral controllers.
38	// (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits)
39	//
40	// The external peripherals IRQs are connected to the XPIC component
41	// in IOX interconnect.
42	//
43	// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1)
44	// contain an extra IO bridge component. These IOB0 & IOB1 components are
45	// connected to the three networks (INT, RAM, IOX).
46	// The number of clusters cannot be larger than 256.
47	// The number of processors per cluster cannot be larger than 4.
48	//
49	// - It uses two dspin_local_crossbar per cluster to implement the
50	// local interconnect correponding to the INT network.
51	// - It uses three dspin_local_crossbar per cluster to implement the
52	// local interconnect correponding to the coherence INT network.
53	// - It uses two virtual_dspin_router per cluster to implement
54	// the INT network (routing both the direct and coherence trafic).
55	// - It uses two dspin_router per cluster to implement the RAM network.
56	// - It uses the vci_cc_vcache_wrapper.
57	// - It uses the vci_mem_cache.
58	// - It contains one vci_xicu and one vci_multi_dma per cluster.
59	// - It contains one vci_simple ram per cluster to model the L3 cache.
60	// - It contains one vci_simple_rom per cluster which can be used for a
61	// distributed boot.
62	// - It contains one vci_multi_tty per cluster for debug purposes (number
63	// of channels can be 0). This TTY is mostly useful when using distributed
64	// boot.
65	//
66	// General policy for 40 bits physical address decoding:
67	// All physical segments base addresses are multiple of 1 Mbytes
68	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
69	// The (x_width + y_width) MSB bits define the cluster index, and the
70	// LADR bits define the local index:
71	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
72	// \|x_width\|y_width\|---\| 8 \| 24 \|
73	//
74	// General policy for 14 bits SRCID decoding:
75	// Each component is identified by (x_id, y_id, l_id) tuple.
76	// \| X_ID \| Y_ID \|---\| L_ID \|
77	// \|x_width\|y_width\|---\| 6 \|
78	/////////////////////////////////////////////////////////////////////////
79
80	#include <systemc>
81	#include <sys/time.h>
82	#include <iostream>
83	#include <sstream>
84	#include <cstdlib>
85	#include <cstdarg>
86	#include <stdint.h>
87	#include <string>
88
89	#include "gdbserver.h"
90	#include "mapping_table.h"
91
92	#include "tsar_iob_cluster.h"
93	#include "vci_chbuf_dma.h"
94	#include "vci_multi_tty.h"
95	#include "vci_multi_nic.h"
96	#include "vci_block_device_tsar.h"
97	#include "vci_framebuffer.h"
98	#include "vci_iopic.h"
99	#include "vci_iox_network.h"
100
101	#include "alloc_elems.h"
102	#include "hard_config.h"
103
104	////////////////////////////////////////////////////////////////////////
105	// Parallelization
106	////////////////////////////////////////////////////////////////////////
107
108	#define USE_OPENMP 0
109
110	#if USE_OPENMP
111	#include <omp.h>
112	#endif
113
114	////////////////////////////////////////////////////////////////////////
115	// DSPIN parameters
116	////////////////////////////////////////////////////////////////////////
117
118	#define dspin_int_cmd_width 39
119	#define dspin_int_rsp_width 32
120
121	#define dspin_ram_cmd_width 64
122	#define dspin_ram_rsp_width 64
123
124	////////////////////////////////////////////////////////////////////////
125	// VCI fields width for the 3 VCI networks
126	////////////////////////////////////////////////////////////////////////
127
128	#define vci_cell_width_int 4
129	#define vci_cell_width_ext 8
130
131	#define vci_plen_width 8
132	#define vci_address_width 40
133	#define vci_rerror_width 1
134	#define vci_clen_width 1
135	#define vci_rflag_width 1
136	#define vci_srcid_width 14
137	#define vci_pktid_width 4
138	#define vci_trdid_width 4
139	#define vci_wrplen_width 1
140
141	////////////////////////////////////////////////////////////////////////
142	// Secondary Hardware Parameters values
143	////////////////////////////////////////////////////////////////////////
144
145	#define XRAM_LATENCY 0
146
147	#define MEMC_WAYS 16
148	#define MEMC_SETS 256
149
150	#define L1_IWAYS 4
151	#define L1_ISETS 64
152
153	#define L1_DWAYS 4
154	#define L1_DSETS 64
155
156	#define FBUF_X_SIZE 128
157	#define FBUF_Y_SIZE 128
158
159	#define BDEV_SECTOR_SIZE 512
160	#define BDEV_IMAGE_NAME "/dev/null"
161
162	#define NIC_RX_NAME "/dev/null"
163	#define NIC_TX_NAME "/dev/null"
164	#define NIC_TIMEOUT 10000
165
166	#define cluster(x,y) TsarIobClusterType::clusterId((x),(y))
167
168	////////////////////////////////////////////////////////////////////////
169	// Software to be loaded in ROM & RAM
170	////////////////////////////////////////////////////////////////////////
171
172	#define BOOT_SOFT_NAME "/dev/null"
173
174	////////////////////////////////////////////////////////////////////////
175	// DEBUG Parameters default values
176	////////////////////////////////////////////////////////////////////////
177
178	#define MAX_FROZEN_CYCLES 10000
179
180	////////////////////////////////////////////////////////////////////////
181	// SRCID definition
182	////////////////////////////////////////////////////////////////////////
183	// All initiators are in the same indexing space (14 bits).
184	// The SRCID is structured in two fields:
185	// - The 10 MSB bits define the cluster index
186	// - The 4 LSB bits define the local index.
187	// Two different initiators cannot have the same SRCID, but a given
188	// initiator can have two alias SRCIDs:
189	// - Internal initiators (procs, mdma) are replicated in all clusters,
190	// and each initiator has one single SRCID.
191	// - External initiators (bdev, cdma) are not replicated, but can be
192	// accessed in 2 clusters : cluster_iob0 and cluster_iob1.
193	// They have the same local index, but two different cluster indexes.
194	// As cluster_iob0 and cluster_iob1 contain both internal initiators
195	// and external initiators, they must have different local indexes.
196	// Consequence: For a local interconnect, the INI_ID port index
197	// is NOT equal to the SRCID local index, and the local interconnect
198	// must make a translation: SRCID => INI_ID (port index)
199	////////////////////////////////////////////////////////////////////////
200
201	#define PROC_LOCAL_SRCID 0x0 // from 0 to 7
202	#define MDMA_LOCAL_SRCID 0x8
203	#define IOBX_LOCAL_SRCID 0x9
204	#define CDMA_LOCAL_SRCID 0xA
205	#define BDEV_LOCAL_SRCID 0xB
206	#define XPIC_LOCAL_SRCID 0xC
207
208	///////////////////////////////////////////////////////////////////////
209	// TGT_ID and INI_ID port indexing for IOX local interconnect
210	///////////////////////////////////////////////////////////////////////
211
212	#define IOX_FBUF_TGT_ID 0
213	#define IOX_BDEV_TGT_ID 1
214	#define IOX_MNIC_TGT_ID 2
215	#define IOX_CDMA_TGT_ID 3
216	#define IOX_MTTY_TGT_ID 4
217	#define IOX_XPIC_TGT_ID 5
218	#define IOX_IOB0_TGT_ID 6
219	#define IOX_IOB1_TGT_ID 7
220
221	#define IOX_BDEV_INI_ID 0
222	#define IOX_CDMA_INI_ID 1
223	#define IOX_XPIC_INI_ID 2
224	#define IOX_IOB0_INI_ID 3
225	#define IOX_IOB1_INI_ID 4
226
227	////////////////////////////////////////////////////////////////////////
228	int _main(int argc, char *argv[]) {
229	using namespace sc_core;
230	using namespace soclib::caba;
231	using namespace soclib::common;
232
233	char soft_name[256] = BOOT_SOFT_NAME; // path: binary code
234	uint64_t ncycles = 1000000000; // simulated cycles
235	char disk_name[256] = BDEV_IMAGE_NAME; // path: disk image
236	char nic_rx_name[256] = NIC_RX_NAME; // path: rx packets file
237	char nic_tx_name[256] = NIC_TX_NAME; // path: tx packets file
238	ssize_t threads_nr = 1; // simulator's threads
239	bool debug_ok = false;
240	size_t debug_period = 1; // trace period
241	size_t debug_memc_id = 0xFFFFFFFF; // idx of traced memc
242	size_t debug_proc_id = 0xFFFFFFFF; // idx of traced proc
243	bool debug_iob = false; // trace iobs when true
244	uint32_t debug_from = 0; // trace start cycle
245	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen procs
246	bool distboot = false; // distributed boot
247	const size_t block_size = BDEV_SECTOR_SIZE; // disk block size
248	const size_t x_size = X_SIZE;
249	const size_t y_size = Y_SIZE;
250
251	assert((X_WIDTH == 4) and (Y_WIDTH == 4));
252
253	////////////// command line arguments //////////////////////
254	if (argc > 1) {
255	for (int n = 1; n < argc; n = n + 2) {
256	if ((strcmp(argv[n],"-NCYCLES") == 0) && ((n+1) < argc)) {
257	ncycles = strtoll(argv[n+1], NULL, 0);
258	continue;
259	}
260	if ((strcmp(argv[n],"-SOFT") == 0) && ((n+1) < argc) ) {
261	strcpy(soft_name, argv[n+1]);
262	continue;
263	}
264	if ((strcmp(argv[n],"-DISK") == 0) && ((n+1) < argc) ) {
265	strcpy(disk_name, argv[n+1]);
266	continue;
267	}
268	if ((strcmp(argv[n],"-DEBUG") == 0) && ((n+1) < argc) ) {
269	debug_ok = true;
270	debug_from = strtol(argv[n+1], NULL, 0);
271	continue;
272	}
273	if ((strcmp(argv[n],"-MEMCID") == 0) && ((n+1) < argc) ) {
274	debug_memc_id = strtol(argv[n+1], NULL, 0);
275	size_t x = debug_memc_id >> Y_WIDTH;
276	size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1);
277	assert((x < x_size) && (y < y_size));
278	continue;
279	}
280	if ((strcmp(argv[n],"-IOB") == 0) && ((n+1) < argc) ) {
281	debug_iob = (strtol(argv[n+1], NULL, 0) != 0) ? 1 : 0;
282	continue;
283	}
284	if ((strcmp(argv[n],"-PROCID") == 0) && ((n+1) < argc) ) {
285	debug_proc_id = strtol(argv[n+1], NULL, 0);
286	size_t cluster_xy = debug_proc_id / NB_PROCS ;
287	size_t x = cluster_xy >> Y_WIDTH;
288	size_t y = cluster_xy & ((1 << Y_WIDTH) - 1);
289	assert((x < x_size) && (y < y_size));
290	continue;
291	}
292	if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) {
293	threads_nr = strtol(argv[n+1], NULL, 0);
294	assert(threads_nr > 0);
295	continue;
296	}
297	if ((strcmp(argv[n], "-FROZEN") == 0) && ((n+1) < argc)) {
298	frozen_cycles = strtol(argv[n+1], NULL, 0);
299	assert(frozen_cycles > 0);
300	continue;
301	}
302	if ((strcmp(argv[n], "-PERIOD") == 0) && ((n+1) < argc)) {
303	debug_period = strtol(argv[n+1], NULL, 0);
304	assert(debug_period > 0);
305	continue;
306	}
307	if ((strcmp(argv[n], "-DISTBOOT") == 0)) {
308	distboot = true;
309	continue;
310	}
311
312	std::cout
313	<< "\nArguments are (key,value) couples."
314	<< "\nThe order is not important."
315	<< "\nAccepted arguments are :\n"
316	<< "\n -NCYCLES number of simulated_cycles"
317	<< "\n -SOFT pathname for embedded soft"
318	<< "\n -DISK pathname for disk image"
319	<< "\n -DEBUG debug start cycle"
320	<< "\n -MEMCID index of memc to trace"
321	<< "\n -IOB debug IOBs if non_zero_value"
322	<< "\n -PROCID index of proc to trace"
323	<< "\n -THREADS simulator's threads number"
324	<< "\n -FROZEN max number of frozen cycles"
325	<< "\n -PERIOD number of cycles between trace"
326	<< "\n -DISTBOOT use distributed boot ROM"
327	<< "\n (processors physical address extention is"
328	<< "\n initialized with local cluster id)"
329	<< std::endl;
330
331	exit(0);
332	}
333	}
334
335	assert( (NB_TTY_CHANNELS < 16) and
336	"The NB_TTY_CHANNELS parameter must be smaller than 16" );
337
338	assert( (NB_NIC_CHANNELS == 1) and
339	"The NB_NIC_CHANNELS parameter must be 1" );
340
341	assert( (x_size > 0) and (y_size > 0) and
342	"Number of clusters on X and Y must be at least 1" );
343
344	std::cout << "\n- X_SIZE = " << x_size
345	<< "\n- Y_SIZE = " << y_size
346	<< "\n- NB_PROCS = " << NB_PROCS
347	<< "\n- NB_DMA_CHANNELS = " << NB_DMA_CHANNELS
348	<< "\n- NB_TTY_CHANNELS = " << NB_TTY_CHANNELS
349	<< "\n- NB_NIC_CHANNELS = " << NB_NIC_CHANNELS
350	<< "\n- MEMC_WAYS = " << MEMC_WAYS
351	<< "\n- MEMC_SETS = " << MEMC_SETS
352	<< "\n- RAM_LATENCY = " << XRAM_LATENCY
353	<< "\n- MAX_FROZEN = " << frozen_cycles
354	<< "\n- DISTBOOT = " << distboot
355	<< std::endl;
356
357	std::cout << std::endl;
358
359	#if USE_OPENMP
360	omp_set_dynamic(false);
361	omp_set_num_threads(threads_nr);
362	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
363	#endif
364
365	// Define VciParams objects
366	typedef soclib::caba::VciParams<vci_cell_width_int,
367	vci_plen_width,
368	vci_address_width,
369	vci_rerror_width,
370	vci_clen_width,
371	vci_rflag_width,
372	vci_srcid_width,
373	vci_pktid_width,
374	vci_trdid_width,
375	vci_wrplen_width> vci_param_int;
376
377	typedef soclib::caba::VciParams<vci_cell_width_ext,
378	vci_plen_width,
379	vci_address_width,
380	vci_rerror_width,
381	vci_clen_width,
382	vci_rflag_width,
383	vci_srcid_width,
384	vci_pktid_width,
385	vci_trdid_width,
386	vci_wrplen_width> vci_param_ext;
387
388	// Clusters
389	typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width,
390	dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width>
391	TsarIobClusterType;
392
393	// clusters containing IOB0 and IOB1
394	size_t cluster_iob0 = cluster(0, 0);
395	size_t cluster_iob1 = cluster(x_size - 1, y_size - 1);
396
397	// using mono cluster configuration (only one IO bridge) ?
398	bool is_mono_cluster = ((x_size == 1) && (y_size == 1));
399
400	/////////////////////////////////////////////////////////////////////
401	// INT network mapping table
402	// - two levels address decoding for commands
403	// - two levels srcid decoding for responses
404	// - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster
405	// - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster
406	/////////////////////////////////////////////////////////////////////
407	MappingTable maptab_int(
408	vci_address_width,
409	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
410	IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH),
411	0x00FF000000);
412
413	for (size_t x = 0; x < x_size; x++) {
414	for (size_t y = 0; y < y_size; y++) {
415	uint64_t offset = ((uint64_t)cluster(x,y))
416	<< (vci_address_width - X_WIDTH - Y_WIDTH);
417	const bool config = true;
418	const bool cacheable = true;
419
420	// the five following segments are defined in all clusters
421
422	std::ostringstream smemc_conf;
423	smemc_conf << "int_seg_memc_conf_" << x << "_" << y;
424	maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE,
425	IntTab(cluster(x,y),INT_MEMC_TGT_ID),
426	not cacheable, config ));
427
428	std::ostringstream smemc_xram;
429	smemc_xram << "int_seg_memc_xram_" << x << "_" << y;
430	maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE,
431	IntTab(cluster(x,y),INT_MEMC_TGT_ID),
432	cacheable));
433
434	std::ostringstream sxicu;
435	sxicu << "int_seg_xicu_" << x << "_" << y;
436	maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE,
437	IntTab(cluster(x,y),INT_XICU_TGT_ID),
438	not cacheable));
439
440	std::ostringstream sbrom;
441	sbrom << "int_seg_brom_" << x << "_" << y;
442	maptab_int.add(Segment(sbrom.str(), BROM_BASE+offset, BROM_SIZE,
443	IntTab(cluster(x,y),INT_BROM_TGT_ID),
444	cacheable));
445
446	std::ostringstream smtty;
447	smtty << "int_seg_mtty_" << x << "_" << y;
448	maptab_int.add(Segment(smtty.str(), MTTY_BASE+offset, MTTY_SIZE,
449	IntTab(cluster(x,y),INT_MTTY_TGT_ID),
450	not cacheable));
451
452	std::ostringstream smdma;
453	smdma << "int_seg_mdma_" << x << "_" << y;
454	maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE,
455	IntTab(cluster(x,y),INT_MDMA_TGT_ID),
456	not cacheable));
457
458	// the following segments are only defined in cluster_iob0 or in
459	// cluster_iob1
460	if ((cluster(x,y) == cluster_iob0) \|\|
461	(cluster(x,y) == cluster_iob1)) {
462	std::ostringstream siobx;
463	siobx << "int_seg_iobx_" << x << "_" << y;
464	maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE,
465	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
466	not cacheable, config ));
467
468	std::ostringstream stty;
469	stty << "int_seg_mtty_" << x << "_" << y;
470	maptab_int.add(Segment(stty.str(), XTTY_BASE+offset, XTTY_SIZE,
471	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
472	not cacheable));
473
474	std::ostringstream sfbf;
475	sfbf << "int_seg_fbuf_" << x << "_" << y;
476	maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE,
477	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
478	not cacheable));
479
480	std::ostringstream sbdv;
481	sbdv << "int_seg_bdev_" << x << "_" << y;
482	maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE,
483	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
484	not cacheable));
485
486	std::ostringstream snic;
487	snic << "int_seg_mnic_" << x << "_" << y;
488	maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE,
489	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
490	not cacheable));
491
492	std::ostringstream sdma;
493	sdma << "int_seg_cdma_" << x << "_" << y;
494	maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE,
495	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
496	not cacheable));
497
498	std::ostringstream spic;
499	sdma << "int_seg_xpic_" << x << "_" << y;
500	maptab_int.add(Segment(spic.str(), XPIC_BASE+offset, XPIC_SIZE,
501	IntTab(cluster(x,y), INT_IOBX_TGT_ID),
502	not cacheable));
503	}
504
505	// This define the mapping between the SRCIDs
506	// and the port index on the local interconnect.
507
508	maptab_int.srcid_map(IntTab(cluster(x,y), MDMA_LOCAL_SRCID),
509	IntTab(cluster(x,y), INT_MDMA_INI_ID));
510	maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID),
511	IntTab(cluster(x,y), INT_IOBX_INI_ID));
512	maptab_int.srcid_map(IntTab(cluster(x,y), XPIC_LOCAL_SRCID),
513	IntTab(cluster(x,y), INT_IOBX_INI_ID));
514
515	for ( size_t p = 0 ; p < NB_PROCS ; p++ ) {
516	maptab_int.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p),
517	IntTab(cluster(x,y), INT_PROC_INI_ID + p));
518	}
519	}
520	}
521	std::cout << "INT network " << maptab_int << std::endl;
522
523	/////////////////////////////////////////////////////////////////////////
524	// RAM network mapping table
525	// - two levels address decoding for commands
526	// - two levels srcid decoding for responses
527	// - 2 local initiators (MEMC, IOBX) per cluster
528	// (IOBX component only in cluster_iob0 and cluster_iob1)
529	// - 1 local target (XRAM) per cluster
530	////////////////////////////////////////////////////////////////////////
531	MappingTable maptab_ram(
532	vci_address_width,
533	IntTab(X_WIDTH + Y_WIDTH, 0),
534	IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH),
535	0x00FF000000);
536
537	for (size_t x = 0; x < x_size; x++) {
538	for (size_t y = 0; y < y_size ; y++) {
539	uint64_t offset = ((uint64_t)cluster(x,y))
540	<< (vci_address_width - X_WIDTH - Y_WIDTH);
541
542	std::ostringstream sxram;
543	sxram << "ext_seg_xram_" << x << "_" << y;
544	maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, XRAM_SIZE,
545	IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false));
546	}
547	}
548
549	// This define the mapping between the initiators SRCID
550	// and the port index on the RAM local interconnect.
551	// External initiator have two alias SRCID (iob0 / iob1)
552
553	maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
554	IntTab(cluster_iob0, RAM_IOBX_INI_ID));
555	maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
556	IntTab(cluster_iob0, RAM_IOBX_INI_ID));
557	maptab_ram.srcid_map(IntTab(cluster_iob0, XPIC_LOCAL_SRCID),
558	IntTab(cluster_iob0, RAM_IOBX_INI_ID));
559	maptab_ram.srcid_map(IntTab(cluster_iob0, RAM_MEMC_INI_ID),
560	IntTab(cluster_iob0, RAM_MEMC_INI_ID));
561
562	if (not is_mono_cluster) {
563	maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
564	IntTab(cluster_iob1, RAM_IOBX_INI_ID));
565	maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
566	IntTab(cluster_iob1, RAM_IOBX_INI_ID));
567	maptab_ram.srcid_map(IntTab(cluster_iob1, XPIC_LOCAL_SRCID),
568	IntTab(cluster_iob1, RAM_IOBX_INI_ID));
569	maptab_ram.srcid_map(IntTab(cluster_iob1, RAM_MEMC_INI_ID),
570	IntTab(cluster_iob1, RAM_MEMC_INI_ID));
571	}
572
573	std::cout << "RAM network " << maptab_ram << std::endl;
574
575	///////////////////////////////////////////////////////////////////////
576	// IOX network mapping table
577	// - two levels address decoding for commands
578	// - two levels srcid decoding for responses
579	// - 4 initiators (IOB0, IOB1, BDEV, CDMA)
580	// - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC)
581	///////////////////////////////////////////////////////////////////////
582
583	const size_t iox_addr_drop_bits = X_WIDTH + Y_WIDTH - 1;
584	const size_t iox_addr_decd_bits = 16 - X_WIDTH - Y_WIDTH + 1;
585	MappingTable maptab_iox(
586	vci_address_width,
587	IntTab(iox_addr_drop_bits, iox_addr_decd_bits),
588	IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH),
589	0x00FF000000);
590
591
592	// Each peripheral can be accessed through two segments,
593	// depending on the used IOB (IOB0 or IOB1).
594
595	uint64_t iob0_base = ((uint64_t)cluster_iob0)
596	<< (vci_address_width - X_WIDTH - Y_WIDTH);
597
598	maptab_iox.add(Segment("iox_seg_mtty_0", XTTY_BASE + iob0_base, XTTY_SIZE,
599	IntTab(0, IOX_MTTY_TGT_ID), false));
600	maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE,
601	IntTab(0, IOX_FBUF_TGT_ID), false));
602	maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE,
603	IntTab(0, IOX_BDEV_TGT_ID), false));
604	maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE,
605	IntTab(0, IOX_MNIC_TGT_ID), false));
606	maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE,
607	IntTab(0, IOX_CDMA_TGT_ID), false));
608	maptab_iox.add(Segment("iox_seg_xpic_0", XPIC_BASE + iob0_base, XPIC_SIZE,
609	IntTab(0, IOX_XPIC_TGT_ID), false));
610
611	if (not is_mono_cluster) {
612	uint64_t iob1_base = ((uint64_t)cluster_iob1)
613	<< (vci_address_width - X_WIDTH - Y_WIDTH);
614
615	maptab_iox.add(Segment("iox_seg_mtty_1", XTTY_BASE + iob1_base,
616	XTTY_SIZE, IntTab(0, IOX_MTTY_TGT_ID), false));
617	maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base,
618	FBUF_SIZE, IntTab(0, IOX_FBUF_TGT_ID), false));
619	maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base,
620	BDEV_SIZE, IntTab(0, IOX_BDEV_TGT_ID), false));
621	maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base,
622	MNIC_SIZE, IntTab(0, IOX_MNIC_TGT_ID), false));
623	maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base,
624	CDMA_SIZE, IntTab(0, IOX_CDMA_TGT_ID), false));
625	maptab_iox.add(Segment("iox_seg_xpic_1", XPIC_BASE + iob1_base,
626	XPIC_SIZE, IntTab(0, IOX_XPIC_TGT_ID), false));
627	}
628
629	///////////////////////////////////////////////////////////////////////////
630	// - For external DMA peripherals, each physical RAM and replicated
631	// XICU can be accessed through IOB0, or through IOB1 depending on address
632	// bit A[32] (0 => IOB0, 1 => IOB1).
633	//
634	// NOTE: the special attribute in the XICU segments is used by the IOB to
635	// route commands through the INT network. The commands on not special
636	// segments (RAM) are routed by the IOB through the RAM network
637	//
638	// NOTE: The IOX interconnect is implemented as a local interconnect because
639	// the global bits need to be dropped, but no locality check is
640	// performed
641	///////////////////////////////////////////////////////////////////////////
642
643	for (size_t x = 0; x < x_size; x++) {
644	for (size_t y = 0; y < y_size ; y++) {
645	const bool special = true;
646	const bool cacheable = true;
647
648	const uint64_t offset = static_cast<uint64_t>(cluster(x,y))
649	<< (vci_address_width - X_WIDTH - Y_WIDTH);
650
651	const uint64_t xicu_base = XICU_BASE + offset;
652	if ( (y & 0x1) == 0 ) {
653	// segments mapped to IOB0
654	std::ostringstream sxcu0;
655	sxcu0 << "iox_seg_xcu0_" << x << "_" << y;
656	maptab_iox.add(Segment(sxcu0.str(), xicu_base, XICU_SIZE,
657	IntTab(0, IOX_IOB0_TGT_ID), not cacheable, special));
658
659	std::ostringstream sram0;
660	sram0 << "iox_seg_ram0_" << x << "_" << y;
661	maptab_iox.add(Segment(sram0.str(), offset, XICU_BASE,
662	IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not special));
663	} else {
664	// segments mapped to IOB1
665	std::ostringstream sxcu1;
666	sxcu1 << "iox_seg_xcu1_" << x << "_" << y;
667	maptab_iox.add(Segment(sxcu1.str(), xicu_base \| (1ULL<<32), XICU_SIZE,
668	IntTab(0, IOX_IOB1_TGT_ID), not cacheable, special));
669
670	std::ostringstream sram1;
671	sram1 << "iox_seg_ram1_" << x << "_" << y;
672	maptab_iox.add(Segment(sram1.str(), offset \| (1ULL<<32), XICU_BASE,
673	IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not special));
674	}
675	}
676	}
677
678	// This define the mapping between the initiators (identified by the SRCID)
679	// and the port index on the IOX local interconnect.
680
681	maptab_iox.srcid_map(IntTab(0, CDMA_LOCAL_SRCID),
682	IntTab(0, IOX_CDMA_INI_ID));
683	maptab_iox.srcid_map(IntTab(0, BDEV_LOCAL_SRCID),
684	IntTab(0, IOX_BDEV_INI_ID));
685	maptab_iox.srcid_map(IntTab(0, XPIC_LOCAL_SRCID),
686	IntTab(0, IOX_XPIC_INI_ID));
687	maptab_iox.srcid_map(IntTab(0, IOX_IOB0_INI_ID),
688	IntTab(0, IOX_IOB0_INI_ID));
689
690	if (not is_mono_cluster) {
691	maptab_iox.srcid_map(IntTab(0, IOX_IOB1_INI_ID),
692	IntTab(0, IOX_IOB1_INI_ID));
693	}
694
695	std::cout << "IOX network " << maptab_iox << std::endl;
696
697	////////////////////
698	// Signals
699	////////////////////
700
701	sc_clock signal_clk("clk");
702	sc_signal<bool> signal_resetn("resetn");
703
704	sc_signal<bool> signal_irq_false;
705	sc_signal<bool> signal_irq_bdev;
706	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
707	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
708	sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS];
709	sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2];
710
711	// DSPIN signals for loopback in cluster_iob0 & cluster_iob1
712	DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback;
713	DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback;
714	DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback;
715	DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback;
716
717	// VCI signals for IOX network
718	VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0");
719	VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1");
720	VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev");
721	VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma");
722	VciSignals<vci_param_ext> signal_vci_ini_xpic("signal_vci_ini_xpic");
723
724	VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0");
725	VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1");
726	VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
727	VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
728	VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
729	VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
730	VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
731	VciSignals<vci_param_ext> signal_vci_tgt_xpic("signal_vci_tgt_xpic");
732
733	// Horizontal inter-clusters INT network DSPIN
734	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc =
735	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
736	"signal_dspin_int_cmd_h_inc", x_size-1, y_size, 3);
737	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec =
738	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
739	"signal_dspin_int_cmd_h_dec", x_size-1, y_size, 3);
740	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc =
741	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
742	"signal_dspin_int_rsp_h_inc", x_size-1, y_size, 2);
743	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec =
744	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
745	"signal_dspin_int_rsp_h_dec", x_size-1, y_size, 2);
746
747	// Vertical inter-clusters INT network DSPIN
748	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc =
749	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
750	"signal_dspin_int_cmd_v_inc", x_size, y_size-1, 3);
751	DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec =
752	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
753	"signal_dspin_int_cmd_v_dec", x_size, y_size-1, 3);
754	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc =
755	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
756	"signal_dspin_int_rsp_v_inc", x_size, y_size-1, 2);
757	DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec =
758	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
759	"signal_dspin_int_rsp_v_dec", x_size, y_size-1, 2);
760
761	// Mesh boundaries INT network DSPIN
762	DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in =
763	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
764	"signal_dspin_false_int_cmd_in", x_size, y_size, 4, 3);
765	DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out =
766	alloc_elems<DspinSignals<dspin_int_cmd_width> >(
767	"signal_dspin_false_int_cmd_out", x_size, y_size, 4, 3);
768	DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in =
769	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
770	"signal_dspin_false_int_rsp_in", x_size, y_size, 4, 2);
771	DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out =
772	alloc_elems<DspinSignals<dspin_int_rsp_width> >(
773	"signal_dspin_false_int_rsp_out", x_size, y_size, 4, 2);
774
775
776	// Horizontal inter-clusters RAM network DSPIN
777	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc =
778	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
779	"signal_dspin_ram_cmd_h_inc", x_size-1, y_size);
780	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec =
781	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
782	"signal_dspin_ram_cmd_h_dec", x_size-1, y_size);
783	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc =
784	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
785	"signal_dspin_ram_rsp_h_inc", x_size-1, y_size);
786	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec =
787	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
788	"signal_dspin_ram_rsp_h_dec", x_size-1, y_size);
789
790	// Vertical inter-clusters RAM network DSPIN
791	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc =
792	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
793	"signal_dspin_ram_cmd_v_inc", x_size, y_size-1);
794	DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec =
795	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
796	"signal_dspin_ram_cmd_v_dec", x_size, y_size-1);
797	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc =
798	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
799	"signal_dspin_ram_rsp_v_inc", x_size, y_size-1);
800	DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec =
801	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
802	"signal_dspin_ram_rsp_v_dec", x_size, y_size-1);
803
804	// Mesh boundaries RAM network DSPIN
805	DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in =
806	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
807	"signal_dspin_false_ram_cmd_in", x_size, y_size, 4);
808	DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out =
809	alloc_elems<DspinSignals<dspin_ram_cmd_width> >(
810	"signal_dspin_false_ram_cmd_out", x_size, y_size, 4);
811	DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in =
812	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
813	"signal_dspin_false_ram_rsp_in", x_size, y_size, 4);
814	DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out =
815	alloc_elems<DspinSignals<dspin_ram_rsp_width> >(
816	"signal_dspin_false_ram_rsp_out", x_size, y_size, 4);
817
818	////////////////////////////
819	// Loader
820	////////////////////////////
821
822	soclib::common::Loader loader(soft_name);
823
824	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
825	proc_iss::set_loader(loader);
826
827	////////////////////////////////////////
828	// Instanciated Hardware Components
829	////////////////////////////////////////
830
831	std::cout << std::endl << "External Bus and Peripherals" << std::endl
832	<< std::endl;
833
834	const size_t nb_iox_initiators = (not is_mono_cluster) ? 5 : 4;
835	const size_t nb_iox_targets = (not is_mono_cluster) ? 8 : 7;
836
837	// IOX network
838	VciIoxNetwork<vci_param_ext>* iox_network;
839	iox_network = new VciIoxNetwork<vci_param_ext>("iox_network",
840	maptab_iox,
841	nb_iox_targets, // number of targets
842	nb_iox_initiators ); // number of initiators
843
844	// Network Controller
845	VciMultiNic<vci_param_ext>* mnic;
846	mnic = new VciMultiNic<vci_param_ext>("mnic",
847	IntTab(0, IOX_MNIC_TGT_ID),
848	maptab_iox,
849	NB_NIC_CHANNELS,
850	0, // mac_4 address
851	0, // mac_2 address
852	nic_rx_name,
853	nic_tx_name);
854
855	// Frame Buffer
856	VciFrameBuffer<vci_param_ext>* fbuf;
857	fbuf = new VciFrameBuffer<vci_param_ext>("fbuf",
858	IntTab(0, IOX_FBUF_TGT_ID),
859	maptab_iox,
860	FBUF_X_SIZE, FBUF_Y_SIZE );
861
862	// Block Device
863	// for AHCI
864	// std::vector<std::string> filenames;
865	// filenames.push_back(disk_name); // one single disk
866	VciBlockDeviceTsar<vci_param_ext>* bdev;
867	bdev = new VciBlockDeviceTsar<vci_param_ext>("bdev",
868	maptab_iox,
869	IntTab(0, BDEV_LOCAL_SRCID),
870	IntTab(0, IOX_BDEV_TGT_ID),
871	disk_name,
872	block_size,
873	64, // burst size (bytes)
874	0 ); // disk latency
875
876	// Chained Buffer DMA controller
877	VciChbufDma<vci_param_ext>* cdma;
878	cdma = new VciChbufDma<vci_param_ext>("cdma",
879	maptab_iox,
880	IntTab(0, CDMA_LOCAL_SRCID),
881	IntTab(0, IOX_CDMA_TGT_ID),
882	64, // burst size (bytes)
883	NB_CMA_CHANNELS);
884
885	// Multi-TTY controller
886	std::vector<std::string> vect_names;
887	for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ )
888	{
889	std::ostringstream term_name;
890	term_name << "mtty_iox_" << tid;
891	vect_names.push_back(term_name.str().c_str());
892	}
893	VciMultiTty<vci_param_ext>* mtty;
894	mtty = new VciMultiTty<vci_param_ext>("mtty_iox",
895	IntTab(0, IOX_MTTY_TGT_ID),
896	maptab_iox,
897	vect_names);
898
899	// IOPIC
900	VciIopic<vci_param_ext>* xpic;
901	xpic = new VciIopic<vci_param_ext>( "xpic",
902	maptab_iox,
903	IntTab(0, XPIC_LOCAL_SRCID),
904	IntTab(0, IOX_XPIC_TGT_ID),
905	32 ); // number of input HWI
906
907
908	TsarIobClusterType* clusters[x_size][y_size];
909
910	#if USE_OPENMP
911	#pragma omp parallel
912	{
913	#pragma omp for
914	#endif
915
916	for(size_t i = 0; i < (x_size * y_size); i++) {
917	size_t x = i / y_size;
918	size_t y = i % y_size;
919
920	#if USE_OPENMP
921	#pragma omp critical
922	{
923	#endif
924	std::cout << std::endl;
925	std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl;
926	std::cout << std::endl;
927
928	std::ostringstream sc;
929	sc << "cluster_" << x << "_" << y;
930
931	bool memc_debug = (cluster(x,y) == debug_memc_id);
932	bool proc_debug = (cluster(x,y) == (debug_proc_id / NB_PROCS));
933
934	bool is_io0 = (cluster(x,y) == cluster_iob0);
935	bool is_io1 = (cluster(x,y) == cluster_iob1);
936	bool is_io = is_io0 \|\| is_io1;
937
938	IntTab iox_iob_tgtid =
939	IntTab(0, is_io0 ? IOX_IOB0_TGT_ID : IOX_IOB1_TGT_ID);
940	IntTab iox_iob_srcid =
941	IntTab(0, is_io0 ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID);
942
943	TsarIobClusterType::ClusterParams params = {
944	.insname = sc.str().c_str(),
945
946	.x_id = x,
947	.y_id = y,
948
949	.mt_int = maptab_int,
950	.mt_ext = maptab_ram,
951	.mt_iox = maptab_iox,
952
953	.is_io = is_io,
954	.iox_iob_tgtid = iox_iob_tgtid,
955	.iox_iob_srcid = iox_iob_srcid,
956
957	.memc_ways = MEMC_WAYS,
958	.memc_sets = MEMC_SETS,
959	.l1_i_ways = L1_IWAYS,
960	.l1_i_sets = L1_ISETS,
961	.l1_d_ways = L1_DWAYS,
962	.l1_d_sets = L1_DSETS,
963	.xram_latency = XRAM_LATENCY,
964
965	.loader = loader,
966
967	.distboot = distboot,
968
969	.frozen_cycles = frozen_cycles,
970	.debug_start_cycle = debug_from,
971	.memc_debug_ok = memc_debug,
972	.proc_debug_ok = proc_debug,
973	.iob_debug_ok = debug_iob
974	};
975
976	clusters[x][y] = new TsarIobClusterType(params);
977
978	#if USE_OPENMP
979	} // end critical
980	#endif
981	} // end for
982	#if USE_OPENMP
983	}
984	#endif
985
986	std::cout << std::endl;
987
988	///////////////////////////////////////////////////////////////////////////
989	// Net-list
990	///////////////////////////////////////////////////////////////////////////
991
992	// IOX network connexion
993	iox_network->p_clk (signal_clk);
994	iox_network->p_resetn (signal_resetn);
995	iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev);
996	iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma);
997	iox_network->p_to_ini[IOX_XPIC_INI_ID] (signal_vci_ini_xpic);
998	iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0);
999	iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty);
1000	iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf);
1001	iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic);
1002	iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev);
1003	iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma);
1004	iox_network->p_to_tgt[IOX_XPIC_TGT_ID] (signal_vci_tgt_xpic);
1005	iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0);
1006
1007	if (not is_mono_cluster) {
1008	iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1);
1009	iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1);
1010	}
1011
1012	// BDEV connexion
1013	bdev->p_clk (signal_clk);
1014	bdev->p_resetn (signal_resetn);
1015	bdev->p_irq (signal_irq_bdev);
1016	bdev->p_vci_target (signal_vci_tgt_bdev);
1017	bdev->p_vci_initiator (signal_vci_ini_bdev);
1018
1019	std::cout << " - BDEV connected" << std::endl;
1020
1021	// FBUF connexion
1022	fbuf->p_clk (signal_clk);
1023	fbuf->p_resetn (signal_resetn);
1024	fbuf->p_vci (signal_vci_tgt_fbuf);
1025
1026	std::cout << " - FBUF connected" << std::endl;
1027
1028	// MNIC connexion
1029	mnic->p_clk (signal_clk);
1030	mnic->p_resetn (signal_resetn);
1031	mnic->p_vci (signal_vci_tgt_mnic);
1032	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
1033	{
1034	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
1035	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
1036	}
1037
1038	std::cout << " - MNIC connected" << std::endl;
1039
1040	// MTTY connexion
1041	mtty->p_clk (signal_clk);
1042	mtty->p_resetn (signal_resetn);
1043	mtty->p_vci (signal_vci_tgt_mtty);
1044	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) {
1045	mtty->p_irq[i] (signal_irq_mtty[i]);
1046	}
1047
1048	std::cout << " - MTTY connected" << std::endl;
1049
1050	// CDMA connexion
1051	cdma->p_clk (signal_clk);
1052	cdma->p_resetn (signal_resetn);
1053	cdma->p_vci_target (signal_vci_tgt_cdma);
1054	cdma->p_vci_initiator (signal_vci_ini_cdma);
1055	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++) {
1056	cdma->p_irq[i] (signal_irq_cdma[i]);
1057	}
1058
1059	std::cout << " - CDMA connected" << std::endl;
1060
1061	// XPIC connexion
1062	xpic->p_clk (signal_clk);
1063	xpic->p_resetn (signal_resetn);
1064	xpic->p_vci_target (signal_vci_tgt_xpic);
1065	xpic->p_vci_initiator (signal_vci_ini_xpic);
1066	for ( size_t i=0 ; i<32 ; i++)
1067	{
1068	if (i < NB_NIC_CHANNELS) xpic->p_hwi[i] (signal_irq_mnic_rx[i]);
1069	else if (i < 2) xpic->p_hwi[i] (signal_irq_false);
1070	else if (i < 2+NB_NIC_CHANNELS) xpic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
1071	else if (i < 4) xpic->p_hwi[i] (signal_irq_false);
1072	else if (i < 4+NB_CMA_CHANNELS) xpic->p_hwi[i] (signal_irq_cdma[i-4]);
1073	else if (i < 8) xpic->p_hwi[i] (signal_irq_false);
1074	else if (i < 9) xpic->p_hwi[i] (signal_irq_bdev);
1075	else if (i < 9+NB_TTY_CHANNELS) xpic->p_hwi[i] (signal_irq_mtty[i-9]);
1076	else xpic->p_hwi[i] (signal_irq_false);
1077	}
1078
1079	std::cout << " - XPIC connected" << std::endl;
1080
1081	// IOB0 cluster connexion to IOX network
1082	(*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0);
1083	(*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0);
1084
1085	// IOB1 cluster connexion to IOX network
1086	if (not is_mono_cluster) {
1087	(*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1);
1088	(*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1);
1089	}
1090
1091	// All clusters Clock & RESET connexions
1092	for ( size_t x = 0; x < (x_size); x++ ) {
1093	for (size_t y = 0; y < y_size; y++) {
1094	clusters[x][y]->p_clk (signal_clk);
1095	clusters[x][y]->p_resetn (signal_resetn);
1096	}
1097	}
1098
1099	const int& NORTH = VirtualDspinRouter<dspin_int_cmd_width>::NORTH;
1100	const int& SOUTH = VirtualDspinRouter<dspin_int_cmd_width>::SOUTH;
1101	const int& EAST = VirtualDspinRouter<dspin_int_cmd_width>::EAST;
1102	const int& WEST = VirtualDspinRouter<dspin_int_cmd_width>::WEST;
1103
1104	// Inter Clusters horizontal connections
1105	if (x_size > 1) {
1106	for (size_t x = 0; x < (x_size-1); x++) {
1107	for (size_t y = 0; y < y_size; y++) {
1108	for (size_t k = 0; k < 3; k++) {
1109	clusters[x][y]->p_dspin_int_cmd_out[EAST][k](
1110	signal_dspin_int_cmd_h_inc[x][y][k]);
1111	clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k](
1112	signal_dspin_int_cmd_h_inc[x][y][k]);
1113	clusters[x][y]->p_dspin_int_cmd_in[EAST][k](
1114	signal_dspin_int_cmd_h_dec[x][y][k]);
1115	clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k](
1116	signal_dspin_int_cmd_h_dec[x][y][k]);
1117	}
1118
1119	for (size_t k = 0; k < 2; k++) {
1120	clusters[x][y]->p_dspin_int_rsp_out[EAST][k](
1121	signal_dspin_int_rsp_h_inc[x][y][k]);
1122	clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k](
1123	signal_dspin_int_rsp_h_inc[x][y][k]);
1124	clusters[x][y]->p_dspin_int_rsp_in[EAST][k](
1125	signal_dspin_int_rsp_h_dec[x][y][k]);
1126	clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k](
1127	signal_dspin_int_rsp_h_dec[x][y][k]);
1128	}
1129
1130	clusters[x][y]->p_dspin_ram_cmd_out[EAST](
1131	signal_dspin_ram_cmd_h_inc[x][y]);
1132	clusters[x+1][y]->p_dspin_ram_cmd_in[WEST](
1133	signal_dspin_ram_cmd_h_inc[x][y]);
1134	clusters[x][y]->p_dspin_ram_cmd_in[EAST](
1135	signal_dspin_ram_cmd_h_dec[x][y]);
1136	clusters[x+1][y]->p_dspin_ram_cmd_out[WEST](
1137	signal_dspin_ram_cmd_h_dec[x][y]);
1138	clusters[x][y]->p_dspin_ram_rsp_out[EAST](
1139	signal_dspin_ram_rsp_h_inc[x][y]);
1140	clusters[x+1][y]->p_dspin_ram_rsp_in[WEST](
1141	signal_dspin_ram_rsp_h_inc[x][y]);
1142	clusters[x][y]->p_dspin_ram_rsp_in[EAST](
1143	signal_dspin_ram_rsp_h_dec[x][y]);
1144	clusters[x+1][y]->p_dspin_ram_rsp_out[WEST](
1145	signal_dspin_ram_rsp_h_dec[x][y]);
1146	}
1147	}
1148	}
1149
1150	std::cout << std::endl << "Horizontal connections established"
1151	<< std::endl;
1152
1153	// Inter Clusters vertical connections
1154	if (y_size > 1) {
1155	for (size_t y = 0; y < (y_size-1); y++) {
1156	for (size_t x = 0; x < x_size; x++) {
1157	for (size_t k = 0; k < 3; k++) {
1158	clusters[x][y]->p_dspin_int_cmd_out[NORTH][k](
1159	signal_dspin_int_cmd_v_inc[x][y][k]);
1160	clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k](
1161	signal_dspin_int_cmd_v_inc[x][y][k]);
1162	clusters[x][y]->p_dspin_int_cmd_in[NORTH][k](
1163	signal_dspin_int_cmd_v_dec[x][y][k]);
1164	clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k](
1165	signal_dspin_int_cmd_v_dec[x][y][k]);
1166	}
1167
1168	for (size_t k = 0; k < 2; k++) {
1169	clusters[x][y]->p_dspin_int_rsp_out[NORTH][k](
1170	signal_dspin_int_rsp_v_inc[x][y][k]);
1171	clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k](
1172	signal_dspin_int_rsp_v_inc[x][y][k]);
1173	clusters[x][y]->p_dspin_int_rsp_in[NORTH][k](
1174	signal_dspin_int_rsp_v_dec[x][y][k]);
1175	clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k](
1176	signal_dspin_int_rsp_v_dec[x][y][k]);
1177	}
1178
1179	clusters[x][y]->p_dspin_ram_cmd_out[NORTH](
1180	signal_dspin_ram_cmd_v_inc[x][y]);
1181	clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH](
1182	signal_dspin_ram_cmd_v_inc[x][y]);
1183	clusters[x][y]->p_dspin_ram_cmd_in[NORTH](
1184	signal_dspin_ram_cmd_v_dec[x][y]);
1185	clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH](
1186	signal_dspin_ram_cmd_v_dec[x][y]);
1187	clusters[x][y]->p_dspin_ram_rsp_out[NORTH](
1188	signal_dspin_ram_rsp_v_inc[x][y]);
1189	clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH](
1190	signal_dspin_ram_rsp_v_inc[x][y]);
1191	clusters[x][y]->p_dspin_ram_rsp_in[NORTH](
1192	signal_dspin_ram_rsp_v_dec[x][y]);
1193	clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH](
1194	signal_dspin_ram_rsp_v_dec[x][y]);
1195	}
1196	}
1197	}
1198
1199	std::cout << "Vertical connections established" << std::endl;
1200
1201	// East & West boundary cluster connections
1202	for (size_t y = 0; y < y_size; y++) {
1203	// L1-L2 cmd network boundary connections
1204	for (size_t k = 0; k < 3; k++) {
1205	clusters[0][y]->p_dspin_int_cmd_in[WEST][k](
1206	signal_dspin_false_int_cmd_in[0][y][WEST][k]);
1207	clusters[0][y]->p_dspin_int_cmd_out[WEST][k](
1208	signal_dspin_false_int_cmd_out[0][y][WEST][k]);
1209	clusters[x_size-1][y]->p_dspin_int_cmd_in[EAST][k](
1210	signal_dspin_false_int_cmd_in[x_size-1][y][EAST][k]);
1211	clusters[x_size-1][y]->p_dspin_int_cmd_out[EAST][k](
1212	signal_dspin_false_int_cmd_out[x_size-1][y][EAST][k]);
1213	}
1214
1215	// L1-L2 rsp network boundary connections
1216	for (size_t k = 0; k < 2; k++) {
1217	clusters[0][y]->p_dspin_int_rsp_in[WEST][k](
1218	signal_dspin_false_int_rsp_in[0][y][WEST][k]);
1219	clusters[0][y]->p_dspin_int_rsp_out[WEST][k](
1220	signal_dspin_false_int_rsp_out[0][y][WEST][k]);
1221	clusters[x_size-1][y]->p_dspin_int_rsp_in[EAST][k](
1222	signal_dspin_false_int_rsp_in[x_size-1][y][EAST][k]);
1223	clusters[x_size-1][y]->p_dspin_int_rsp_out[EAST][k](
1224	signal_dspin_false_int_rsp_out[x_size-1][y][EAST][k]);
1225	}
1226
1227	// L2-XRAM cmd network boundary connections
1228	clusters[0][y]->p_dspin_ram_cmd_in[WEST](
1229	signal_dspin_false_ram_cmd_in[0][y][WEST]);
1230	clusters[0][y]->p_dspin_ram_cmd_out[WEST](
1231	signal_dspin_false_ram_cmd_out[0][y][WEST]);
1232	clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST](
1233	signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]);
1234	clusters[x_size-1][y]->p_dspin_ram_cmd_out[EAST](
1235	signal_dspin_false_ram_cmd_out[x_size-1][y][EAST]);
1236
1237	// L2-XRAM rsp network boundary connections
1238	clusters[0][y]->p_dspin_ram_rsp_in[WEST](
1239	signal_dspin_false_ram_rsp_in[0][y][WEST]);
1240	clusters[0][y]->p_dspin_ram_rsp_out[WEST](
1241	signal_dspin_false_ram_rsp_out[0][y][WEST]);
1242	clusters[x_size-1][y]->p_dspin_ram_rsp_in[EAST](
1243	signal_dspin_false_ram_rsp_in[x_size-1][y][EAST]);
1244	clusters[x_size-1][y]->p_dspin_ram_rsp_out[EAST](
1245	signal_dspin_false_ram_rsp_out[x_size-1][y][EAST]);
1246	}
1247
1248	std::cout << "East & West boundaries established" << std::endl;
1249
1250	// North & South boundary clusters connections
1251	for (size_t x = 0; x < x_size; x++) {
1252	for (size_t k = 0; k < 3; k++) {
1253	clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k](
1254	signal_dspin_false_int_cmd_in[x][0][SOUTH][k]);
1255	clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k](
1256	signal_dspin_false_int_cmd_out[x][0][SOUTH][k]);
1257	clusters[x][y_size-1]->p_dspin_int_cmd_in[NORTH][k](
1258	signal_dspin_false_int_cmd_in[x][y_size-1][NORTH][k]);
1259	clusters[x][y_size-1]->p_dspin_int_cmd_out[NORTH][k](
1260	signal_dspin_false_int_cmd_out[x][y_size-1][NORTH][k]);
1261	}
1262
1263	for (size_t k = 0; k < 2; k++) {
1264	clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k](
1265	signal_dspin_false_int_rsp_in[x][0][SOUTH][k]);
1266	clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k](
1267	signal_dspin_false_int_rsp_out[x][0][SOUTH][k]);
1268	clusters[x][y_size-1]->p_dspin_int_rsp_in[NORTH][k](
1269	signal_dspin_false_int_rsp_in[x][y_size-1][NORTH][k]);
1270	clusters[x][y_size-1]->p_dspin_int_rsp_out[NORTH][k](
1271	signal_dspin_false_int_rsp_out[x][y_size-1][NORTH][k]);
1272	}
1273
1274	clusters[x][0]->p_dspin_ram_cmd_in[SOUTH](
1275	signal_dspin_false_ram_cmd_in[x][0][SOUTH]);
1276	clusters[x][0]->p_dspin_ram_cmd_out[SOUTH](
1277	signal_dspin_false_ram_cmd_out[x][0][SOUTH]);
1278	clusters[x][0]->p_dspin_ram_rsp_in[SOUTH](
1279	signal_dspin_false_ram_rsp_in[x][0][SOUTH]);
1280	clusters[x][0]->p_dspin_ram_rsp_out[SOUTH](
1281	signal_dspin_false_ram_rsp_out[x][0][SOUTH]);
1282
1283	clusters[x][y_size-1]->p_dspin_ram_cmd_in[NORTH](
1284	signal_dspin_false_ram_cmd_in[x][y_size-1][NORTH]);
1285	clusters[x][y_size-1]->p_dspin_ram_cmd_out[NORTH](
1286	signal_dspin_false_ram_cmd_out[x][y_size-1][NORTH]);
1287	clusters[x][y_size-1]->p_dspin_ram_rsp_in[NORTH](
1288	signal_dspin_false_ram_rsp_in[x][y_size-1][NORTH]);
1289	clusters[x][y_size-1]->p_dspin_ram_rsp_out[NORTH](
1290	signal_dspin_false_ram_rsp_out[x][y_size-1][NORTH]);
1291	}
1292
1293	std::cout << "North & South boundaries established" << std::endl
1294	<< std::endl;
1295
1296	////////////////////////////////////////////////////////
1297	// Simulation
1298	///////////////////////////////////////////////////////
1299
1300	sc_start(sc_core::sc_time(0, SC_NS));
1301
1302	signal_resetn = false;
1303	signal_irq_false = false;
1304
1305	// network boundaries signals
1306	for (size_t x = 0; x < x_size ; x++) {
1307	for (size_t y = 0; y < y_size ; y++) {
1308	for (size_t a = 0; a < 4; a++) {
1309	for (size_t k = 0; k < 3; k++) {
1310	signal_dspin_false_int_cmd_in[x][y][a][k].write = false;
1311	signal_dspin_false_int_cmd_in[x][y][a][k].read = true;
1312	signal_dspin_false_int_cmd_out[x][y][a][k].write = false;
1313	signal_dspin_false_int_cmd_out[x][y][a][k].read = true;
1314	}
1315
1316	for (size_t k = 0; k < 2; k++) {
1317	signal_dspin_false_int_rsp_in[x][y][a][k].write = false;
1318	signal_dspin_false_int_rsp_in[x][y][a][k].read = true;
1319	signal_dspin_false_int_rsp_out[x][y][a][k].write = false;
1320	signal_dspin_false_int_rsp_out[x][y][a][k].read = true;
1321	}
1322
1323	signal_dspin_false_ram_cmd_in[x][y][a].write = false;
1324	signal_dspin_false_ram_cmd_in[x][y][a].read = true;
1325	signal_dspin_false_ram_cmd_out[x][y][a].write = false;
1326	signal_dspin_false_ram_cmd_out[x][y][a].read = true;
1327
1328	signal_dspin_false_ram_rsp_in[x][y][a].write = false;
1329	signal_dspin_false_ram_rsp_in[x][y][a].read = true;
1330	signal_dspin_false_ram_rsp_out[x][y][a].write = false;
1331	signal_dspin_false_ram_rsp_out[x][y][a].read = true;
1332	}
1333	}
1334	}
1335
1336	sc_start(sc_core::sc_time(1, SC_NS));
1337	signal_resetn = true;
1338
1339	struct timeval t1, t2;
1340	const uint64_t stats_period = 100000;
1341	gettimeofday(&t1, NULL);
1342	for (uint64_t n = 1; n < ncycles; n++) {
1343	// stats display
1344	if((n % stats_period) == 0) {
1345	gettimeofday(&t2, NULL);
1346
1347	uint64_t ms1 = (uint64_t) t1.tv_sec * 1000 +
1348	(uint64_t) t1.tv_usec / 1000;
1349	uint64_t ms2 = (uint64_t) t2.tv_sec * 1000 +
1350	(uint64_t) t2.tv_usec / 1000;
1351	double freq = (double) stats_period / (ms2 - ms1);
1352
1353	std::cerr << "Platform Clock Frequency: " << freq << " Khz"
1354	<< std::endl;
1355
1356	gettimeofday(&t1, NULL);
1357	}
1358
1359	if (debug_ok and (n > debug_from) and ((n % debug_period) == 0)) {
1360	std::cout << " ***********************"
1361	<< " cycle " << std::dec << n
1362	<< " ***********************"
1363	<< std::endl;
1364
1365	// trace proc[debug_proc_id]
1366	if ( debug_proc_id != 0xFFFFFFFF ) {
1367	size_t l = debug_proc_id % NB_PROCS ;
1368	size_t cluster_xy = debug_proc_id / NB_PROCS ;
1369	size_t x = cluster_xy >> Y_WIDTH;
1370	size_t y = cluster_xy & ((1 << Y_WIDTH) - 1);
1371
1372	clusters[x][y]->proc[l]->print_trace(1);
1373
1374	std::ostringstream proc_signame;
1375	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
1376	clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(
1377	proc_signame.str());
1378
1379	clusters[x][y]->xicu->print_trace(l);
1380
1381	std::ostringstream xicu_signame;
1382	xicu_signame << "[SIG]XICU_" << x << "_" << y;
1383	clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(
1384	xicu_signame.str());
1385
1386	if( clusters[x][y]->signal_proc_it[l].read() ) {
1387	std::cout << "### IRQ_PROC_" << std::dec
1388	<< x << "_" << y << "_" << l
1389	<< " ACTIVE" << std::endl;
1390	}
1391	}
1392
1393	// trace RAM xbar (between MEMC and IOB)
1394	// clusters[0][0]->ram_xbar_cmd->print_trace();
1395	// clusters[0][0]->ram_xbar_rsp->print_trace();
1396	// clusters[x_size-1][y_size-1]->ram_xbar_cmd->print_trace();
1397	// clusters[x_size-1][y_size-1]->ram_xbar_rsp->print_trace();
1398
1399	// trace INT network
1400	// clusters[0][0]->int_xbar_d->print_trace();
1401
1402	// clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace(
1403	// "[SIG] INT_CMD_L2G_D_0_0");
1404	// clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace(
1405	// "[SIG] INT_RSP_G2L_D_0_0");
1406
1407	// clusters[0][0]->int_router_cmd->print_trace(0);
1408	// clusters[0][0]->int_router_rsp->print_trace(0);
1409
1410	// trace INT_CMD_D xbar and router in cluster 0_1
1411	// clusters[0][1]->int_router_cmd->print_trace(0);
1412	// clusters[0][1]->int_router_rsp->print_trace(0);
1413
1414	// clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace(
1415	// "[SIG] INT_CMD_G2L_D_0_0");
1416	// clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace(
1417	// "[SIG] INT_RSP_L2G_D_0_0");
1418
1419	// clusters[0][1]->int_xbar_cmd_d->print_trace();
1420
1421	// trace memc[debug_memc_id]
1422	if ( debug_memc_id != 0xFFFFFFFF ) {
1423	size_t x = debug_memc_id >> Y_WIDTH;
1424	size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1);
1425
1426	clusters[x][y]->memc->print_trace(0);
1427	std::ostringstream smemc_tgt;
1428	smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y;
1429	clusters[x][y]->signal_int_vci_tgt_memc.print_trace(
1430	smemc_tgt.str());
1431	std::ostringstream smemc_ini;
1432	smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y;
1433	clusters[x][y]->signal_ram_vci_ini_memc.print_trace(
1434	smemc_ini.str());
1435	clusters[x][y]->xram->print_trace();
1436	std::ostringstream sxram_tgt;
1437	sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y;
1438	clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(
1439	sxram_tgt.str());
1440	}
1441
1442	// trace iob, iox and external peripherals
1443	//if ( debug_iob ) {
1444	// clusters[0][0]->iob->print_trace();
1445	// clusters[0][0]->signal_int_vci_tgt_iobx.print_trace(
1446	// "[SIG]IOB0_INT_TGT");
1447	// clusters[0][0]->signal_int_vci_ini_iobx.print_trace(
1448	// "[SIG]IOB0_INT_INI");
1449	// clusters[0][0]->signal_ram_vci_ini_iobx.print_trace(
1450	// "[SIG]IOB0_RAM_INI");
1451
1452	// signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
1453	// signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
1454
1455	// cdma->print_trace();
1456	// signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT");
1457	// signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI");
1458
1459	// iox_network->print_trace();
1460
1461	// // interrupts
1462	// if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED"
1463	// << std::endl;
1464	//}
1465	}
1466	sc_start(sc_core::sc_time(1, SC_NS));
1467	}
1468
1469	delete iox_network;
1470	delete mnic;
1471	delete fbuf;
1472	delete bdev;
1473	delete cdma;
1474	delete mtty;
1475	delete xpic;
1476
1477	for(size_t x = 0; x < x_size; x++) {
1478	for(size_t y = 0; y < y_size; y++) {
1479	delete clusters[x][y];
1480	}
1481	}
1482	return EXIT_SUCCESS;
1483	}
1484
1485	int sc_main (int argc, char *argv[]) {
1486	try {
1487	return _main(argc, argv);
1488	} catch (std::exception &e) {
1489	std::cout << e.what() << std::endl;
1490	} catch (...) {
1491	std::cout << "Unknown exception occured" << std::endl;
1492	throw;
1493	}
1494	return 1;
1495	}
1496
1497
1498	// Local Variables:
1499	// tab-width: 3
1500	// c-basic-offset: 3
1501	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1502	// indent-tabs-mode: nil
1503	// End:
1504
1505	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
1506

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source: branches/fault_tolerance/platform/tsar_generic_iob/top.cpp@ 722

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