[724] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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| 12 | // - 2 dspin_local_crossbar for commands and responses. |
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| 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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| 17 | #define tmpl(x) \ |
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| 18 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 19 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 20 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 21 | x TsarIobCluster<\ |
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| 22 | vci_param_int , vci_param_ext,\ |
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| 23 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 24 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 25 | |
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| 26 | namespace soclib { namespace caba { |
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| 27 | |
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| 28 | ////////////////////////////////////////////////////////////////////////// |
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| 29 | // Constructor |
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| 30 | ////////////////////////////////////////////////////////////////////////// |
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| 31 | tmpl(/**/)::TsarIobCluster( |
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| 32 | ////////////////////////////////////////////////////////////////////////// |
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| 33 | sc_module_name insname, |
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| 34 | size_t nb_procs, |
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| 35 | size_t nb_dmas, |
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| 36 | size_t x_id, |
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| 37 | size_t y_id, |
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| 38 | size_t xmax, |
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| 39 | size_t ymax, |
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| 40 | |
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| 41 | const soclib::common::MappingTable &mt_int, |
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| 42 | const soclib::common::MappingTable &mt_ram, |
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| 43 | const soclib::common::MappingTable &mt_iox, |
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| 44 | |
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| 45 | size_t x_width, |
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| 46 | size_t y_width, |
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| 47 | size_t l_width, |
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| 48 | |
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| 49 | size_t int_memc_tgt_id, // local index |
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| 50 | size_t int_xicu_tgt_id, // local index |
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| 51 | size_t int_mdma_tgt_id, // local index |
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| 52 | size_t int_brom_tgt_id, // local index |
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| 53 | size_t int_iobx_tgt_id, // local index |
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| 54 | |
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| 55 | size_t int_proc_ini_id, // local index |
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| 56 | size_t int_mdma_ini_id, // local index |
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| 57 | size_t int_iobx_ini_id, // local index |
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| 58 | |
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| 59 | size_t ram_xram_tgt_id, // local index |
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| 60 | size_t ram_memc_ini_id, // local index |
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| 61 | size_t ram_iobx_ini_id, // local index |
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| 62 | |
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| 63 | bool is_io, // is IO cluster (IOB)? |
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| 64 | size_t iox_iobx_tgt_id, // local_index |
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| 65 | size_t iox_iobx_ini_id, // local index |
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| 66 | |
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| 67 | size_t memc_ways, |
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| 68 | size_t memc_sets, |
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| 69 | size_t l1_i_ways, |
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| 70 | size_t l1_i_sets, |
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| 71 | size_t l1_d_ways, |
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| 72 | size_t l1_d_sets, |
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| 73 | size_t xram_latency, |
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| 74 | size_t xcu_nb_inputs, |
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| 75 | |
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| 76 | bool distboot, |
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| 77 | |
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| 78 | const Loader &loader, |
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| 79 | |
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| 80 | uint32_t frozen_cycles, |
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| 81 | uint32_t debug_start_cycle, |
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| 82 | bool memc_debug_ok, |
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| 83 | bool proc_debug_ok, |
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| 84 | bool iob_debug_ok ) |
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| 85 | : soclib::caba::BaseModule(insname), |
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| 86 | p_clk("clk"), |
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| 87 | p_resetn("resetn") |
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| 88 | { |
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| 89 | assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); |
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| 90 | |
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| 91 | size_t cluster_id = (x_id<<4) + y_id; |
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| 92 | |
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| 93 | // Vectors of DSPIN ports for inter-cluster communications |
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| 94 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 95 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 96 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 97 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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| 98 | |
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| 99 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 100 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 101 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 102 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 103 | |
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| 104 | // VCI ports from IOB to IOX network (only in IO clusters) |
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| 105 | if ( is_io ) |
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| 106 | { |
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| 107 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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| 108 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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| 109 | } |
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| 110 | |
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| 111 | ///////////////////////////////////////////////////////////////////////////// |
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| 112 | // Hardware components |
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| 113 | ///////////////////////////////////////////////////////////////////////////// |
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| 114 | |
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| 115 | //////////// PROCS |
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| 116 | for (size_t p = 0; p < nb_procs; p++) |
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| 117 | { |
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| 118 | std::ostringstream s_proc; |
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| 119 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 120 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 121 | dspin_int_cmd_width, |
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| 122 | dspin_int_rsp_width, |
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| 123 | GdbServer<Mips32ElIss> >( |
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| 124 | s_proc.str().c_str(), |
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| 125 | cluster_id*nb_procs + p, // GLOBAL PROC_ID |
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| 126 | mt_int, // Mapping Table INT network |
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| 127 | IntTab(cluster_id,p), // SRCID |
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| 128 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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| 129 | 8, // ITLB ways |
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| 130 | 8, // ITLB sets |
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| 131 | 8, // DTLB ways |
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| 132 | 8, // DTLB sets |
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| 133 | l1_i_ways, l1_i_sets, 16, // ICACHE size |
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| 134 | l1_d_ways, l1_d_sets, 16, // DCACHE size |
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| 135 | 4, // WBUF nlines |
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| 136 | 4, // WBUF nwords |
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| 137 | x_width, |
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| 138 | y_width, |
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| 139 | frozen_cycles, // max frozen cycles |
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| 140 | debug_start_cycle, |
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| 141 | proc_debug_ok); |
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| 142 | |
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| 143 | // initialize physical address extension with cluster ID when using |
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| 144 | // distributed boot |
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| 145 | if (distboot) |
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| 146 | { |
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| 147 | proc[p]->set_dcache_paddr_ext_reset(cluster_id); |
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| 148 | proc[p]->set_icache_paddr_ext_reset(cluster_id); |
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| 149 | } |
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| 150 | } |
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| 151 | |
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| 152 | /////////// MEMC |
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| 153 | std::ostringstream s_memc; |
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| 154 | s_memc << "memc_" << x_id << "_" << y_id; |
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| 155 | memc = new VciMemCache<vci_param_int, |
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| 156 | vci_param_ext, |
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| 157 | dspin_int_rsp_width, |
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| 158 | dspin_int_cmd_width>( |
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| 159 | s_memc.str().c_str(), |
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| 160 | mt_int, // Mapping Table INT network |
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| 161 | mt_ram, // Mapping Table RAM network |
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| 162 | IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network |
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| 163 | IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network |
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| 164 | x_width, // number of bits for x coordinate |
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| 165 | y_width, // number of bits for y coordinate |
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| 166 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 167 | 3, // MAX NUMBER OF COPIES |
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| 168 | 4096, // HEAP SIZE |
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| 169 | 8, // TRANSACTION TABLE DEPTH |
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| 170 | 8, // UPDATE TABLE DEPTH |
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| 171 | 8, // INVALIDATE TABLE DEPTH |
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| 172 | debug_start_cycle, |
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| 173 | memc_debug_ok ); |
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| 174 | |
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| 175 | std::ostringstream s_wi_memc; |
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| 176 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 177 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 178 | dspin_ram_cmd_width, |
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| 179 | dspin_ram_rsp_width>( |
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| 180 | s_wi_memc.str().c_str(), |
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| 181 | x_width + y_width + l_width); |
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| 182 | |
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| 183 | /////////// XICU |
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| 184 | std::ostringstream s_xicu; |
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| 185 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 186 | xicu = new VciXicu<vci_param_int>( |
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| 187 | s_xicu.str().c_str(), |
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| 188 | mt_int, // mapping table INT network |
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| 189 | IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space |
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| 190 | xcu_nb_inputs, // number of timer IRQs |
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| 191 | xcu_nb_inputs, // number of hard IRQs |
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| 192 | xcu_nb_inputs, // number of soft IRQs |
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| 193 | 16); // number of output IRQs |
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| 194 | |
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| 195 | //////////// MDMA |
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| 196 | std::ostringstream s_mdma; |
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| 197 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 198 | mdma = new VciMultiDma<vci_param_int>( |
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| 199 | s_mdma.str().c_str(), |
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| 200 | mt_int, |
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| 201 | IntTab(cluster_id, nb_procs), // SRCID |
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| 202 | IntTab(cluster_id, int_mdma_tgt_id), // TGTID |
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| 203 | 64, // burst size |
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| 204 | nb_dmas); // number of IRQs |
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| 205 | |
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| 206 | /////////// DISTRIBUTED BOOT ROM |
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| 207 | std::ostringstream s_brom; |
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| 208 | s_brom << "brom_" << x_id << "_" << y_id; |
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| 209 | brom = new VciSimpleRom<vci_param_int>( |
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| 210 | s_brom.str().c_str(), |
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| 211 | IntTab(cluster_id, int_brom_tgt_id), |
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| 212 | mt_int, |
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| 213 | loader, |
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| 214 | x_width + y_width); // msb drop bits |
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| 215 | |
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| 216 | /////////// Direct LOCAL_XBAR(S) |
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| 217 | size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; |
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| 218 | size_t nb_direct_targets = is_io ? 5 : 4; |
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| 219 | |
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| 220 | std::ostringstream s_int_xbar_d; |
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| 221 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 222 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 223 | s_int_xbar_d.str().c_str(), |
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| 224 | mt_int, // mapping table |
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| 225 | cluster_id, // cluster id |
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| 226 | nb_direct_initiators, // number of local initiators |
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| 227 | nb_direct_targets, // number of local targets |
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| 228 | 0 ); // default target |
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| 229 | |
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| 230 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 231 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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| 232 | << x_id << "_" << y_id; |
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| 233 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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| 234 | dspin_int_cmd_width, |
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| 235 | dspin_int_rsp_width>( |
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| 236 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 237 | x_width + y_width + l_width); |
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| 238 | |
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| 239 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 240 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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| 241 | << x_id << "_" << y_id; |
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| 242 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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| 243 | dspin_int_cmd_width, |
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| 244 | dspin_int_rsp_width>( |
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| 245 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 246 | x_width + y_width + l_width); |
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| 247 | |
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| 248 | //////////// Coherence LOCAL_XBAR(S) |
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| 249 | std::ostringstream s_int_xbar_m2p_c; |
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| 250 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 251 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 252 | s_int_xbar_m2p_c.str().c_str(), |
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| 253 | mt_int, // mapping table |
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| 254 | x_id, y_id, // cluster coordinates |
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| 255 | x_width, y_width, l_width, // several dests |
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| 256 | 1, // number of local sources |
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| 257 | nb_procs, // number of local dests |
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| 258 | 2, 2, // fifo depths |
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| 259 | true, // pseudo CMD |
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| 260 | false, // no routing table |
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| 261 | true ); // broacast |
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| 262 | |
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| 263 | std::ostringstream s_int_xbar_p2m_c; |
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| 264 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 265 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 266 | s_int_xbar_p2m_c.str().c_str(), |
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| 267 | mt_int, // mapping table |
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| 268 | x_id, y_id, // cluster coordinates |
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| 269 | x_width, y_width, 0, // only one dest |
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| 270 | nb_procs, // number of local sources |
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| 271 | 1, // number of local dests |
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| 272 | 2, 2, // fifo depths |
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| 273 | false, // pseudo RSP |
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| 274 | false, // no routing table |
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| 275 | false ); // no broacast |
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| 276 | |
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| 277 | std::ostringstream s_int_xbar_clack_c; |
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| 278 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 279 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 280 | s_int_xbar_clack_c.str().c_str(), |
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| 281 | mt_int, // mapping table |
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| 282 | x_id, y_id, // cluster coordinates |
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| 283 | x_width, y_width, l_width, |
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| 284 | 1, // number of local sources |
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| 285 | nb_procs, // number of local targets |
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| 286 | 1, 1, // fifo depths |
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| 287 | true, // CMD |
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| 288 | false, // no routing table |
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| 289 | false); // broadcast |
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| 290 | |
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| 291 | ////////////// INT ROUTER(S) |
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| 292 | std::ostringstream s_int_router_cmd; |
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| 293 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 294 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 295 | s_int_router_cmd.str().c_str(), |
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| 296 | x_id,y_id, // coordinate in the mesh |
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| 297 | x_width, y_width, // x & y fields width |
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| 298 | 3, // nb virtual channels |
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| 299 | 4,4); // input & output fifo depths |
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| 300 | |
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| 301 | std::ostringstream s_int_router_rsp; |
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| 302 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 303 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 304 | s_int_router_rsp.str().c_str(), |
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| 305 | x_id,y_id, // router coordinates in mesh |
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| 306 | x_width, y_width, // x & y fields width |
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| 307 | 2, // nb virtual channels |
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| 308 | 4,4); // input & output fifo depths |
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| 309 | |
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| 310 | ////////////// XRAM |
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| 311 | std::ostringstream s_xram; |
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| 312 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 313 | xram = new VciSimpleRam<vci_param_ext>( |
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| 314 | s_xram.str().c_str(), |
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| 315 | IntTab(cluster_id, ram_xram_tgt_id), |
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| 316 | mt_ram, |
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| 317 | loader, |
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| 318 | xram_latency); |
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| 319 | |
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| 320 | std::ostringstream s_wt_xram; |
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| 321 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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| 322 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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| 323 | dspin_ram_cmd_width, |
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| 324 | dspin_ram_rsp_width>( |
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| 325 | s_wt_xram.str().c_str(), |
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| 326 | x_width + y_width + l_width); |
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| 327 | |
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| 328 | ///////////// RAM ROUTER(S) |
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| 329 | std::ostringstream s_ram_router_cmd; |
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| 330 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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| 331 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
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| 332 | s_ram_router_cmd.str().c_str(), |
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| 333 | x_id, y_id, // router coordinates in mesh |
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| 334 | x_width, // x field width in first flit |
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| 335 | y_width, // y field width in first flit |
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| 336 | 4, 4); // input & output fifo depths |
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| 337 | |
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| 338 | std::ostringstream s_ram_router_rsp; |
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| 339 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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| 340 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
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| 341 | s_ram_router_rsp.str().c_str(), |
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| 342 | x_id, y_id, // coordinates in mesh |
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| 343 | x_width, // x field width in first flit |
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| 344 | y_width, // y field width in first flit |
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| 345 | 4, 4); // input & output fifo depths |
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| 346 | |
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| 347 | |
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| 348 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 349 | if ( is_io ) |
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| 350 | { |
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| 351 | /////////// IO_BRIDGE |
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| 352 | std::ostringstream s_iob; |
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| 353 | s_iob << "iob_" << x_id << "_" << y_id; |
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| 354 | iob = new VciIoBridge<vci_param_int, |
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| 355 | vci_param_ext>( |
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| 356 | s_iob.str().c_str(), |
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| 357 | mt_ram, // EXT network maptab |
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| 358 | mt_int, // INT network maptab |
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| 359 | mt_iox, // IOX network maptab |
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| 360 | IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID |
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| 361 | IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID |
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| 362 | IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID |
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| 363 | IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID |
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| 364 | 16, // cache line words |
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| 365 | 8, // IOTLB ways |
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| 366 | 8, // IOTLB sets |
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| 367 | debug_start_cycle, |
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| 368 | iob_debug_ok ); |
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| 369 | |
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| 370 | std::ostringstream s_iob_ram_wi; |
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| 371 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
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| 372 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 373 | dspin_ram_cmd_width, |
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| 374 | dspin_ram_rsp_width>( |
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| 375 | s_iob_ram_wi.str().c_str(), |
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| 376 | vci_param_int::S); |
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| 377 | |
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| 378 | std::ostringstream s_ram_xbar_cmd; |
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| 379 | s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; |
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| 380 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
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| 381 | s_ram_xbar_cmd.str().c_str(), // name |
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| 382 | mt_ram, // mapping table |
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| 383 | x_id, y_id, // x, y |
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| 384 | x_width, y_width, l_width, // x_width, y_width, l_width |
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| 385 | 2, 0, // local inputs, local outputs |
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| 386 | 2, 2, // in fifo, out fifo depths |
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| 387 | true, // is cmd ? |
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| 388 | false, // use routing table ? |
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| 389 | false); // support broadcast ? |
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| 390 | |
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| 391 | std::ostringstream s_ram_xbar_rsp; |
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| 392 | s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; |
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| 393 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
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| 394 | s_ram_xbar_rsp.str().c_str(), // name |
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| 395 | mt_ram, // mapping table |
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| 396 | x_id, y_id, // x, y |
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| 397 | x_width, y_width, l_width, // x_width, y_width, l_width |
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| 398 | 0, 2, // local inputs, local outputs |
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| 399 | 2, 2, // in fifo, out fifo depths |
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| 400 | false, // is cmd ? |
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| 401 | true, // use routing table ? |
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| 402 | false); // support broadcast ? |
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| 403 | } // end if IO |
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| 404 | |
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| 405 | //////////////////////////////////// |
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| 406 | // Connections are defined here |
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| 407 | //////////////////////////////////// |
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| 408 | |
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| 409 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
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| 410 | // : local srcid[memc] = nb_procs |
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| 411 | |
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| 412 | //////////////////////// internal CMD & RSP routers |
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| 413 | int_router_cmd->p_clk (this->p_clk); |
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| 414 | int_router_cmd->p_resetn (this->p_resetn); |
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| 415 | int_router_rsp->p_clk (this->p_clk); |
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| 416 | int_router_rsp->p_resetn (this->p_resetn); |
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| 417 | |
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| 418 | for (int i = 0; i < 4; i++) |
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| 419 | { |
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| 420 | for(int k = 0; k < 3; k++) |
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| 421 | { |
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| 422 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
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| 423 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
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| 424 | } |
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| 425 | |
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| 426 | for(int k = 0; k < 2; k++) |
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| 427 | { |
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| 428 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
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| 429 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
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| 430 | } |
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| 431 | } |
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| 432 | |
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| 433 | // local ports |
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| 434 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
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| 435 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
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| 436 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
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| 437 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
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| 438 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
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| 439 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
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| 440 | |
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| 441 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
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| 442 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
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| 443 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
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| 444 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
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| 445 | |
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| 446 | ///////////////////// CMD DSPIN local crossbar direct |
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| 447 | int_xbar_d->p_clk (this->p_clk); |
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| 448 | int_xbar_d->p_resetn (this->p_resetn); |
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| 449 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
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| 450 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
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| 451 | |
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| 452 | int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); |
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| 453 | int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); |
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| 454 | int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); |
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| 455 | int_xbar_d->p_to_target[int_brom_tgt_id] (signal_int_vci_tgt_brom); |
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| 456 | int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); |
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| 457 | for (size_t p = 0; p < nb_procs; p++) |
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| 458 | int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); |
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| 459 | |
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| 460 | if ( is_io ) |
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| 461 | { |
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| 462 | int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); |
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| 463 | int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); |
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| 464 | } |
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| 465 | |
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| 466 | int_wi_gate_d->p_clk (this->p_clk); |
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| 467 | int_wi_gate_d->p_resetn (this->p_resetn); |
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| 468 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
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| 469 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
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| 470 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
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| 471 | |
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| 472 | int_wt_gate_d->p_clk (this->p_clk); |
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| 473 | int_wt_gate_d->p_resetn (this->p_resetn); |
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| 474 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
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| 475 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
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| 476 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
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| 477 | |
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| 478 | ////////////////////// M2P DSPIN local crossbar coherence |
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| 479 | int_xbar_m2p_c->p_clk (this->p_clk); |
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| 480 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
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| 481 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
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| 482 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
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| 483 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
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| 484 | for (size_t p = 0; p < nb_procs; p++) |
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| 485 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
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| 486 | |
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| 487 | ////////////////////////// P2M DSPIN local crossbar coherence |
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| 488 | int_xbar_p2m_c->p_clk (this->p_clk); |
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| 489 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
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| 490 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
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| 491 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
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| 492 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
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| 493 | for (size_t p = 0; p < nb_procs; p++) |
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| 494 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
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| 495 | |
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| 496 | ////////////////////// CLACK DSPIN local crossbar coherence |
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| 497 | int_xbar_clack_c->p_clk (this->p_clk); |
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| 498 | int_xbar_clack_c->p_resetn (this->p_resetn); |
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| 499 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
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| 500 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
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| 501 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
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| 502 | for (size_t p = 0; p < nb_procs; p++) |
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| 503 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
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| 504 | |
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| 505 | //////////////////////////////////// Processors |
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| 506 | for (size_t p = 0; p < nb_procs; p++) |
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| 507 | { |
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| 508 | proc[p]->p_clk (this->p_clk); |
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| 509 | proc[p]->p_resetn (this->p_resetn); |
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| 510 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
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| 511 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
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| 512 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
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| 513 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
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| 514 | |
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| 515 | for ( size_t j = 0 ; j < 6 ; j++) |
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| 516 | { |
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| 517 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); |
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| 518 | else proc[p]->p_irq[j] (signal_false); |
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| 519 | } |
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| 520 | } |
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| 521 | |
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| 522 | ///////////////////////////////////// XICU |
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| 523 | xicu->p_clk (this->p_clk); |
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| 524 | xicu->p_resetn (this->p_resetn); |
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| 525 | xicu->p_vci (signal_int_vci_tgt_xicu); |
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| 526 | for ( size_t i=0 ; i < 16 ; i++) |
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| 527 | { |
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| 528 | xicu->p_irq[i] (signal_proc_it[i]); |
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| 529 | } |
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| 530 | for ( size_t i=0 ; i < xcu_nb_inputs ; i++) |
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| 531 | { |
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| 532 | if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); |
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| 533 | else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); |
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| 534 | else xicu->p_hwi[i] (signal_false); |
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| 535 | } |
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| 536 | |
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| 537 | ///////////////////////////////////// MEMC |
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| 538 | memc->p_clk (this->p_clk); |
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| 539 | memc->p_resetn (this->p_resetn); |
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| 540 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
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| 541 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
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| 542 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
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| 543 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
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| 544 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
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| 545 | memc->p_irq (signal_irq_memc); |
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| 546 | |
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| 547 | // wrapper to RAM network |
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| 548 | memc_ram_wi->p_clk (this->p_clk); |
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| 549 | memc_ram_wi->p_resetn (this->p_resetn); |
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| 550 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
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| 551 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
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| 552 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
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| 553 | |
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| 554 | //////////////////////////////////// XRAM |
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| 555 | xram->p_clk (this->p_clk); |
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| 556 | xram->p_resetn (this->p_resetn); |
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| 557 | xram->p_vci (signal_ram_vci_tgt_xram); |
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| 558 | |
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| 559 | // wrapper to RAM network |
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| 560 | xram_ram_wt->p_clk (this->p_clk); |
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| 561 | xram_ram_wt->p_resetn (this->p_resetn); |
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| 562 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
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| 563 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
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| 564 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
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| 565 | |
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| 566 | /////////////////////////////////// MDMA |
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| 567 | mdma->p_clk (this->p_clk); |
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| 568 | mdma->p_resetn (this->p_resetn); |
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| 569 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
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| 570 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
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| 571 | for (size_t i=0 ; i<nb_dmas ; i++) |
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| 572 | mdma->p_irq[i] (signal_irq_mdma[i]); |
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| 573 | |
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| 574 | /////////////////////////////////// BROM |
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| 575 | brom->p_clk (this->p_clk); |
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| 576 | brom->p_resetn (this->p_resetn); |
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| 577 | brom->p_vci (signal_int_vci_tgt_brom); |
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| 578 | |
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| 579 | //////////////////////////// RAM network CMD & RSP routers |
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| 580 | ram_router_cmd->p_clk (this->p_clk); |
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| 581 | ram_router_cmd->p_resetn (this->p_resetn); |
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| 582 | ram_router_rsp->p_clk (this->p_clk); |
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| 583 | ram_router_rsp->p_resetn (this->p_resetn); |
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| 584 | for( size_t n=0 ; n<4 ; n++) |
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| 585 | { |
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| 586 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
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| 587 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
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| 588 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
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| 589 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
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| 590 | } |
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| 591 | |
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| 592 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
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| 593 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
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| 594 | |
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| 595 | if ( is_io ) |
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| 596 | { |
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| 597 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); |
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| 598 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); |
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| 599 | } |
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| 600 | else |
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| 601 | { |
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| 602 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
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| 603 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
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| 604 | } |
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| 605 | |
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| 606 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
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| 607 | if ( is_io ) |
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| 608 | { |
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| 609 | // IO bridge |
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| 610 | iob->p_clk (this->p_clk); |
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| 611 | iob->p_resetn (this->p_resetn); |
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| 612 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
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| 613 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
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| 614 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
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| 615 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
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| 616 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
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| 617 | |
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| 618 | // initiator wrapper to RAM network |
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| 619 | iob_ram_wi->p_clk (this->p_clk); |
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| 620 | iob_ram_wi->p_resetn (this->p_resetn); |
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| 621 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); |
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| 622 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); |
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| 623 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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| 624 | |
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| 625 | // crossbar between MEMC and IOB to RAM network |
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| 626 | ram_xbar_cmd->p_clk (this->p_clk); |
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| 627 | ram_xbar_cmd->p_resetn (this->p_resetn); |
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| 628 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); |
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| 629 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); |
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| 630 | ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); |
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| 631 | ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); |
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| 632 | |
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| 633 | ram_xbar_rsp->p_clk (this->p_clk); |
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| 634 | ram_xbar_rsp->p_resetn (this->p_resetn); |
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| 635 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); |
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| 636 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); |
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| 637 | ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); |
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| 638 | ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); |
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| 639 | } |
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| 640 | |
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| 641 | SC_METHOD(init); |
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| 642 | } // end constructor |
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| 643 | |
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| 644 | tmpl(void)::init() |
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| 645 | { |
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| 646 | signal_ram_dspin_cmd_false.write = false; |
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| 647 | signal_ram_dspin_cmd_false.read = true; |
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| 648 | signal_ram_dspin_rsp_false.write = false; |
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| 649 | signal_ram_dspin_rsp_false.read = true; |
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| 650 | } // end init |
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| 651 | |
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| 652 | }} |
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| 653 | |
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| 654 | |
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| 655 | // Local Variables: |
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| 656 | // tab-width: 4 |
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| 657 | // c-basic-offset: 4 |
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| 658 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 659 | // indent-tabs-mode: nil |
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| 660 | // End: |
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| 661 | |
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| 662 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 663 | |
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