[839] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * File : vci_cc_vcache_wrapper.h |
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| 4 | * Copyright (c) UPMC, Lip6, SoC |
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| 5 | * Authors : Alain GREINER, Yang GAO |
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| 6 | * Date : 27/11/2011 |
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| 7 | * |
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| 8 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 9 | * |
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| 10 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 11 | * |
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| 12 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 13 | * under the terms of the GNU Lesser General Public License as published |
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| 14 | * by the Free Software Foundation; version 2.1 of the License. |
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| 15 | * |
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| 16 | * SoCLib is distributed in the hope that it will be useful, but |
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 19 | * Lesser General Public License for more details. |
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| 20 | * |
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| 21 | * You should have received a copy of the GNU Lesser General Public |
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| 22 | * License along with SoCLib; if not, write to the Free Software |
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| 23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 24 | * 02110-1301 USA |
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| 25 | * |
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| 26 | * SOCLIB_LGPL_HEADER_END |
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| 27 | * |
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| 28 | * Maintainers: cesar.fuguet-tortolero@lip6.fr |
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| 29 | * alexandre.joannou@lip6.fr |
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| 30 | */ |
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| 31 | |
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| 32 | #ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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| 33 | #define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H |
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| 34 | |
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| 35 | #include <inttypes.h> |
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| 36 | #include <systemc> |
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| 37 | #include "caba_base_module.h" |
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| 38 | #include "multi_write_buffer.h" |
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| 39 | #include "generic_fifo.h" |
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| 40 | #include "generic_tlb.h" |
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| 41 | #include "generic_cache.h" |
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| 42 | #include "vci_initiator.h" |
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| 43 | #include "dspin_interface.h" |
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| 44 | #include "dspin_dhccp_param.h" |
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| 45 | #include "mapping_table.h" |
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| 46 | #include "static_assert.h" |
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| 47 | #include "iss2.h" |
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| 48 | |
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| 49 | #define LLSC_TIMEOUT 10000 |
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| 50 | |
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| 51 | namespace soclib { |
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| 52 | namespace caba { |
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| 53 | |
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| 54 | using namespace sc_core; |
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| 55 | |
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| 56 | //////////////////////////////////////////// |
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[840] | 57 | template<typename vci_param, |
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[839] | 58 | size_t dspin_in_width, |
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| 59 | size_t dspin_out_width, |
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| 60 | typename iss_t> |
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| 61 | class VciCcVCacheWrapper |
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| 62 | //////////////////////////////////////////// |
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| 63 | : public soclib::caba::BaseModule |
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| 64 | { |
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| 65 | |
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[905] | 66 | typedef typename vci_param::fast_addr_t paddr_t; |
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| 67 | typedef typename vci_param::trdid_t trdid_t; |
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[839] | 68 | |
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[840] | 69 | enum icache_fsm_state_e |
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[839] | 70 | { |
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| 71 | ICACHE_IDLE, |
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| 72 | // handling XTN processor requests |
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| 73 | ICACHE_XTN_TLB_FLUSH, |
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| 74 | ICACHE_XTN_CACHE_FLUSH, |
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| 75 | ICACHE_XTN_CACHE_FLUSH_GO, |
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| 76 | ICACHE_XTN_TLB_INVAL, |
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| 77 | ICACHE_XTN_CACHE_INVAL_VA, |
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| 78 | ICACHE_XTN_CACHE_INVAL_PA, |
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| 79 | ICACHE_XTN_CACHE_INVAL_GO, |
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| 80 | // handling tlb miss |
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| 81 | ICACHE_TLB_WAIT, |
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| 82 | // handling cache miss |
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| 83 | ICACHE_MISS_SELECT, |
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| 84 | ICACHE_MISS_CLEAN, |
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| 85 | ICACHE_MISS_WAIT, |
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| 86 | ICACHE_MISS_DATA_UPDT, |
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| 87 | ICACHE_MISS_DIR_UPDT, |
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| 88 | // handling unc read |
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| 89 | ICACHE_UNC_WAIT, |
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| 90 | // handling coherence requests |
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| 91 | ICACHE_CC_CHECK, |
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| 92 | ICACHE_CC_UPDT, |
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| 93 | ICACHE_CC_INVAL, |
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| 94 | }; |
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| 95 | |
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[840] | 96 | enum dcache_fsm_state_e |
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[839] | 97 | { |
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| 98 | DCACHE_IDLE, |
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| 99 | // handling itlb & dtlb miss |
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| 100 | DCACHE_TLB_MISS, |
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| 101 | DCACHE_TLB_PTE1_GET, |
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| 102 | DCACHE_TLB_PTE1_SELECT, |
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| 103 | DCACHE_TLB_PTE1_UPDT, |
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| 104 | DCACHE_TLB_PTE2_GET, |
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| 105 | DCACHE_TLB_PTE2_SELECT, |
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| 106 | DCACHE_TLB_PTE2_UPDT, |
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| 107 | DCACHE_TLB_LR_UPDT, |
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| 108 | DCACHE_TLB_LR_WAIT, |
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| 109 | DCACHE_TLB_RETURN, |
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[840] | 110 | // handling processor XTN requests |
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[839] | 111 | DCACHE_XTN_SWITCH, |
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| 112 | DCACHE_XTN_SYNC, |
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| 113 | DCACHE_XTN_IC_INVAL_VA, |
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| 114 | DCACHE_XTN_IC_FLUSH, |
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| 115 | DCACHE_XTN_IC_INVAL_PA, |
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| 116 | DCACHE_XTN_IC_PADDR_EXT, |
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| 117 | DCACHE_XTN_IT_INVAL, |
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| 118 | DCACHE_XTN_DC_FLUSH, |
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| 119 | DCACHE_XTN_DC_FLUSH_GO, |
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| 120 | DCACHE_XTN_DC_INVAL_VA, |
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| 121 | DCACHE_XTN_DC_INVAL_PA, |
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| 122 | DCACHE_XTN_DC_INVAL_END, |
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| 123 | DCACHE_XTN_DC_INVAL_GO, |
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| 124 | DCACHE_XTN_DT_INVAL, |
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[919] | 125 | DCACHE_XTN_CC_TEST, |
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[839] | 126 | //handling dirty bit update |
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| 127 | DCACHE_DIRTY_GET_PTE, |
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| 128 | DCACHE_DIRTY_WAIT, |
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[840] | 129 | // handling processor miss requests |
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[839] | 130 | DCACHE_MISS_SELECT, |
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| 131 | DCACHE_MISS_CLEAN, |
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| 132 | DCACHE_MISS_WAIT, |
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| 133 | DCACHE_MISS_DATA_UPDT, |
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| 134 | DCACHE_MISS_DIR_UPDT, |
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| 135 | // handling processor unc, ll and sc requests |
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| 136 | DCACHE_UNC_WAIT, |
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| 137 | DCACHE_LL_WAIT, |
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| 138 | DCACHE_SC_WAIT, |
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| 139 | // handling coherence requests |
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| 140 | DCACHE_CC_CHECK, |
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| 141 | DCACHE_CC_UPDT, |
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| 142 | DCACHE_CC_INVAL, |
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| 143 | // handling TLB inval (after a coherence or XTN request) |
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| 144 | DCACHE_INVAL_TLB_SCAN, |
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| 145 | }; |
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| 146 | |
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[840] | 147 | enum cmd_fsm_state_e |
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[839] | 148 | { |
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| 149 | CMD_IDLE, |
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| 150 | CMD_INS_MISS, |
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| 151 | CMD_INS_UNC, |
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| 152 | CMD_DATA_MISS, |
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| 153 | CMD_DATA_UNC_READ, |
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| 154 | CMD_DATA_UNC_WRITE, |
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| 155 | CMD_DATA_WRITE, |
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| 156 | CMD_DATA_LL, |
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| 157 | CMD_DATA_SC, |
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| 158 | CMD_DATA_CAS, |
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| 159 | }; |
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| 160 | |
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[840] | 161 | enum rsp_fsm_state_e |
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[839] | 162 | { |
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| 163 | RSP_IDLE, |
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| 164 | RSP_INS_MISS, |
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| 165 | RSP_INS_UNC, |
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| 166 | RSP_DATA_MISS, |
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| 167 | RSP_DATA_UNC, |
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| 168 | RSP_DATA_LL, |
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| 169 | RSP_DATA_WRITE, |
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| 170 | }; |
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| 171 | |
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[840] | 172 | enum cc_receive_fsm_state_e |
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[839] | 173 | { |
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| 174 | CC_RECEIVE_IDLE, |
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| 175 | CC_RECEIVE_BRDCAST_HEADER, |
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| 176 | CC_RECEIVE_BRDCAST_NLINE, |
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| 177 | CC_RECEIVE_INS_INVAL_HEADER, |
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| 178 | CC_RECEIVE_INS_INVAL_NLINE, |
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| 179 | CC_RECEIVE_INS_UPDT_HEADER, |
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| 180 | CC_RECEIVE_INS_UPDT_NLINE, |
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| 181 | CC_RECEIVE_DATA_INVAL_HEADER, |
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| 182 | CC_RECEIVE_DATA_INVAL_NLINE, |
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| 183 | CC_RECEIVE_DATA_UPDT_HEADER, |
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| 184 | CC_RECEIVE_DATA_UPDT_NLINE, |
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| 185 | CC_RECEIVE_INS_UPDT_DATA, |
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| 186 | CC_RECEIVE_DATA_UPDT_DATA, |
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[919] | 187 | CC_RECEIVE_TEST_HEADER, |
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| 188 | CC_RECEIVE_TEST_SIGNATURE, |
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[839] | 189 | }; |
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| 190 | |
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[840] | 191 | enum cc_send_fsm_state_e |
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[839] | 192 | { |
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| 193 | CC_SEND_IDLE, |
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| 194 | CC_SEND_CLEANUP_1, |
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| 195 | CC_SEND_CLEANUP_2, |
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| 196 | CC_SEND_MULTI_ACK, |
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[919] | 197 | CC_SEND_TEST_HEADER, |
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| 198 | CC_SEND_TEST_SIGNATURE, |
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[839] | 199 | }; |
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| 200 | |
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[919] | 201 | enum cc_test_fsm_state_e |
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| 202 | { |
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| 203 | CC_TEST_IDLE, |
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| 204 | CC_TEST_P2M_REQ, |
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| 205 | CC_TEST_P2M_WAIT, |
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| 206 | CC_TEST_ACK_WAIT, |
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| 207 | }; |
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| 208 | |
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[839] | 209 | /* transaction type, pktid field */ |
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| 210 | enum transaction_type_e |
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| 211 | { |
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| 212 | // b3 unused |
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| 213 | // b2 READ / NOT READ |
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| 214 | // if READ |
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| 215 | // b1 DATA / INS |
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| 216 | // b0 UNC / MISS |
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| 217 | // else |
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| 218 | // b1 accÚs table llsc type SW / other |
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| 219 | // b2 WRITE/CAS/LL/SC |
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[840] | 220 | TYPE_DATA_UNC = 0x0, |
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| 221 | TYPE_READ_DATA_MISS = 0x1, |
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| 222 | TYPE_READ_INS_UNC = 0x2, |
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| 223 | TYPE_READ_INS_MISS = 0x3, |
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| 224 | TYPE_WRITE = 0x4, |
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| 225 | TYPE_CAS = 0x5, |
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| 226 | TYPE_LL = 0x6, |
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| 227 | TYPE_SC = 0x7 |
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[839] | 228 | }; |
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| 229 | |
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| 230 | /* SC return values */ |
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| 231 | enum sc_status_type_e |
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| 232 | { |
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[840] | 233 | SC_SUCCESS = 0x00000000, |
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| 234 | SC_FAIL = 0x00000001 |
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[839] | 235 | }; |
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| 236 | |
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| 237 | // cc_send_type |
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[840] | 238 | typedef enum |
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[839] | 239 | { |
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| 240 | CC_TYPE_CLEANUP, |
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| 241 | CC_TYPE_MULTI_ACK, |
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| 242 | } cc_send_t; |
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| 243 | |
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| 244 | // cc_receive_type |
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[840] | 245 | typedef enum |
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[839] | 246 | { |
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| 247 | CC_TYPE_CLACK, |
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| 248 | CC_TYPE_BRDCAST, |
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| 249 | CC_TYPE_INVAL, |
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| 250 | CC_TYPE_UPDT, |
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| 251 | } cc_receive_t; |
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| 252 | |
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| 253 | // TLB Mode : ITLB / DTLB / ICACHE / DCACHE |
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[840] | 254 | enum |
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[839] | 255 | { |
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| 256 | INS_TLB_MASK = 0x8, |
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| 257 | DATA_TLB_MASK = 0x4, |
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| 258 | INS_CACHE_MASK = 0x2, |
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| 259 | DATA_CACHE_MASK = 0x1, |
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| 260 | }; |
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| 261 | |
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| 262 | // Error Type |
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| 263 | enum mmu_error_type_e |
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| 264 | { |
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| 265 | MMU_NONE = 0x0000, // None |
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[840] | 266 | MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 |
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| 267 | MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 |
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[839] | 268 | MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode |
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| 269 | MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page |
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| 270 | MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write & undefined external access |
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| 271 | MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write & Bus Error accessing PT1 |
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| 272 | MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 |
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| 273 | MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access |
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[840] | 274 | MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 |
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| 275 | MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 |
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[839] | 276 | MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode |
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| 277 | MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page |
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[840] | 278 | MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access |
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[839] | 279 | MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 |
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| 280 | MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 |
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| 281 | MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access |
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[845] | 282 | MMU_READ_DATA_TIMEOUT = 0x1200, // Read & Watchdog timeout |
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[839] | 283 | }; |
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| 284 | |
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| 285 | // miss types for data cache |
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| 286 | enum dcache_miss_type_e |
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| 287 | { |
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| 288 | PTE1_MISS, |
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| 289 | PTE2_MISS, |
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| 290 | PROC_MISS, |
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| 291 | }; |
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| 292 | |
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[846] | 293 | // this enumeration type extends the ExternalAcessTypes defined in iss2.h |
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[919] | 294 | // XTN_CC_TEST: |
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| 295 | // When XTN_WRITE: triggers the CC_TEST. The target MEMC is in dreq.wdata |
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| 296 | // When XTN_READ: returns the CC_TEST result |
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[846] | 297 | enum xtn_cop2_extension_e { |
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| 298 | XTN_WDT_MAX = 26, // Read & Write the watchdog timer threshold |
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[919] | 299 | XTN_CC_TEST = 27, // Trigger coherence network test |
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[846] | 300 | }; |
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[839] | 301 | |
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| 302 | public: |
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| 303 | sc_in<bool> p_clk; |
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| 304 | sc_in<bool> p_resetn; |
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| 305 | sc_in<bool> p_irq[iss_t::n_irq]; |
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| 306 | soclib::caba::VciInitiator<vci_param> p_vci; |
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| 307 | soclib::caba::DspinInput<dspin_in_width> p_dspin_m2p; |
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| 308 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m; |
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| 309 | soclib::caba::DspinInput<dspin_in_width> p_dspin_clack; |
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| 310 | |
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| 311 | private: |
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| 312 | |
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| 313 | // STRUCTURAL PARAMETERS |
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| 314 | soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table; |
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| 315 | |
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[840] | 316 | const size_t m_srcid; |
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| 317 | const size_t m_cc_global_id; |
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| 318 | const size_t m_nline_width; |
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| 319 | const size_t m_itlb_ways; |
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| 320 | const size_t m_itlb_sets; |
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| 321 | const size_t m_dtlb_ways; |
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| 322 | const size_t m_dtlb_sets; |
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| 323 | const size_t m_icache_ways; |
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| 324 | const size_t m_icache_sets; |
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| 325 | const paddr_t m_icache_yzmask; |
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| 326 | const size_t m_icache_words; |
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| 327 | const size_t m_dcache_ways; |
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| 328 | const size_t m_dcache_sets; |
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| 329 | const paddr_t m_dcache_yzmask; |
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| 330 | const size_t m_dcache_words; |
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| 331 | const size_t m_x_width; |
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| 332 | const size_t m_y_width; |
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| 333 | const size_t m_proc_id; |
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| 334 | const uint32_t m_max_frozen_cycles; |
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| 335 | const size_t m_paddr_nbits; |
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| 336 | uint32_t m_debug_start_cycle; |
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| 337 | bool m_debug_ok; |
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[839] | 338 | |
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[840] | 339 | uint32_t m_dcache_paddr_ext_reset; |
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| 340 | uint32_t m_icache_paddr_ext_reset; |
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[839] | 341 | |
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| 342 | //////////////////////////////////////// |
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| 343 | // Communication with processor ISS |
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| 344 | //////////////////////////////////////// |
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| 345 | typename iss_t::InstructionRequest m_ireq; |
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| 346 | typename iss_t::InstructionResponse m_irsp; |
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| 347 | typename iss_t::DataRequest m_dreq; |
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| 348 | typename iss_t::DataResponse m_drsp; |
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| 349 | |
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| 350 | ///////////////////////////////////////////// |
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[840] | 351 | // debug variables |
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[839] | 352 | ///////////////////////////////////////////// |
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| 353 | bool m_debug_previous_i_hit; |
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| 354 | bool m_debug_previous_d_hit; |
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| 355 | bool m_debug_icache_fsm; |
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| 356 | bool m_debug_dcache_fsm; |
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| 357 | bool m_debug_cmd_fsm; |
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| 358 | uint32_t m_previous_status; |
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| 359 | |
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| 360 | |
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| 361 | /////////////////////////////// |
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| 362 | // Software visible REGISTERS |
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| 363 | /////////////////////////////// |
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[840] | 364 | sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register |
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| 365 | sc_signal<uint32_t> r_mmu_mode; // mmu mode register |
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| 366 | sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low |
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| 367 | sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight |
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| 368 | sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address |
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| 369 | sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address |
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[839] | 370 | sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type |
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| 371 | sc_signal<uint32_t> r_mmu_detr; // mmu data error type |
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[840] | 372 | uint32_t r_mmu_params; // read-only |
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| 373 | uint32_t r_mmu_release; // read_only |
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[839] | 374 | |
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| 375 | |
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| 376 | ////////////////////////////// |
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| 377 | // ICACHE FSM REGISTERS |
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| 378 | ////////////////////////////// |
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| 379 | sc_signal<int> r_icache_fsm; // state register |
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| 380 | sc_signal<int> r_icache_fsm_save; // return state for coherence op |
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[840] | 381 | sc_signal<paddr_t> r_icache_vci_paddr; // physical address |
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[839] | 382 | sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor |
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| 383 | |
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| 384 | // icache miss handling |
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[840] | 385 | sc_signal<size_t> r_icache_miss_way; // selected way for cache update |
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| 386 | sc_signal<size_t> r_icache_miss_set; // selected set for cache update |
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| 387 | sc_signal<size_t> r_icache_miss_word; // word index ( cache update) |
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[839] | 388 | sc_signal<bool> r_icache_miss_inval; // coherence request matching a miss |
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| 389 | sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge |
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| 390 | |
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| 391 | // coherence request handling |
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[840] | 392 | sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval |
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| 393 | sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval |
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| 394 | sc_signal<size_t> r_icache_cc_word; // word counter for cc update |
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[839] | 395 | sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing |
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| 396 | |
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| 397 | // coherence clack handling |
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| 398 | sc_signal<bool> r_icache_clack_req; // clack request |
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[840] | 399 | sc_signal<size_t> r_icache_clack_way; // clack way |
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| 400 | sc_signal<size_t> r_icache_clack_set; // clack set |
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[839] | 401 | |
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| 402 | // icache flush handling |
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[840] | 403 | sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush |
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[839] | 404 | |
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| 405 | // communication between ICACHE FSM and VCI_CMD FSM |
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| 406 | sc_signal<bool> r_icache_miss_req; // cached read miss |
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| 407 | sc_signal<bool> r_icache_unc_req; // uncached read miss |
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| 408 | |
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| 409 | // communication between ICACHE FSM and DCACHE FSM |
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[840] | 410 | sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache) |
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[839] | 411 | sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error |
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| 412 | |
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| 413 | // Filp-Flop in ICACHE FSM for saving the cleanup victim request |
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[840] | 414 | sc_signal<bool> r_icache_cleanup_victim_req; |
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[839] | 415 | sc_signal<paddr_t> r_icache_cleanup_victim_nline; |
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| 416 | |
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| 417 | // communication between ICACHE FSM and CC_SEND FSM |
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| 418 | sc_signal<bool> r_icache_cc_send_req; // ICACHE cc_send request |
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| 419 | sc_signal<int> r_icache_cc_send_type; // ICACHE cc_send request type |
---|
| 420 | sc_signal<paddr_t> r_icache_cc_send_nline; // ICACHE cc_send nline |
---|
| 421 | sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way |
---|
| 422 | sc_signal<size_t> r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index |
---|
| 423 | |
---|
| 424 | // Physical address extension for data access |
---|
| 425 | sc_signal<uint32_t> r_icache_paddr_ext; // CP2 register (if vci_address > 32) |
---|
| 426 | |
---|
| 427 | /////////////////////////////// |
---|
| 428 | // DCACHE FSM REGISTERS |
---|
| 429 | /////////////////////////////// |
---|
| 430 | sc_signal<int> r_dcache_fsm; // state register |
---|
| 431 | sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence op |
---|
| 432 | sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op |
---|
| 433 | // registers written in P0 stage (used in P1 stage) |
---|
| 434 | sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage |
---|
| 435 | sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage |
---|
| 436 | sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) |
---|
| 437 | sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) |
---|
| 438 | sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) |
---|
| 439 | sc_signal<paddr_t> r_dcache_save_paddr; // physical address |
---|
[840] | 440 | sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) |
---|
| 441 | sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) |
---|
| 442 | sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache) |
---|
[839] | 443 | // registers used by the Dirty bit sub-fsm |
---|
| 444 | sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address |
---|
[840] | 445 | sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache |
---|
| 446 | sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache |
---|
[839] | 447 | |
---|
| 448 | // communication between DCACHE FSM and VCI_CMD FSM |
---|
[845] | 449 | sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command |
---|
| 450 | sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command |
---|
[839] | 451 | sc_signal<bool> r_dcache_vci_miss_req; // read miss request |
---|
| 452 | sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) |
---|
| 453 | sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable byte enable |
---|
| 454 | sc_signal<uint32_t> r_dcache_vci_unc_write; // uncacheable data write request |
---|
| 455 | sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS |
---|
| 456 | sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS |
---|
| 457 | sc_signal<uint32_t> r_dcache_vci_cas_new; // new data value for a CAS |
---|
| 458 | sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL |
---|
| 459 | sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC |
---|
| 460 | sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) |
---|
[888] | 461 | sc_signal<trdid_t> r_dcache_vci_wdt_trdid; // dcache WDT trdid (for debug) |
---|
[839] | 462 | |
---|
| 463 | // register used for XTN inval |
---|
[845] | 464 | sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) |
---|
| 465 | sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) |
---|
[839] | 466 | |
---|
| 467 | // handling dcache miss |
---|
[845] | 468 | sc_signal<int> r_dcache_miss_type; // depending on the requester |
---|
| 469 | sc_signal<size_t> r_dcache_miss_word; // word index for cache update |
---|
| 470 | sc_signal<size_t> r_dcache_miss_way; // selected way for cache update |
---|
| 471 | sc_signal<size_t> r_dcache_miss_set; // selected set for cache update |
---|
[839] | 472 | sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss |
---|
| 473 | sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge |
---|
| 474 | |
---|
[888] | 475 | // Watchdog timer (WDT) for timeout exception (black-hole detection) |
---|
| 476 | sc_signal<uint32_t> r_dcache_wdt_max; // wdt triggering value |
---|
| 477 | sc_signal<uint32_t> r_dcache_wdt; // wdt counter |
---|
[853] | 478 | sc_signal<trdid_t> r_dcache_wdt_timeout; // timeout counter (for debug) |
---|
[845] | 479 | |
---|
[839] | 480 | // handling coherence requests |
---|
[840] | 481 | sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval |
---|
| 482 | sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval |
---|
[845] | 483 | sc_signal<size_t> r_dcache_cc_word; // word counter for cc update |
---|
[839] | 484 | sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing |
---|
| 485 | |
---|
| 486 | // coherence clack handling |
---|
| 487 | sc_signal<bool> r_dcache_clack_req; // clack request |
---|
[845] | 488 | sc_signal<size_t> r_dcache_clack_way; // clack way |
---|
| 489 | sc_signal<size_t> r_dcache_clack_set; // clack set |
---|
[839] | 490 | |
---|
| 491 | // dcache flush handling |
---|
[845] | 492 | sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush |
---|
[839] | 493 | |
---|
| 494 | // ll response handling |
---|
[845] | 495 | sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp |
---|
[839] | 496 | |
---|
| 497 | // used by the TLB miss sub-fsm |
---|
[845] | 498 | sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss |
---|
| 499 | sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) |
---|
| 500 | sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte |
---|
| 501 | sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 |
---|
| 502 | sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 |
---|
| 503 | sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache |
---|
| 504 | sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache |
---|
[840] | 505 | sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache |
---|
[845] | 506 | sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb |
---|
| 507 | sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb |
---|
[839] | 508 | |
---|
| 509 | // ITLB and DTLB invalidation |
---|
[840] | 510 | sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index |
---|
[839] | 511 | sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter |
---|
| 512 | |
---|
| 513 | // communication between DCACHE FSM and ICACHE FSM |
---|
| 514 | sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor) |
---|
| 515 | sc_signal<int> r_dcache_xtn_opcode; // xtn request type |
---|
| 516 | |
---|
| 517 | // Filp-Flop in DCACHE FSM for saving the cleanup victim request |
---|
[840] | 518 | sc_signal<bool> r_dcache_cleanup_victim_req; |
---|
[839] | 519 | sc_signal<paddr_t> r_dcache_cleanup_victim_nline; |
---|
| 520 | |
---|
| 521 | // communication between DCACHE FSM and CC_SEND FSM |
---|
| 522 | sc_signal<bool> r_dcache_cc_send_req; // DCACHE cc_send request |
---|
| 523 | sc_signal<int> r_dcache_cc_send_type; // DCACHE cc_send request type |
---|
| 524 | sc_signal<paddr_t> r_dcache_cc_send_nline; // DCACHE cc_send nline |
---|
| 525 | sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way |
---|
| 526 | sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index |
---|
| 527 | |
---|
| 528 | // dcache directory extension |
---|
| 529 | bool *r_dcache_in_tlb; // copy exist in dtlb or itlb |
---|
| 530 | bool *r_dcache_contains_ptd; // cache line contains a PTD |
---|
| 531 | |
---|
| 532 | // Physical address extension for data access |
---|
| 533 | sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32) |
---|
| 534 | |
---|
[919] | 535 | // communication between DCACHE FSM and CC_TEST FSM |
---|
| 536 | sc_signal<bool> r_dcache_to_cc_test_req; |
---|
| 537 | sc_signal<uint32_t> r_dcache_to_cc_test_dest; |
---|
| 538 | |
---|
[839] | 539 | /////////////////////////////////// |
---|
| 540 | // VCI_CMD FSM REGISTERS |
---|
| 541 | /////////////////////////////////// |
---|
| 542 | sc_signal<int> r_vci_cmd_fsm; |
---|
[840] | 543 | sc_signal<size_t> r_vci_cmd_min; // used for write bursts |
---|
| 544 | sc_signal<size_t> r_vci_cmd_max; // used for write bursts |
---|
[845] | 545 | sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts |
---|
| 546 | sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss |
---|
[839] | 547 | |
---|
| 548 | /////////////////////////////////// |
---|
| 549 | // VCI_RSP FSM REGISTERS |
---|
| 550 | /////////////////////////////////// |
---|
| 551 | sc_signal<int> r_vci_rsp_fsm; |
---|
| 552 | sc_signal<size_t> r_vci_rsp_cpt; |
---|
| 553 | sc_signal<bool> r_vci_rsp_ins_error; |
---|
| 554 | sc_signal<bool> r_vci_rsp_data_error; |
---|
[845] | 555 | GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM |
---|
| 556 | GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM |
---|
[839] | 557 | |
---|
| 558 | /////////////////////////////////// |
---|
| 559 | // CC_SEND FSM REGISTER |
---|
| 560 | /////////////////////////////////// |
---|
| 561 | sc_signal<int> r_cc_send_fsm; // state register |
---|
| 562 | sc_signal<bool> r_cc_send_last_client; // 0 dcache / 1 icache |
---|
| 563 | |
---|
| 564 | /////////////////////////////////// |
---|
| 565 | // CC_RECEIVE FSM REGISTER |
---|
| 566 | /////////////////////////////////// |
---|
| 567 | sc_signal<int> r_cc_receive_fsm; // state register |
---|
| 568 | sc_signal<bool> r_cc_receive_data_ins; // request to : 0 dcache / 1 icache |
---|
| 569 | |
---|
| 570 | // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM |
---|
| 571 | sc_signal<size_t> r_cc_receive_word_idx; // word index |
---|
| 572 | GenericFifo<uint32_t> r_cc_receive_updt_fifo_be; |
---|
| 573 | GenericFifo<uint32_t> r_cc_receive_updt_fifo_data; |
---|
| 574 | GenericFifo<bool> r_cc_receive_updt_fifo_eop; |
---|
| 575 | |
---|
| 576 | // communication between CC_RECEIVE FSM and ICACHE FSM |
---|
[845] | 577 | sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request |
---|
| 578 | sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request |
---|
| 579 | sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way |
---|
| 580 | sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set |
---|
| 581 | sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index |
---|
[840] | 582 | sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address |
---|
[839] | 583 | |
---|
| 584 | // communication between CC_RECEIVE FSM and DCACHE FSM |
---|
[845] | 585 | sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request |
---|
| 586 | sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request |
---|
| 587 | sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way |
---|
| 588 | sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set |
---|
| 589 | sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index |
---|
[840] | 590 | sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address |
---|
[839] | 591 | |
---|
| 592 | /////////////////////////////////// |
---|
| 593 | // DSPIN CLACK INTERFACE REGISTER |
---|
| 594 | /////////////////////////////////// |
---|
| 595 | sc_signal<bool> r_dspin_clack_req; |
---|
| 596 | sc_signal<uint64_t> r_dspin_clack_flit; |
---|
[919] | 597 | sc_signal<bool> r_dspin_clack_test; |
---|
[840] | 598 | |
---|
[919] | 599 | /////////////////////////////////// |
---|
| 600 | // CC_TEST FSM REGISTER |
---|
| 601 | /////////////////////////////////// |
---|
| 602 | enum cc_test_result_e |
---|
| 603 | { |
---|
| 604 | CC_TEST_SUCCESS = 0, |
---|
| 605 | CC_TEST_FAILURE = 1, |
---|
| 606 | }; |
---|
| 607 | |
---|
| 608 | sc_signal<int> r_cc_test_fsm; |
---|
| 609 | sc_signal<bool> r_cc_test_to_cc_send_req; |
---|
| 610 | sc_signal<bool> r_cc_test_m2p_req; |
---|
| 611 | sc_signal<uint64_t> r_cc_test_m2p_sign; |
---|
| 612 | sc_signal<bool> r_cc_test_clack_req; |
---|
| 613 | sc_signal<uint64_t> r_cc_test_clack_sign; |
---|
| 614 | sc_signal<int> r_cc_test_to_dcache_result; |
---|
| 615 | |
---|
[839] | 616 | ////////////////////////////////////////////////////////////////// |
---|
| 617 | // processor, write buffer, caches , TLBs |
---|
| 618 | ////////////////////////////////////////////////////////////////// |
---|
| 619 | |
---|
[840] | 620 | iss_t r_iss; |
---|
| 621 | MultiWriteBuffer<paddr_t> r_wbuf; |
---|
| 622 | GenericCache<paddr_t> r_icache; |
---|
| 623 | GenericCache<paddr_t> r_dcache; |
---|
| 624 | GenericTlb<paddr_t> r_itlb; |
---|
| 625 | GenericTlb<paddr_t> r_dtlb; |
---|
[839] | 626 | |
---|
| 627 | ////////////////////////////////////////////////////////////////// |
---|
| 628 | // llsc registration buffer |
---|
| 629 | ////////////////////////////////////////////////////////////////// |
---|
| 630 | |
---|
[840] | 631 | sc_signal<paddr_t> r_dcache_llsc_paddr; |
---|
| 632 | sc_signal<uint32_t> r_dcache_llsc_key; |
---|
| 633 | sc_signal<uint32_t> r_dcache_llsc_count; |
---|
| 634 | sc_signal<bool> r_dcache_llsc_valid; |
---|
[839] | 635 | |
---|
| 636 | //////////////////////////////// |
---|
| 637 | // Activity counters |
---|
| 638 | //////////////////////////////// |
---|
| 639 | uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ |
---|
| 640 | uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE |
---|
| 641 | uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ |
---|
| 642 | uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE |
---|
| 643 | |
---|
| 644 | uint32_t m_cpt_icache_data_read; // ICACHE DATA READ |
---|
| 645 | uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE |
---|
| 646 | uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ |
---|
| 647 | uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE |
---|
| 648 | |
---|
[840] | 649 | uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen |
---|
| 650 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
[839] | 651 | |
---|
| 652 | // Cache activity counters |
---|
| 653 | uint32_t m_cpt_data_read; // total number of read data |
---|
| 654 | uint32_t m_cpt_data_write; // total number of write data |
---|
| 655 | uint32_t m_cpt_data_miss; // number of read miss |
---|
| 656 | uint32_t m_cpt_ins_miss; // number of instruction miss |
---|
| 657 | uint32_t m_cpt_unc_read; // number of read uncached |
---|
| 658 | uint32_t m_cpt_write_cached; // number of cached write |
---|
| 659 | uint32_t m_cpt_ins_read; // number of instruction read |
---|
| 660 | uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss |
---|
| 661 | |
---|
| 662 | uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer |
---|
| 663 | uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss |
---|
| 664 | uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read |
---|
| 665 | uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss |
---|
| 666 | |
---|
| 667 | uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions |
---|
| 668 | uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions |
---|
| 669 | uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions |
---|
| 670 | uint32_t m_cpt_write_transaction; // number of VCI write transactions |
---|
| 671 | uint32_t m_cpt_icache_unc_transaction; |
---|
| 672 | |
---|
| 673 | uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions |
---|
| 674 | uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions |
---|
| 675 | uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions |
---|
| 676 | uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions |
---|
| 677 | uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions |
---|
| 678 | uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions |
---|
| 679 | |
---|
| 680 | // TLB activity counters |
---|
| 681 | uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read |
---|
| 682 | uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss |
---|
| 683 | uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update |
---|
| 684 | uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line |
---|
| 685 | uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache |
---|
| 686 | |
---|
| 687 | uint32_t m_cpt_data_tlb_read; // number of data tlb read |
---|
| 688 | uint32_t m_cpt_data_tlb_miss; // number of data tlb miss |
---|
| 689 | uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update |
---|
| 690 | uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty |
---|
| 691 | uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache |
---|
| 692 | uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line |
---|
| 693 | uint32_t m_cpt_tlb_occup_dcache; |
---|
| 694 | |
---|
[840] | 695 | uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss |
---|
| 696 | uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss |
---|
[839] | 697 | uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc |
---|
| 698 | uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc |
---|
| 699 | uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty |
---|
| 700 | uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache |
---|
| 701 | uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache |
---|
| 702 | |
---|
| 703 | uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions |
---|
| 704 | uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions |
---|
| 705 | uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions |
---|
| 706 | uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions |
---|
| 707 | uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions |
---|
| 708 | uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions |
---|
| 709 | uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions |
---|
| 710 | uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions |
---|
| 711 | |
---|
[840] | 712 | uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions |
---|
| 713 | uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions |
---|
| 714 | uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions |
---|
| 715 | uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions |
---|
| 716 | uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions |
---|
| 717 | uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions |
---|
| 718 | uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions |
---|
| 719 | uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions |
---|
[839] | 720 | |
---|
| 721 | // coherence activity counters |
---|
[840] | 722 | uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands |
---|
| 723 | uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands |
---|
| 724 | uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands |
---|
| 725 | uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands |
---|
| 726 | uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands |
---|
[839] | 727 | |
---|
[840] | 728 | uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets |
---|
| 729 | uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets |
---|
| 730 | uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets |
---|
| 731 | uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets |
---|
[839] | 732 | |
---|
[840] | 733 | uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets |
---|
| 734 | uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets |
---|
[839] | 735 | |
---|
[840] | 736 | uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions |
---|
| 737 | uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions |
---|
| 738 | uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions |
---|
| 739 | uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions |
---|
[839] | 740 | |
---|
| 741 | uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate |
---|
| 742 | uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate |
---|
| 743 | |
---|
| 744 | uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate |
---|
| 745 | uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate |
---|
| 746 | |
---|
| 747 | // FSM activity counters |
---|
| 748 | uint32_t m_cpt_fsm_icache [64]; |
---|
| 749 | uint32_t m_cpt_fsm_dcache [64]; |
---|
| 750 | uint32_t m_cpt_fsm_cmd [64]; |
---|
| 751 | uint32_t m_cpt_fsm_rsp [64]; |
---|
| 752 | uint32_t m_cpt_fsm_cc_receive [64]; |
---|
| 753 | uint32_t m_cpt_fsm_cc_send [64]; |
---|
| 754 | |
---|
[840] | 755 | uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen |
---|
| 756 | bool m_monitor_ok; // used to debug cache output |
---|
| 757 | uint32_t m_monitor_base; |
---|
| 758 | uint32_t m_monitor_length; |
---|
[839] | 759 | |
---|
| 760 | protected: |
---|
| 761 | SC_HAS_PROCESS(VciCcVCacheWrapper); |
---|
| 762 | |
---|
| 763 | public: |
---|
| 764 | VciCcVCacheWrapper( |
---|
| 765 | sc_module_name name, |
---|
| 766 | const int proc_id, |
---|
| 767 | const soclib::common::MappingTable &mtd, |
---|
| 768 | const soclib::common::IntTab &srcid, |
---|
| 769 | const size_t cc_global_id, |
---|
| 770 | const size_t itlb_ways, |
---|
| 771 | const size_t itlb_sets, |
---|
| 772 | const size_t dtlb_ways, |
---|
| 773 | const size_t dtlb_sets, |
---|
| 774 | const size_t icache_ways, |
---|
| 775 | const size_t icache_sets, |
---|
| 776 | const size_t icache_words, |
---|
| 777 | const size_t dcache_ways, |
---|
| 778 | const size_t dcache_sets, |
---|
| 779 | const size_t dcache_words, |
---|
| 780 | const size_t wbuf_nlines, |
---|
| 781 | const size_t wbuf_nwords, |
---|
| 782 | const size_t x_width, |
---|
| 783 | const size_t y_width, |
---|
| 784 | const uint32_t max_frozen_cycles, |
---|
| 785 | const uint32_t debug_start_cycle, |
---|
| 786 | const bool debug_ok ); |
---|
| 787 | |
---|
| 788 | ~VciCcVCacheWrapper(); |
---|
| 789 | |
---|
| 790 | void print_cpi(); |
---|
| 791 | void print_stats(); |
---|
| 792 | void clear_stats(); |
---|
| 793 | void print_trace(size_t mode = 0); |
---|
| 794 | void cache_monitor(paddr_t addr); |
---|
| 795 | void start_monitor(paddr_t,paddr_t); |
---|
| 796 | void stop_monitor(); |
---|
[840] | 797 | inline void iss_set_debug_mask(uint v) |
---|
[839] | 798 | { |
---|
[840] | 799 | r_iss.set_debug_mask(v); |
---|
[839] | 800 | } |
---|
| 801 | |
---|
| 802 | ///////////////////////////////////////////////////////////// |
---|
| 803 | // Set the m_dcache_paddr_ext_reset attribute |
---|
| 804 | // |
---|
| 805 | // The r_dcache_paddr_ext register will be initialized after |
---|
| 806 | // reset with the m_dcache_paddr_ext_reset value |
---|
| 807 | ///////////////////////////////////////////////////////////// |
---|
| 808 | inline void set_dcache_paddr_ext_reset(uint32_t v) |
---|
| 809 | { |
---|
| 810 | m_dcache_paddr_ext_reset = v; |
---|
| 811 | } |
---|
| 812 | |
---|
| 813 | ///////////////////////////////////////////////////////////// |
---|
| 814 | // Set the m_icache_paddr_ext_reset attribute |
---|
| 815 | // |
---|
| 816 | // The r_icache_paddr_ext register will be initialized after |
---|
| 817 | // reset with the m_icache_paddr_ext_reset value |
---|
| 818 | ///////////////////////////////////////////////////////////// |
---|
| 819 | inline void set_icache_paddr_ext_reset(uint32_t v) |
---|
| 820 | { |
---|
| 821 | m_icache_paddr_ext_reset = v; |
---|
| 822 | } |
---|
| 823 | |
---|
| 824 | private: |
---|
| 825 | void transition(); |
---|
| 826 | void genMoore(); |
---|
| 827 | |
---|
| 828 | soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); |
---|
| 829 | soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); |
---|
| 830 | }; |
---|
| 831 | |
---|
| 832 | }} |
---|
| 833 | |
---|
| 834 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */ |
---|
| 835 | |
---|
| 836 | // Local Variables: |
---|
| 837 | // tab-width: 4 |
---|
| 838 | // c-basic-offset: 4 |
---|
| 839 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 840 | // indent-tabs-mode: nil |
---|
| 841 | // End: |
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| 842 | |
---|
| 843 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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