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vci_cc_vcache_wrapper.cpp @ 865

Last change on this file since 865 was 853, checked in by cfuguet, 10 years ago

reconf: introducing assert to detect early watchdog timeout.

Introducing an assert in the vci_cc_vcache_wrapper component. An early watchdog timeout arises when the timeout threshold is less than the max latency of a read miss transaction.

File size: 245.1 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include <signal.h>
32
33	#include "arithmetics.h"
34	#include "../include/vci_cc_vcache_wrapper.h"
35
36	#define DEBUG_DCACHE 1
37	#define DEBUG_ICACHE 1
38	#define DEBUG_CMD 0
39
40	namespace soclib {
41	namespace caba {
42
43	namespace {
44	const char * icache_fsm_state_str[] = {
45	"ICACHE_IDLE",
46
47	"ICACHE_XTN_TLB_FLUSH",
48	"ICACHE_XTN_CACHE_FLUSH",
49	"ICACHE_XTN_CACHE_FLUSH_GO",
50	"ICACHE_XTN_TLB_INVAL",
51	"ICACHE_XTN_CACHE_INVAL_VA",
52	"ICACHE_XTN_CACHE_INVAL_PA",
53	"ICACHE_XTN_CACHE_INVAL_GO",
54
55	"ICACHE_TLB_WAIT",
56
57	"ICACHE_MISS_SELECT",
58	"ICACHE_MISS_CLEAN",
59	"ICACHE_MISS_WAIT",
60	"ICACHE_MISS_DATA_UPDT",
61	"ICACHE_MISS_DIR_UPDT",
62
63	"ICACHE_UNC_WAIT",
64
65	"ICACHE_CC_CHECK",
66	"ICACHE_CC_UPDT",
67	"ICACHE_CC_INVAL",
68	};
69
70	const char * dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IC_PADDR_EXT",
90	"DCACHE_XTN_IT_INVAL",
91	"DCACHE_XTN_DC_FLUSH",
92	"DCACHE_XTN_DC_FLUSH_GO",
93	"DCACHE_XTN_DC_INVAL_VA",
94	"DCACHE_XTN_DC_INVAL_PA",
95	"DCACHE_XTN_DC_INVAL_END",
96	"DCACHE_XTN_DC_INVAL_GO",
97	"DCACHE_XTN_DT_INVAL",
98
99	"DCACHE_DIRTY_GET_PTE",
100	"DCACHE_DIRTY_WAIT",
101
102	"DCACHE_MISS_SELECT",
103	"DCACHE_MISS_CLEAN",
104	"DCACHE_MISS_WAIT",
105	"DCACHE_MISS_DATA_UPDT",
106	"DCACHE_MISS_DIR_UPDT",
107
108	"DCACHE_UNC_WAIT",
109	"DCACHE_LL_WAIT",
110	"DCACHE_SC_WAIT",
111
112	"DCACHE_CC_CHECK",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_INVAL",
115
116	"DCACHE_INVAL_TLB_SCAN",
117	};
118
119	const char * cmd_fsm_state_str[] = {
120	"CMD_IDLE",
121	"CMD_INS_MISS",
122	"CMD_INS_UNC",
123	"CMD_DATA_MISS",
124	"CMD_DATA_UNC_READ",
125	"CMD_DATA_UNC_WRITE",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char * vci_pktid_type_str[] = {
133	"TYPE_DATA_UNC",
134	"TYPE_READ_DATA_MISS",
135	"TYPE_READ_INS_UNC",
136	"TYPE_READ_INS_MISS",
137	"TYPE_WRITE",
138	"TYPE_CAS",
139	"TYPE_LL",
140	"TYPE_SC",
141	};
142
143	const char * vci_cmd_type_str[] = {
144	"NOP or STORE_COND",
145	"READ",
146	"WRITE",
147	"LOCKED_READ"
148	};
149
150	const char * rsp_fsm_state_str[] = {
151	"RSP_IDLE",
152	"RSP_INS_MISS",
153	"RSP_INS_UNC",
154	"RSP_DATA_MISS",
155	"RSP_DATA_UNC",
156	"RSP_DATA_LL",
157	"RSP_DATA_WRITE",
158	};
159
160	const char * cc_receive_fsm_state_str[] = {
161	"CC_RECEIVE_IDLE",
162	"CC_RECEIVE_BRDCAST_HEADER",
163	"CC_RECEIVE_BRDCAST_NLINE",
164	"CC_RECEIVE_INS_INVAL_HEADER",
165	"CC_RECEIVE_INS_INVAL_NLINE",
166	"CC_RECEIVE_INS_UPDT_HEADER",
167	"CC_RECEIVE_INS_UPDT_NLINE",
168	"CC_RECEIVE_INS_UPDT_DATA",
169	"CC_RECEIVE_DATA_INVAL_HEADER",
170	"CC_RECEIVE_DATA_INVAL_NLINE",
171	"CC_RECEIVE_DATA_UPDT_HEADER",
172	"CC_RECEIVE_DATA_UPDT_NLINE",
173	"CC_RECEIVE_DATA_UPDT_DATA",
174	};
175
176	const char * cc_send_fsm_state_str[] = {
177	"CC_SEND_IDLE",
178	"CC_SEND_CLEANUP_1",
179	"CC_SEND_CLEANUP_2",
180	"CC_SEND_MULTI_ACK",
181	};
182	}
183
184	#define tmpl(...) \
185	template<typename vci_param, \
186	size_t dspin_in_width, \
187	size_t dspin_out_width, \
188	typename iss_t> __VA_ARGS__ \
189	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
190
191	using namespace soclib::common;
192
193	/////////////////////////////////
194	tmpl(/**/)::VciCcVCacheWrapper(
195	sc_module_name name,
196	const int proc_id,
197	const MappingTable &mtd,
198	const IntTab &srcid,
199	const size_t cc_global_id,
200	const size_t itlb_ways,
201	const size_t itlb_sets,
202	const size_t dtlb_ways,
203	const size_t dtlb_sets,
204	const size_t icache_ways,
205	const size_t icache_sets,
206	const size_t icache_words,
207	const size_t dcache_ways,
208	const size_t dcache_sets,
209	const size_t dcache_words,
210	const size_t wbuf_nlines,
211	const size_t wbuf_nwords,
212	const size_t x_width,
213	const size_t y_width,
214	const uint32_t max_frozen_cycles,
215	const uint32_t debug_start_cycle,
216	const bool debug_ok)
217	: soclib::caba::BaseModule(name),
218
219	p_clk("p_clk"),
220	p_resetn("p_resetn"),
221	p_vci("p_vci"),
222	p_dspin_m2p("p_dspin_m2p"),
223	p_dspin_p2m("p_dspin_p2m"),
224	p_dspin_clack("p_dspin_clack"),
225
226	m_cacheability_table( mtd.getCacheabilityTable()),
227	m_srcid(mtd.indexForId(srcid)),
228	m_cc_global_id(cc_global_id),
229	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
230	m_itlb_ways(itlb_ways),
231	m_itlb_sets(itlb_sets),
232	m_dtlb_ways(dtlb_ways),
233	m_dtlb_sets(dtlb_sets),
234	m_icache_ways(icache_ways),
235	m_icache_sets(icache_sets),
236	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
237	m_icache_words(icache_words),
238	m_dcache_ways(dcache_ways),
239	m_dcache_sets(dcache_sets),
240	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
241	m_dcache_words(dcache_words),
242	m_x_width(x_width),
243	m_y_width(y_width),
244	m_proc_id(proc_id),
245	m_max_frozen_cycles(max_frozen_cycles),
246	m_paddr_nbits(vci_param::N),
247	m_debug_start_cycle(debug_start_cycle),
248	m_debug_ok(debug_ok),
249	m_dcache_paddr_ext_reset(0),
250	m_icache_paddr_ext_reset(0),
251
252	r_mmu_ptpr("r_mmu_ptpr"),
253	r_mmu_mode("r_mmu_mode"),
254	r_mmu_word_lo("r_mmu_word_lo"),
255	r_mmu_word_hi("r_mmu_word_hi"),
256	r_mmu_ibvar("r_mmu_ibvar"),
257	r_mmu_dbvar("r_mmu_dbvar"),
258	r_mmu_ietr("r_mmu_ietr"),
259	r_mmu_detr("r_mmu_detr"),
260
261	r_icache_fsm("r_icache_fsm"),
262	r_icache_fsm_save("r_icache_fsm_save"),
263	r_icache_vci_paddr("r_icache_vci_paddr"),
264	r_icache_vaddr_save("r_icache_vaddr_save"),
265
266	r_icache_miss_way("r_icache_miss_way"),
267	r_icache_miss_set("r_icache_miss_set"),
268	r_icache_miss_word("r_icache_miss_word"),
269	r_icache_miss_inval("r_icache_miss_inval"),
270	r_icache_miss_clack("r_icache_miss_clack"),
271
272	r_icache_cc_way("r_icache_cc_way"),
273	r_icache_cc_set("r_icache_cc_set"),
274	r_icache_cc_word("r_icache_cc_word"),
275	r_icache_cc_need_write("r_icache_cc_need_write"),
276
277	r_icache_flush_count("r_icache_flush_count"),
278
279	r_icache_miss_req("r_icache_miss_req"),
280	r_icache_unc_req("r_icache_unc_req"),
281
282	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
283	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
284
285	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
286	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
287
288	r_icache_cc_send_req("r_icache_cc_send_req"),
289	r_icache_cc_send_type("r_icache_cc_send_type"),
290	r_icache_cc_send_nline("r_icache_cc_send_nline"),
291	r_icache_cc_send_way("r_icache_cc_send_way"),
292	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
293
294	r_dcache_fsm("r_dcache_fsm"),
295	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
296	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
297
298	r_dcache_wbuf_req("r_dcache_wbuf_req"),
299	r_dcache_updt_req("r_dcache_updt_req"),
300	r_dcache_save_vaddr("r_dcache_save_vaddr"),
301	r_dcache_save_wdata("r_dcache_save_wdata"),
302	r_dcache_save_be("r_dcache_save_be"),
303	r_dcache_save_paddr("r_dcache_save_paddr"),
304	r_dcache_save_cache_way("r_dcache_save_cache_way"),
305	r_dcache_save_cache_set("r_dcache_save_cache_set"),
306	r_dcache_save_cache_word("r_dcache_save_cache_word"),
307
308	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
309	r_dcache_dirty_way("r_dcache_dirty_way"),
310	r_dcache_dirty_set("r_dcache_dirty_set"),
311
312	r_dcache_vci_paddr("r_dcache_vci_paddr"),
313	r_dcache_vci_wdata("r_dcache_vci_wdata"),
314	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
315	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
316	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
317	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
318	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
319	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
320	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
321	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
322	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
323	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
324	r_dcache_vci_miss_trdid("r_dcache_vci_miss_trdid"),
325
326	r_dcache_xtn_way("r_dcache_xtn_way"),
327	r_dcache_xtn_set("r_dcache_xtn_set"),
328
329	r_dcache_miss_type("r_dcache_miss_type"),
330	r_dcache_miss_word("r_dcache_miss_word"),
331	r_dcache_miss_way("r_dcache_miss_way"),
332	r_dcache_miss_set("r_dcache_miss_set"),
333	r_dcache_miss_inval("r_dcache_miss_inval"),
334	r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"),
335	r_dcache_miss_wdt("r_dcache_miss_wdt"),
336	r_dcache_wdt_timeout("r_dcache_wdt_timeout"),
337
338	r_dcache_cc_way("r_dcache_cc_way"),
339	r_dcache_cc_set("r_dcache_cc_set"),
340	r_dcache_cc_word("r_dcache_cc_word"),
341	r_dcache_cc_need_write("r_dcache_cc_need_write"),
342
343	r_dcache_flush_count("r_dcache_flush_count"),
344
345	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
346
347	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
348	r_dcache_tlb_ins("r_dcache_tlb_ins"),
349	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
350	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
351	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
352	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
353	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
354	r_dcache_tlb_way("r_dcache_tlb_way"),
355	r_dcache_tlb_set("r_dcache_tlb_set"),
356
357	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
358	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
359
360	r_dcache_xtn_req("r_dcache_xtn_req"),
361	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
362
363	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
364	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
365
366	r_dcache_cc_send_req("r_dcache_cc_send_req"),
367	r_dcache_cc_send_type("r_dcache_cc_send_type"),
368	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
369	r_dcache_cc_send_way("r_dcache_cc_send_way"),
370	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
371
372	r_vci_cmd_fsm("r_vci_cmd_fsm"),
373	r_vci_cmd_min("r_vci_cmd_min"),
374	r_vci_cmd_max("r_vci_cmd_max"),
375	r_vci_cmd_cpt("r_vci_cmd_cpt"),
376	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
377
378	r_vci_rsp_fsm("r_vci_rsp_fsm"),
379	r_vci_rsp_cpt("r_vci_rsp_cpt"),
380	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
381	r_vci_rsp_data_error("r_vci_rsp_data_error"),
382	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
383	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
384
385	r_cc_send_fsm("r_cc_send_fsm"),
386	r_cc_send_last_client("r_cc_send_last_client"),
387
388	r_cc_receive_fsm("r_cc_receive_fsm"),
389	r_cc_receive_data_ins("r_cc_receive_data_ins"),
390	r_cc_receive_word_idx("r_cc_receive_word_idx"),
391	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
392	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
393	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
394
395	r_cc_receive_icache_req("r_cc_receive_icache_req"),
396	r_cc_receive_icache_type("r_cc_receive_icache_type"),
397	r_cc_receive_icache_way("r_cc_receive_icache_way"),
398	r_cc_receive_icache_set("r_cc_receive_icache_set"),
399	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
400	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
401
402	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
403	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
404	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
405	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
406	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
407	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
408
409	r_iss(this->name(), proc_id),
410	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
411	r_icache("icache", icache_ways, icache_sets, icache_words),
412	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
413	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
414	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
415	{
416	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
417
418	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
419	"Need more PLEN bits.");
420
421	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
422	"Need more TRDID bits.");
423
424	assert((icache_words == dcache_words) and
425	"icache_words and dcache_words parameters must be equal");
426
427	assert((itlb_sets == dtlb_sets) and
428	"itlb_sets and dtlb_sets parameters must be etqual");
429
430	assert((itlb_ways == dtlb_ways) and
431	"itlb_ways and dtlb_ways parameters must be etqual");
432
433	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
434	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
435	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
436	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
437	(uint32_log2(m_icache_words << 2));
438
439	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
440
441	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
442	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
443
444	SC_METHOD(transition);
445	dont_initialize();
446	sensitive << p_clk.pos();
447
448	SC_METHOD(genMoore);
449	dont_initialize();
450	sensitive << p_clk.neg();
451
452	typename iss_t::CacheInfo cache_info;
453	cache_info.has_mmu = true;
454	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
455	cache_info.icache_assoc = icache_ways;
456	cache_info.icache_n_lines = icache_sets;
457	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
458	cache_info.dcache_assoc = dcache_ways;
459	cache_info.dcache_n_lines = dcache_sets;
460	r_iss.setCacheInfo(cache_info);
461	}
462
463	/////////////////////////////////////
464	tmpl(/**/)::~VciCcVCacheWrapper()
465	/////////////////////////////////////
466	{
467	delete [] r_dcache_in_tlb;
468	delete [] r_dcache_contains_ptd;
469	}
470
471	////////////////////////
472	tmpl(void)::print_cpi()
473	////////////////////////
474	{
475	std::cout << name() << " CPI = "
476	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
477	}
478
479	////////////////////////////////////
480	tmpl(void)::print_trace(size_t mode)
481	////////////////////////////////////
482	{
483	// b0 : write buffer trace
484	// b1 : dump processor registers
485	// b2 : dcache trace
486	// b3 : icache trace
487	// b4 : dtlb trace
488	// b5 : itlb trace
489	// b6 : SR (ISS register 32)
490
491	std::cout << std::dec << "PROC " << name() << std::endl;
492
493	std::cout << " " << m_ireq << std::endl;
494	std::cout << " " << m_irsp << std::endl;
495	std::cout << " " << m_dreq << std::endl;
496	std::cout << " " << m_drsp << std::endl;
497
498	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
499	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
500	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
501	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
502	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
503	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
504	<< " \| MMU = " << r_mmu_mode.read();
505
506	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
507	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
508	std::cout << std::endl;
509
510	if (mode & 0x01)
511	{
512	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
513	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
514	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
515	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
516
517	r_wbuf.printTrace((mode >> 1) & 1);
518	}
519	if (mode & 0x02)
520	{
521	r_iss.dump();
522	}
523	if (mode & 0x04)
524	{
525	std::cout << " Data Cache" << std::endl;
526	r_dcache.printTrace();
527	}
528	if (mode & 0x08)
529	{
530	std::cout << " Instruction Cache" << std::endl;
531	r_icache.printTrace();
532	}
533	if (mode & 0x10)
534	{
535	std::cout << " Data TLB" << std::endl;
536	r_dtlb.printTrace();
537	}
538	if (mode & 0x20)
539	{
540	std::cout << " Instruction TLB" << std::endl;
541	r_itlb.printTrace();
542	}
543	if (mode & 0x40)
544	{
545	uint32_t status = r_iss.debugGetRegisterValue(32);
546	std::cout << name();
547	if (status != m_previous_status ) std::cout << " NEW ";
548	std::cout << " status = " << std::hex << status << " " << std::endl;
549	m_previous_status = status;
550	}
551	}
552
553	//////////////////////////////////////////
554	tmpl(void)::cache_monitor(paddr_t addr)
555	//////////////////////////////////////////
556	{
557	bool cache_hit;
558	size_t cache_way = 0;
559	size_t cache_set = 0;
560	size_t cache_word = 0;
561	uint32_t cache_rdata = 0;
562
563	cache_hit = r_dcache.read_neutral(addr,
564	&cache_rdata,
565	&cache_way,
566	&cache_set,
567	&cache_word);
568
569	if (cache_hit != m_debug_previous_d_hit)
570	{
571	std::cout << "Monitor PROC " << name()
572	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
573	<< " / HIT = " << cache_hit
574	<< " / PADDR = " << std::hex << addr
575	<< " / DATA = " << cache_rdata
576	<< " / WAY = " << cache_way << std::endl;
577	m_debug_previous_d_hit = cache_hit;
578	}
579
580	cache_hit = r_icache.read_neutral(addr,
581	&cache_rdata,
582	&cache_way,
583	&cache_set,
584	&cache_word);
585
586	if (cache_hit != m_debug_previous_i_hit)
587	{
588	std::cout << "Monitor PROC " << name()
589	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
590	<< " / HIT = " << cache_hit
591	<< " / PADDR = " << std::hex << addr
592	<< " / DATA = " << cache_rdata
593	<< " / WAY = " << cache_way << std::endl;
594	m_debug_previous_i_hit = cache_hit;
595	}
596	}
597
598	/*
599	////////////////////////
600	tmpl(void)::print_stats()
601	////////////////////////
602	{
603	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
604	std::cout << name() << std::endl
605	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
606	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
607	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
608	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
609	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
610	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
611	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
612	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
613	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
614	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
615	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
616	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
617	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
618	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
619	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
620	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
621	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
622	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
623	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
624	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
625	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
626	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
627	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
628	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
629	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
630	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
631	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
632	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
633	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
634	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
635	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
636	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
637	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
638	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
639	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
640	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
641	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
642	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
643	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
644	}
645
646	////////////////////////
647	tmpl(void)::clear_stats()
648	////////////////////////
649	{
650	m_cpt_dcache_data_read = 0;
651	m_cpt_dcache_data_write = 0;
652	m_cpt_dcache_dir_read = 0;
653	m_cpt_dcache_dir_write = 0;
654	m_cpt_icache_data_read = 0;
655	m_cpt_icache_data_write = 0;
656	m_cpt_icache_dir_read = 0;
657	m_cpt_icache_dir_write = 0;
658
659	m_cpt_frz_cycles = 0;
660	m_cpt_dcache_frz_cycles = 0;
661	m_cpt_total_cycles = 0;
662
663	m_cpt_read = 0;
664	m_cpt_write = 0;
665	m_cpt_data_miss = 0;
666	m_cpt_ins_miss = 0;
667	m_cpt_unc_read = 0;
668	m_cpt_write_cached = 0;
669	m_cpt_ins_read = 0;
670
671	m_cost_write_frz = 0;
672	m_cost_data_miss_frz = 0;
673	m_cost_unc_read_frz = 0;
674	m_cost_ins_miss_frz = 0;
675
676	m_cpt_imiss_transaction = 0;
677	m_cpt_dmiss_transaction = 0;
678	m_cpt_unc_transaction = 0;
679	m_cpt_write_transaction = 0;
680	m_cpt_icache_unc_transaction = 0;
681
682	m_cost_imiss_transaction = 0;
683	m_cost_dmiss_transaction = 0;
684	m_cost_unc_transaction = 0;
685	m_cost_write_transaction = 0;
686	m_cost_icache_unc_transaction = 0;
687	m_length_write_transaction = 0;
688
689	m_cpt_ins_tlb_read = 0;
690	m_cpt_ins_tlb_miss = 0;
691	m_cpt_ins_tlb_update_acc = 0;
692
693	m_cpt_data_tlb_read = 0;
694	m_cpt_data_tlb_miss = 0;
695	m_cpt_data_tlb_update_acc = 0;
696	m_cpt_data_tlb_update_dirty = 0;
697	m_cpt_ins_tlb_hit_dcache = 0;
698	m_cpt_data_tlb_hit_dcache = 0;
699	m_cpt_ins_tlb_occup_cache = 0;
700	m_cpt_data_tlb_occup_cache = 0;
701
702	m_cost_ins_tlb_miss_frz = 0;
703	m_cost_data_tlb_miss_frz = 0;
704	m_cost_ins_tlb_update_acc_frz = 0;
705	m_cost_data_tlb_update_acc_frz = 0;
706	m_cost_data_tlb_update_dirty_frz = 0;
707	m_cost_ins_tlb_occup_cache_frz = 0;
708	m_cost_data_tlb_occup_cache_frz = 0;
709
710	m_cpt_itlbmiss_transaction = 0;
711	m_cpt_itlb_ll_transaction = 0;
712	m_cpt_itlb_sc_transaction = 0;
713	m_cpt_dtlbmiss_transaction = 0;
714	m_cpt_dtlb_ll_transaction = 0;
715	m_cpt_dtlb_sc_transaction = 0;
716	m_cpt_dtlb_ll_dirty_transaction = 0;
717	m_cpt_dtlb_sc_dirty_transaction = 0;
718
719	m_cost_itlbmiss_transaction = 0;
720	m_cost_itlb_ll_transaction = 0;
721	m_cost_itlb_sc_transaction = 0;
722	m_cost_dtlbmiss_transaction = 0;
723	m_cost_dtlb_ll_transaction = 0;
724	m_cost_dtlb_sc_transaction = 0;
725	m_cost_dtlb_ll_dirty_transaction = 0;
726	m_cost_dtlb_sc_dirty_transaction = 0;
727
728	m_cpt_cc_update_data = 0;
729	m_cpt_cc_inval_ins = 0;
730	m_cpt_cc_inval_data = 0;
731	m_cpt_cc_broadcast = 0;
732
733	m_cost_updt_data_frz = 0;
734	m_cost_inval_ins_frz = 0;
735	m_cost_inval_data_frz = 0;
736	m_cost_broadcast_frz = 0;
737
738	m_cpt_cc_cleanup_data = 0;
739	m_cpt_cc_cleanup_ins = 0;
740	}
741
742	*/
743
744	/////////////////////////
745	tmpl(void)::transition()
746	/////////////////////////
747	{
748	if (not p_resetn.read())
749	{
750	r_iss.reset();
751	r_wbuf.reset();
752	r_icache.reset();
753	r_dcache.reset();
754	r_itlb.reset();
755	r_dtlb.reset();
756
757	r_dcache_fsm = DCACHE_IDLE;
758	r_icache_fsm = ICACHE_IDLE;
759	r_vci_cmd_fsm = CMD_IDLE;
760	r_vci_rsp_fsm = RSP_IDLE;
761	r_cc_receive_fsm = CC_RECEIVE_IDLE;
762	r_cc_send_fsm = CC_SEND_IDLE;
763
764	// reset data physical address extension
765	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
766
767	// reset inst physical address extension
768	r_icache_paddr_ext = m_icache_paddr_ext_reset;
769
770	// reset dcache directory extension
771	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
772	{
773	r_dcache_in_tlb[i] = false;
774	r_dcache_contains_ptd[i] = false;
775	}
776
777	// Response FIFOs and cleanup buffer
778	r_vci_rsp_fifo_icache.init();
779	r_vci_rsp_fifo_dcache.init();
780
781	// ICACHE & DCACHE activated
782	// ITLB & DTLB desactivated
783	r_mmu_mode = 0x3;
784
785	// No request from ICACHE FSM to CMD FSM
786	r_icache_miss_req = false;
787	r_icache_unc_req = false;
788
789	// No request from ICACHE_FSM to DCACHE FSM
790	r_icache_tlb_miss_req = false;
791
792	// No request from ICACHE_FSM to CC_SEND FSM
793	r_icache_cc_send_req = false;
794	r_icache_cleanup_victim_req = false;
795
796	r_icache_clack_req = false;
797
798	// No pending write in pipeline
799	r_dcache_wbuf_req = false;
800	r_dcache_updt_req = false;
801
802	// No request from DCACHE_FSM to CMD_FSM
803	r_dcache_vci_miss_req = false;
804	r_dcache_vci_unc_req = false;
805	r_dcache_vci_cas_req = false;
806	r_dcache_vci_ll_req = false;
807	r_dcache_vci_sc_req = false;
808
809	// No processor XTN request pending
810	r_dcache_xtn_req = false;
811
812	// No request from DCACHE FSM to CC_SEND FSM
813	r_dcache_cc_send_req = false;
814	r_dcache_cleanup_victim_req = false;
815
816	r_dcache_clack_req = false;
817
818	// Reset watchdog timer threshold to max value
819	r_dcache_miss_wdt_max = UINT32_MAX;
820	r_dcache_wdt_timeout = 0;
821
822	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
823	r_cc_receive_icache_req = false;
824	r_cc_receive_dcache_req = false;
825
826	// last cc_send client was dcache
827	r_cc_send_last_client = false;
828
829	// No pending cleanup after a replacement
830	r_icache_miss_clack = false;
831	r_dcache_miss_clack = false;
832
833	// No signalisation of a coherence request matching a pending miss
834	r_icache_miss_inval = false;
835	r_dcache_miss_inval = false;
836
837	r_dspin_clack_req = false;
838
839	// No signalisation of errors
840	r_vci_rsp_ins_error = false;
841	r_vci_rsp_data_error = false;
842
843	// Debug variables
844	m_debug_previous_i_hit = false;
845	m_debug_previous_d_hit = false;
846	m_debug_icache_fsm = false;
847	m_debug_dcache_fsm = false;
848	m_debug_cmd_fsm = false;
849
850	// activity counters
851	m_cpt_dcache_data_read = 0;
852	m_cpt_dcache_data_write = 0;
853	m_cpt_dcache_dir_read = 0;
854	m_cpt_dcache_dir_write = 0;
855	m_cpt_icache_data_read = 0;
856	m_cpt_icache_data_write = 0;
857	m_cpt_icache_dir_read = 0;
858	m_cpt_icache_dir_write = 0;
859
860	m_cpt_frz_cycles = 0;
861	m_cpt_total_cycles = 0;
862	m_cpt_stop_simulation = 0;
863
864	m_cpt_data_miss = 0;
865	m_cpt_ins_miss = 0;
866	m_cpt_unc_read = 0;
867	m_cpt_write_cached = 0;
868	m_cpt_ins_read = 0;
869
870	m_cost_write_frz = 0;
871	m_cost_data_miss_frz = 0;
872	m_cost_unc_read_frz = 0;
873	m_cost_ins_miss_frz = 0;
874
875	m_cpt_imiss_transaction = 0;
876	m_cpt_dmiss_transaction = 0;
877	m_cpt_unc_transaction = 0;
878	m_cpt_write_transaction = 0;
879	m_cpt_icache_unc_transaction = 0;
880
881	m_cost_imiss_transaction = 0;
882	m_cost_dmiss_transaction = 0;
883	m_cost_unc_transaction = 0;
884	m_cost_write_transaction = 0;
885	m_cost_icache_unc_transaction = 0;
886	m_length_write_transaction = 0;
887
888	m_cpt_ins_tlb_read = 0;
889	m_cpt_ins_tlb_miss = 0;
890	m_cpt_ins_tlb_update_acc = 0;
891
892	m_cpt_data_tlb_read = 0;
893	m_cpt_data_tlb_miss = 0;
894	m_cpt_data_tlb_update_acc = 0;
895	m_cpt_data_tlb_update_dirty = 0;
896	m_cpt_ins_tlb_hit_dcache = 0;
897	m_cpt_data_tlb_hit_dcache = 0;
898	m_cpt_ins_tlb_occup_cache = 0;
899	m_cpt_data_tlb_occup_cache = 0;
900
901	m_cost_ins_tlb_miss_frz = 0;
902	m_cost_data_tlb_miss_frz = 0;
903	m_cost_ins_tlb_update_acc_frz = 0;
904	m_cost_data_tlb_update_acc_frz = 0;
905	m_cost_data_tlb_update_dirty_frz = 0;
906	m_cost_ins_tlb_occup_cache_frz = 0;
907	m_cost_data_tlb_occup_cache_frz = 0;
908
909	m_cpt_ins_tlb_inval = 0;
910	m_cpt_data_tlb_inval = 0;
911	m_cost_ins_tlb_inval_frz = 0;
912	m_cost_data_tlb_inval_frz = 0;
913
914	m_cpt_cc_broadcast = 0;
915
916	m_cost_updt_data_frz = 0;
917	m_cost_inval_ins_frz = 0;
918	m_cost_inval_data_frz = 0;
919	m_cost_broadcast_frz = 0;
920
921	m_cpt_cc_cleanup_data = 0;
922	m_cpt_cc_cleanup_ins = 0;
923
924	m_cpt_itlbmiss_transaction = 0;
925	m_cpt_itlb_ll_transaction = 0;
926	m_cpt_itlb_sc_transaction = 0;
927	m_cpt_dtlbmiss_transaction = 0;
928	m_cpt_dtlb_ll_transaction = 0;
929	m_cpt_dtlb_sc_transaction = 0;
930	m_cpt_dtlb_ll_dirty_transaction = 0;
931	m_cpt_dtlb_sc_dirty_transaction = 0;
932
933	m_cost_itlbmiss_transaction = 0;
934	m_cost_itlb_ll_transaction = 0;
935	m_cost_itlb_sc_transaction = 0;
936	m_cost_dtlbmiss_transaction = 0;
937	m_cost_dtlb_ll_transaction = 0;
938	m_cost_dtlb_sc_transaction = 0;
939	m_cost_dtlb_ll_dirty_transaction = 0;
940	m_cost_dtlb_sc_dirty_transaction = 0;
941	/*
942	m_cpt_dcache_frz_cycles = 0;
943	m_cpt_read = 0;
944	m_cpt_write = 0;
945	m_cpt_cc_update_data = 0;
946	m_cpt_cc_inval_ins = 0;
947	m_cpt_cc_inval_data = 0;
948	*/
949
950	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
951	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
952	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
953	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
954
955	// init the llsc reservation buffer
956	r_dcache_llsc_valid = false;
957	m_monitor_ok = false;
958
959	return;
960	}
961
962	// Response FIFOs default values
963	bool vci_rsp_fifo_icache_get = false;
964	bool vci_rsp_fifo_icache_put = false;
965	uint32_t vci_rsp_fifo_icache_data = 0;
966
967	bool vci_rsp_fifo_dcache_get = false;
968	bool vci_rsp_fifo_dcache_put = false;
969	uint32_t vci_rsp_fifo_dcache_data = 0;
970
971	// updt fifo
972	bool cc_receive_updt_fifo_get = false;
973	bool cc_receive_updt_fifo_put = false;
974	uint32_t cc_receive_updt_fifo_be = 0;
975	uint32_t cc_receive_updt_fifo_data = 0;
976	bool cc_receive_updt_fifo_eop = false;
977
978	#ifdef INSTRUMENTATION
979	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
980	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
981	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
982	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
983	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
984	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
985	#endif
986
987	m_cpt_total_cycles++;
988
989	m_debug_icache_fsm = m_debug_icache_fsm \|\|
990	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
991	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
992	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
993	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
994	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
995
996	/////////////////////////////////////////////////////////////////////
997	// Get data and instruction requests from processor
998	///////////////////////////////////////////////////////////////////////
999
1000	r_iss.getRequests(m_ireq, m_dreq);
1001
1002	////////////////////////////////////////////////////////////////////////////////////
1003	// ICACHE_FSM
1004	//
1005	// 1/ Coherence operations
1006	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1007	// - There is a coherence request when r_tgt_icache_req is set.
1008	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
1009	// - There is a cleanup ack request when r_cleanup_icache_req is set.
1010	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
1011	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
1012	// - For both types of requests, actions associated to the pre-empted state
1013	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1014	// or CC_CLACK) to execute the requested coherence operation, and returns
1015	// to the pre-empted state.
1016	//
1017	// 2/ Processor requests
1018	// They are taken in IDLE state only. In case of cache miss, or uncacheable
1019	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
1020	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
1021	// flip-flops are reset when the transaction starts.
1022	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
1023	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
1024	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
1025	// The availability of the missing cache line is signaled by the response fifo,
1026	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
1027	// and ICACHE_MISS_DIR_UPDT states.
1028	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
1029	// to wait the response from the RSP FSM, through the response fifo.
1030	// The missing instruction is directly returned to processor in this state.
1031	//
1032	// 3/ TLB miss
1033	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
1034	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
1035	// register, and goes to the ICACHE_TLB_WAIT state.
1036	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
1037	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
1038	// to signal the completion.
1039	//
1040	// 4/ XTN requests
1041	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1042	// using the r_dcache_xtn_req flip-flop.
1043	// The request opcode and the address to be invalidated are transmitted
1044	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
1045	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1046	// is completed.
1047	//
1048	// 5/ Error Handling
1049	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1050	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1051	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1052	////////////////////////////////////////////////////////////////////////////////////////
1053
1054	// default value for m_irsp
1055	m_irsp.valid = false;
1056	m_irsp.error = false;
1057	m_irsp.instruction = 0;
1058
1059	switch (r_icache_fsm.read())
1060	{
1061	/////////////////
1062	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1063	// and coherence requests with a fixed priority:
1064	// 1/ Coherence requests => ICACHE_CC_CHECK
1065	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1066	// 3/ tlb miss => ICACHE_TLB_WAIT
1067	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1068	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1069	{
1070	// coherence clack interrupt
1071	if (r_icache_clack_req.read())
1072	{
1073	r_icache_fsm = ICACHE_CC_CHECK;
1074	r_icache_fsm_save = r_icache_fsm.read();
1075	break;
1076	}
1077
1078	// coherence interrupt
1079	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1080	{
1081	r_icache_fsm = ICACHE_CC_CHECK;
1082	r_icache_fsm_save = r_icache_fsm.read();
1083	break;
1084	}
1085
1086	// XTN requests sent by DCACHE FSM
1087	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
1088	// because they require access to icache or itlb, that are already accessed
1089	if (r_dcache_xtn_req.read())
1090	{
1091	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
1092	{
1093	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1094	}
1095	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
1096	{
1097	r_icache_flush_count = 0;
1098	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1099	}
1100	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
1101	{
1102	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1103	}
1104	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
1105	{
1106	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1107	}
1108	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
1109	{
1110	if (sizeof(paddr_t) <= 32)
1111	{
1112	assert(r_mmu_word_hi.read() == 0 &&
1113	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1114	r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
1115	}
1116	else
1117	{
1118	r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 \|
1119	(paddr_t) r_mmu_word_lo.read();
1120	}
1121	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1122	}
1123	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
1124	{
1125	r_icache_paddr_ext = r_dcache_save_wdata.read();
1126	r_dcache_xtn_req = false;
1127	}
1128	else
1129	{
1130	assert(false and
1131	"undefined XTN request received by ICACHE FSM");
1132	}
1133	break;
1134	} // end if xtn_req
1135
1136	// processor request
1137	if (m_ireq.valid )
1138	{
1139	bool cacheable;
1140	paddr_t paddr;
1141	bool tlb_hit = false;
1142	pte_info_t tlb_flags;
1143	size_t tlb_way;
1144	size_t tlb_set;
1145	paddr_t tlb_nline;
1146	uint32_t cache_inst = 0;
1147	size_t cache_way;
1148	size_t cache_set;
1149	size_t cache_word;
1150	int cache_state = CACHE_SLOT_STATE_EMPTY;
1151
1152	// We register processor request
1153	r_icache_vaddr_save = m_ireq.addr;
1154	paddr = (paddr_t) m_ireq.addr;
1155
1156	// sytematic itlb access (if activated)
1157	if (r_mmu_mode.read() & INS_TLB_MASK)
1158	{
1159
1160	#ifdef INSTRUMENTATION
1161	m_cpt_itlb_read++;
1162	#endif
1163	tlb_hit = r_itlb.translate(m_ireq.addr,
1164	&paddr,
1165	&tlb_flags,
1166	&tlb_nline, // unused
1167	&tlb_way, // unused
1168	&tlb_set); // unused
1169	}
1170	else if (vci_param::N > 32)
1171	{
1172	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
1173	}
1174
1175	// systematic icache access (if activated)
1176	if (r_mmu_mode.read() & INS_CACHE_MASK)
1177	{
1178
1179
1180	#ifdef INSTRUMENTATION
1181	m_cpt_icache_data_read++;
1182	m_cpt_icache_dir_read++;
1183	#endif
1184	r_icache.read(paddr,
1185	&cache_inst,
1186	&cache_way,
1187	&cache_set,
1188	&cache_word,
1189	&cache_state);
1190	}
1191
1192	// We compute cacheability and check access rights:
1193	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1194	// and the access rights are defined by the U and X bits in the PTE.
1195	// - If MMU not activated : cacheability is defined by the segment table,
1196	// and there is no access rights checking
1197
1198	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
1199	{
1200	// cacheability
1201	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1202	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
1203	}
1204	else // itlb activated
1205	{
1206	if (tlb_hit) // ITLB hit
1207	{
1208	// cacheability
1209	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1210	else cacheable = tlb_flags.c;
1211
1212	// access rights checking
1213	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
1214	{
1215
1216	#if DEBUG_ICACHE
1217	if ( m_debug_icache_fsm )
1218	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
1219	<< " : PADDR = " << std::hex << paddr << std::endl;
1220	#endif
1221	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1222	r_mmu_ibvar = m_ireq.addr;
1223	m_irsp.valid = true;
1224	m_irsp.error = true;
1225	m_irsp.instruction = 0;
1226	break;
1227	}
1228	else if (not tlb_flags.x)
1229	{
1230
1231	#if DEBUG_ICACHE
1232	if ( m_debug_icache_fsm )
1233	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
1234	<< " : PADDR = " << std::hex << paddr << std::endl;
1235	#endif
1236	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1237	r_mmu_ibvar = m_ireq.addr;
1238	m_irsp.valid = true;
1239	m_irsp.error = true;
1240	m_irsp.instruction = 0;
1241	break;
1242	}
1243	}
1244	else // ITLB miss
1245	{
1246
1247	#ifdef INSTRUMENTATION
1248	m_cpt_itlb_miss++;
1249	#endif
1250	r_icache_fsm = ICACHE_TLB_WAIT;
1251	r_icache_tlb_miss_req = true;
1252	break;
1253	}
1254	} // end if itlb activated
1255
1256	// physical address registration
1257	r_icache_vci_paddr = paddr;
1258
1259	// Finally, we send the response to processor, and compute next state
1260	if (cacheable)
1261	{
1262	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1263	{
1264
1265	#ifdef INSTRUMENTATION
1266	m_cpt_icache_miss++;
1267	#endif
1268	// we request a VCI transaction
1269	r_icache_fsm = ICACHE_MISS_SELECT;
1270	#if DEBUG_ICACHE
1271	if (m_debug_icache_fsm)
1272	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1273	<< " : PADDR = " << std::hex << paddr << std::endl;
1274	#endif
1275	r_icache_miss_req = true;
1276	}
1277	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1278	{
1279	// stalled until cleanup is acknowledged
1280	r_icache_fsm = ICACHE_IDLE;
1281	}
1282	else // cache hit
1283	{
1284
1285	#ifdef INSTRUMENTATION
1286	m_cpt_ins_read++;
1287	#endif
1288	// return instruction to processor
1289	m_irsp.valid = true;
1290	m_irsp.instruction = cache_inst;
1291	r_icache_fsm = ICACHE_IDLE;
1292	#if DEBUG_ICACHE
1293	if (m_debug_icache_fsm)
1294	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1295	<< " : PADDR = " << std::hex << paddr
1296	<< " / INST = " << cache_inst << std::endl;
1297	#endif
1298	}
1299	}
1300	else // non cacheable read
1301	{
1302	r_icache_unc_req = true;
1303	r_icache_fsm = ICACHE_UNC_WAIT;
1304
1305	#if DEBUG_ICACHE
1306	if (m_debug_icache_fsm)
1307	{
1308	std::cout << " <PROC " << name()
1309	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1310	<< " : PADDR = " << std::hex << paddr << std::endl;
1311	}
1312	#endif
1313	}
1314	} // end if m_ireq.valid
1315	break;
1316	}
1317	/////////////////////
1318	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1319	// the itlb is udated by the DCACHE FSM, as well as the
1320	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1321	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1322	// reset the r_icache_tlb_miss_req flip-flop
1323	// external coherence request are accepted in this state.
1324	{
1325	// coherence clack interrupt
1326	if (r_icache_clack_req.read())
1327	{
1328	r_icache_fsm = ICACHE_CC_CHECK;
1329	r_icache_fsm_save = r_icache_fsm.read();
1330	break;
1331	}
1332
1333	// coherence interrupt
1334	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1335	{
1336	r_icache_fsm = ICACHE_CC_CHECK;
1337	r_icache_fsm_save = r_icache_fsm.read();
1338	break;
1339	}
1340
1341	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
1342
1343	// DCACHE FSM signals response by reseting the request flip-flop
1344	if (not r_icache_tlb_miss_req.read())
1345	{
1346	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
1347	{
1348	r_icache_tlb_rsp_error = false;
1349	m_irsp.error = true;
1350	m_irsp.valid = true;
1351	r_icache_fsm = ICACHE_IDLE;
1352	}
1353	else // tlb updated : return to IDLE state
1354	{
1355	r_icache_fsm = ICACHE_IDLE;
1356	}
1357	}
1358	break;
1359	}
1360	//////////////////////////
1361	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1362	{
1363	r_itlb.flush();
1364	r_dcache_xtn_req = false;
1365	r_icache_fsm = ICACHE_IDLE;
1366	break;
1367	}
1368	////////////////////////////
1369	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1370	// r_icache_flush_count as a slot counter,
1371	// looping in this state until all slots are visited.
1372	// It can require two cycles per slot:
1373	// We test here the slot state, and make the actual inval
1374	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1375	// A cleanup request is generated for each valid line
1376	{
1377	// coherence clack interrupt
1378	if (r_icache_clack_req.read())
1379	{
1380	r_icache_fsm = ICACHE_CC_CHECK;
1381	r_icache_fsm_save = r_icache_fsm.read();
1382	break;
1383	}
1384
1385	// coherence request (from CC_RECEIVE FSM)
1386	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1387	{
1388	r_icache_fsm = ICACHE_CC_CHECK;
1389	r_icache_fsm_save = r_icache_fsm.read();
1390	break;
1391	}
1392
1393	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
1394	{
1395	int state;
1396	paddr_t tag;
1397	size_t way = r_icache_flush_count.read() / m_icache_sets;
1398	size_t set = r_icache_flush_count.read() % m_icache_sets;
1399
1400	#ifdef INSTRUMENTATION
1401	m_cpt_icache_dir_read++;
1402	#endif
1403	r_icache.read_dir(way,
1404	set,
1405	&tag,
1406	&state);
1407
1408	if (state == CACHE_SLOT_STATE_VALID) // inval required
1409	{
1410	// request cleanup
1411	r_icache_cc_send_req = true;
1412	r_icache_cc_send_nline = tag * m_icache_sets + set;
1413	r_icache_cc_send_way = way;
1414	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1415
1416	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1417	r_icache_miss_way = way;
1418	r_icache_miss_set = set;
1419	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1420	}
1421	else if (r_icache_flush_count.read() ==
1422	(m_icache_sets*m_icache_ways - 1)) // last slot
1423	{
1424	r_dcache_xtn_req = false;
1425	m_drsp.valid = true;
1426	r_icache_fsm = ICACHE_IDLE;
1427	}
1428
1429	// saturation counter, to have the same last slot condition
1430	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1431	if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1))
1432	{
1433	r_icache_flush_count = r_icache_flush_count.read() + 1;
1434	}
1435	}
1436	break;
1437	}
1438	///////////////////////////////
1439	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1440	{
1441	size_t way = r_icache_miss_way.read();
1442	size_t set = r_icache_miss_set.read();
1443
1444	#ifdef INSTRUMENTATION
1445	m_cpt_icache_dir_write++;
1446	#endif
1447
1448	r_icache.write_dir(way,
1449	set,
1450	CACHE_SLOT_STATE_ZOMBI);
1451
1452	if (r_icache_flush_count.read() ==
1453	(m_icache_sets*m_icache_ways - 1)) // last slot
1454	{
1455	r_dcache_xtn_req = false;
1456	m_drsp.valid = true;
1457	r_icache_fsm = ICACHE_IDLE;
1458	}
1459	else
1460	{
1461	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1462	}
1463	break;
1464	}
1465
1466	//////////////////////////
1467	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1468	// stored in the r_dcache_save_wdata register
1469	{
1470	r_itlb.inval(r_dcache_save_wdata.read());
1471	r_dcache_xtn_req = false;
1472	r_icache_fsm = ICACHE_IDLE;
1473	break;
1474	}
1475	///////////////////////////////
1476	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1477	// requires 3 cycles (in case of hit on itlb and icache).
1478	// In this state, access TLB to translate virtual address
1479	// stored in the r_dcache_save_wdata register.
1480	{
1481	paddr_t paddr;
1482	bool hit;
1483
1484	// read physical address in TLB when MMU activated
1485	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
1486	{
1487
1488	#ifdef INSTRUMENTATION
1489	m_cpt_itlb_read++;
1490	#endif
1491	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
1492	}
1493	else // itlb not activated
1494	{
1495	paddr = (paddr_t) r_dcache_save_wdata.read();
1496	hit = true;
1497	}
1498
1499	if (hit) // continue the selective inval process
1500	{
1501	r_icache_vci_paddr = paddr;
1502	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1503	}
1504	else // miss : send a request to DCACHE FSM
1505	{
1506
1507	#ifdef INSTRUMENTATION
1508	m_cpt_itlb_miss++;
1509	#endif
1510	r_icache_tlb_miss_req = true;
1511	r_icache_vaddr_save = r_dcache_save_wdata.read();
1512	r_icache_fsm = ICACHE_TLB_WAIT;
1513	}
1514	break;
1515	}
1516	///////////////////////////////
1517	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1518	// require 2 cycles. In this state, we read directory
1519	// with address stored in r_icache_vci_paddr register.
1520	{
1521	int state;
1522	size_t way;
1523	size_t set;
1524	size_t word;
1525
1526	#ifdef INSTRUMENTATION
1527	m_cpt_icache_dir_read++;
1528	#endif
1529	r_icache.read_dir(r_icache_vci_paddr.read(),
1530	&state,
1531	&way,
1532	&set,
1533	&word);
1534
1535	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
1536	{
1537	r_icache_miss_way = way;
1538	r_icache_miss_set = set;
1539	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1540	}
1541	else // miss : acknowlege the XTN request and return
1542	{
1543	r_dcache_xtn_req = false;
1544	r_icache_fsm = ICACHE_IDLE;
1545	}
1546	break;
1547	}
1548	///////////////////////////////
1549	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1550	{
1551	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
1552	{
1553
1554	#ifdef INSTRUMENTATION
1555	m_cpt_icache_dir_write++;
1556	#endif
1557	r_icache.write_dir(r_icache_miss_way.read(),
1558	r_icache_miss_set.read(),
1559	CACHE_SLOT_STATE_ZOMBI);
1560
1561	// request cleanup
1562	r_icache_cc_send_req = true;
1563	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1564	r_icache_cc_send_way = r_icache_miss_way.read();
1565	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1566
1567	// acknowledge the XTN request and return
1568	r_dcache_xtn_req = false;
1569	r_icache_fsm = ICACHE_IDLE;
1570	}
1571	break;
1572	}
1573	////////////////////////
1574	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1575	// Waiting in this state if no slot available.
1576	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
1577	// we send the cleanup request in this state.
1578	// If not, a r_icache_cleanup_victim_req flip-flop is
1579	// utilized for saving this cleanup request, and it will be sent later
1580	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1581	// The r_icache_miss_clack flip-flop is set
1582	// when a cleanup is required
1583	{
1584	if (m_ireq.valid) m_cost_ins_miss_frz++;
1585
1586	// coherence clack interrupt
1587	if (r_icache_clack_req.read())
1588	{
1589	r_icache_fsm = ICACHE_CC_CHECK;
1590	r_icache_fsm_save = r_icache_fsm.read();
1591	break;
1592	}
1593
1594	// coherence interrupt
1595	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1596	{
1597	r_icache_fsm = ICACHE_CC_CHECK;
1598	r_icache_fsm_save = r_icache_fsm.read();
1599	break;
1600	}
1601
1602
1603	bool found;
1604	bool cleanup;
1605	size_t way;
1606	size_t set;
1607	paddr_t victim;
1608
1609	#ifdef INSTRUMENTATION
1610	m_cpt_icache_dir_read++;
1611	#endif
1612	r_icache.read_select(r_icache_vci_paddr.read(),
1613	&victim,
1614	&way,
1615	&set,
1616	&found,
1617	&cleanup);
1618	if (not found)
1619	{
1620	break;
1621	}
1622	else
1623	{
1624	r_icache_miss_way = way;
1625	r_icache_miss_set = set;
1626
1627	if (cleanup)
1628	{
1629	if (not r_icache_cc_send_req.read())
1630	{
1631	r_icache_cc_send_req = true;
1632	r_icache_cc_send_nline = victim;
1633	r_icache_cc_send_way = way;
1634	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1635	}
1636	else
1637	{
1638	r_icache_cleanup_victim_req = true;
1639	r_icache_cleanup_victim_nline = victim;
1640	}
1641
1642	r_icache_miss_clack = true;
1643	r_icache_fsm = ICACHE_MISS_CLEAN;
1644	}
1645	else
1646	{
1647	r_icache_fsm = ICACHE_MISS_WAIT;
1648	}
1649
1650	#if DEBUG_ICACHE
1651	if (m_debug_icache_fsm)
1652	{
1653	std::cout << " <PROC " << name()
1654	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1655	<< " / WAY = " << way
1656	<< " / SET = " << set;
1657	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1658	else std::cout << std::endl;
1659	}
1660	#endif
1661	}
1662	break;
1663	}
1664	///////////////////////
1665	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1666	{
1667	if (m_ireq.valid) m_cost_ins_miss_frz++;
1668
1669	#ifdef INSTRUMENTATION
1670	m_cpt_icache_dir_write++;
1671	#endif
1672	r_icache.write_dir(r_icache_miss_way.read(),
1673	r_icache_miss_set.read(),
1674	CACHE_SLOT_STATE_ZOMBI);
1675	#if DEBUG_ICACHE
1676	if (m_debug_icache_fsm)
1677	{
1678	std::cout << " <PROC " << name()
1679	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1680	<< " / WAY = " << r_icache_miss_way.read()
1681	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1682	}
1683	#endif
1684
1685	r_icache_fsm = ICACHE_MISS_WAIT;
1686	break;
1687	}
1688	//////////////////////
1689	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1690	{
1691	if (m_ireq.valid) m_cost_ins_miss_frz++;
1692
1693	// send cleanup victim request
1694	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1695	{
1696	r_icache_cc_send_req = true;
1697	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1698	r_icache_cc_send_way = r_icache_miss_way;
1699	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1700	r_icache_cleanup_victim_req = false;
1701	}
1702
1703	// coherence clack interrupt
1704	if (r_icache_clack_req.read())
1705	{
1706	r_icache_fsm = ICACHE_CC_CHECK;
1707	r_icache_fsm_save = r_icache_fsm.read();
1708	break;
1709	}
1710
1711	// coherence interrupt
1712	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1713	{
1714	r_icache_fsm = ICACHE_CC_CHECK;
1715	r_icache_fsm_save = r_icache_fsm.read();
1716	break;
1717	}
1718
1719	if (r_vci_rsp_ins_error.read()) // bus error
1720	{
1721	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1722	r_mmu_ibvar = r_icache_vaddr_save.read();
1723	m_irsp.valid = true;
1724	m_irsp.error = true;
1725	r_vci_rsp_ins_error = false;
1726	r_icache_fsm = ICACHE_IDLE;
1727	}
1728	else if (r_vci_rsp_fifo_icache.rok()) // response available
1729	{
1730	r_icache_miss_word = 0;
1731	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1732	}
1733	break;
1734	}
1735	///////////////////////////
1736	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1737	{
1738	if (m_ireq.valid) m_cost_ins_miss_frz++;
1739
1740	if (r_vci_rsp_fifo_icache.rok()) // response available
1741	{
1742
1743	#ifdef INSTRUMENTATION
1744	m_cpt_icache_data_write++;
1745	#endif
1746	r_icache.write(r_icache_miss_way.read(),
1747	r_icache_miss_set.read(),
1748	r_icache_miss_word.read(),
1749	r_vci_rsp_fifo_icache.read());
1750	#if DEBUG_ICACHE
1751	if (m_debug_icache_fsm)
1752	{
1753	std::cout << " <PROC " << name()
1754	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1755	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1756	<< " WAY = " << r_icache_miss_way.read()
1757	<< " SET = " << r_icache_miss_set.read()
1758	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1759	}
1760	#endif
1761	vci_rsp_fifo_icache_get = true;
1762	r_icache_miss_word = r_icache_miss_word.read() + 1;
1763
1764	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
1765	{
1766	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1767	}
1768	}
1769	break;
1770	}
1771	//////////////////////////
1772	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1773	// and the cleanup ack has not been received,
1774	// as indicated by r_icache_miss_clack.
1775	// - If no matching coherence request (r_icache_miss_inval)
1776	// switch directory slot to VALID state.
1777	// - If matching coherence request, switch directory slot
1778	// to ZOMBI state, and send a cleanup request.
1779	{
1780	if (m_ireq.valid ) m_cost_ins_miss_frz++;
1781
1782	// send cleanup victim request
1783	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1784	{
1785	r_icache_cc_send_req = true;
1786	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1787	r_icache_cc_send_way = r_icache_miss_way;
1788	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1789	r_icache_cleanup_victim_req = false;
1790	}
1791
1792	// coherence clack interrupt
1793	if (r_icache_clack_req.read())
1794	{
1795	r_icache_fsm = ICACHE_CC_CHECK;
1796	r_icache_fsm_save = r_icache_fsm.read();
1797	break;
1798	}
1799
1800	// coherence interrupt
1801	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1802	{
1803	r_icache_fsm = ICACHE_CC_CHECK;
1804	r_icache_fsm_save = r_icache_fsm.read();
1805	break;
1806	}
1807
1808	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
1809	{
1810	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
1811	{
1812	if (not r_icache_cc_send_req.read())
1813	{
1814	r_icache_miss_inval = false;
1815	// request cleanup
1816	r_icache_cc_send_req = true;
1817	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1818	r_icache_cc_send_way = r_icache_miss_way.read();
1819	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1820
1821	#ifdef INSTRUMENTATION
1822	m_cpt_icache_dir_write++;
1823	#endif
1824	r_icache.write_dir(r_icache_vci_paddr.read(),
1825	r_icache_miss_way.read(),
1826	r_icache_miss_set.read(),
1827	CACHE_SLOT_STATE_ZOMBI);
1828	#if DEBUG_ICACHE
1829	if (m_debug_icache_fsm)
1830	{
1831	std::cout << " <PROC " << name()
1832	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1833	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1834	<< " WAY = " << std::dec << r_icache_miss_way.read()
1835	<< " SET = " << r_icache_miss_set.read() << std::endl;
1836	}
1837	#endif
1838	}
1839	else
1840	break;
1841	}
1842	else // Switch slot to VALID state
1843	{
1844
1845	#ifdef INSTRUMENTATION
1846	m_cpt_icache_dir_write++;
1847	#endif
1848	r_icache.write_dir(r_icache_vci_paddr.read(),
1849	r_icache_miss_way.read(),
1850	r_icache_miss_set.read(),
1851	CACHE_SLOT_STATE_VALID);
1852	#if DEBUG_ICACHE
1853	if (m_debug_icache_fsm)
1854	{
1855	std::cout << " <PROC " << name()
1856	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1857	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1858	<< " WAY = " << std::dec << r_icache_miss_way.read()
1859	<< " SET = " << r_icache_miss_set.read() << std::endl;
1860	}
1861	#endif
1862	}
1863
1864	r_icache_fsm = ICACHE_IDLE;
1865	}
1866	break;
1867	}
1868	////////////////////
1869	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1870	{
1871	// coherence clack interrupt
1872	if (r_icache_clack_req.read())
1873	{
1874	r_icache_fsm = ICACHE_CC_CHECK;
1875	r_icache_fsm_save = r_icache_fsm.read();
1876	break;
1877	}
1878
1879	// coherence interrupt
1880	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1881	{
1882	r_icache_fsm = ICACHE_CC_CHECK;
1883	r_icache_fsm_save = r_icache_fsm.read();
1884	break;
1885	}
1886
1887	if (r_vci_rsp_ins_error.read()) // bus error
1888	{
1889	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1890	r_mmu_ibvar = m_ireq.addr;
1891	r_vci_rsp_ins_error = false;
1892	m_irsp.valid = true;
1893	m_irsp.error = true;
1894	r_icache_fsm = ICACHE_IDLE;
1895	}
1896	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
1897	{
1898	vci_rsp_fifo_icache_get = true;
1899	r_icache_fsm = ICACHE_IDLE;
1900	if (m_ireq.valid and
1901	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
1902	{
1903	m_irsp.valid = true;
1904	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1905	}
1906	}
1907	break;
1908	}
1909	/////////////////////
1910	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1911	// handling coherence requests.
1912	// if there is a matching pending miss, it is
1913	// signaled in the r_icache_miss_inval flip-flop.
1914	// The return state is defined in r_icache_fsm_save.
1915	{
1916	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1917	paddr_t mask = ~((m_icache_words << 2) - 1);
1918
1919	// CLACK handler
1920	// We switch the directory slot to EMPTY state
1921	// and reset r_icache_miss_clack if the cleanup ack
1922	// is matching a pending miss.
1923	if (r_icache_clack_req.read())
1924	{
1925
1926	if (m_ireq.valid) m_cost_ins_miss_frz++;
1927
1928	#ifdef INSTRUMENTATION
1929	m_cpt_icache_dir_write++;
1930	#endif
1931	r_icache.write_dir(0,
1932	r_icache_clack_way.read(),
1933	r_icache_clack_set.read(),
1934	CACHE_SLOT_STATE_EMPTY);
1935
1936	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
1937	(r_icache_miss_way.read() == r_icache_clack_way.read()))
1938	{
1939	r_icache_miss_clack = false;
1940	}
1941
1942	r_icache_clack_req = false;
1943
1944	// return to cc_save state
1945	r_icache_fsm = r_icache_fsm_save.read();
1946
1947	#if DEBUG_ICACHE
1948	if (m_debug_icache_fsm)
1949	{
1950	std::cout << " <PROC " << name()
1951	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1952	<< " set = " << r_icache_clack_set.read()
1953	<< " / way = " << r_icache_clack_way.read() << std::endl;
1954	}
1955	#endif
1956
1957	break;
1958	}
1959
1960	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
1961
1962	// Match between MISS address and CC address
1963	if (r_cc_receive_icache_req.read() and
1964	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1965	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1966	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1967	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
1968	{
1969	// signaling the matching
1970	r_icache_miss_inval = true;
1971
1972	// in case of update, go to CC_UPDT
1973	// JUST TO POP THE FIFO
1974	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1975	{
1976	r_icache_fsm = ICACHE_CC_UPDT;
1977	r_icache_cc_word = r_cc_receive_word_idx.read();
1978
1979	// just pop the fifo , don't write in icache
1980	r_icache_cc_need_write = false;
1981	}
1982	// the request is dealt with
1983	else
1984	{
1985	r_cc_receive_icache_req = false;
1986	r_icache_fsm = r_icache_fsm_save.read();
1987	}
1988	#if DEBUG_ICACHE
1989	if (m_debug_icache_fsm)
1990	{
1991	std::cout << " <PROC " << name()
1992	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1993	<< " PADDR = " << std::hex << paddr << std::endl;
1994	}
1995	#endif
1996	}
1997
1998	// CC request handler
1999
2000	int state = 0;
2001	size_t way = 0;
2002	size_t set = 0;
2003	size_t word = 0;
2004
2005	#ifdef INSTRUMENTATION
2006	m_cpt_icache_dir_read++;
2007	#endif
2008	r_icache.read_dir(paddr,
2009	&state,
2010	&way,
2011	&set,
2012	&word);
2013
2014	r_icache_cc_way = way;
2015	r_icache_cc_set = set;
2016
2017	if (state == CACHE_SLOT_STATE_VALID) // hit
2018	{
2019	// need to update the cache state
2020	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
2021	{
2022	r_icache_cc_need_write = true;
2023	r_icache_fsm = ICACHE_CC_UPDT;
2024	r_icache_cc_word = r_cc_receive_word_idx.read();
2025	}
2026	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
2027	{
2028	r_icache_fsm = ICACHE_CC_INVAL;
2029	}
2030	}
2031	else // miss
2032	{
2033	// multicast acknowledgement required in case of update
2034	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
2035	{
2036	r_icache_fsm = ICACHE_CC_UPDT;
2037	r_icache_cc_word = r_cc_receive_word_idx.read();
2038
2039	// just pop the fifo , don't write in icache
2040	r_icache_cc_need_write = false;
2041	}
2042	else // No response needed
2043	{
2044	r_cc_receive_icache_req = false;
2045	r_icache_fsm = r_icache_fsm_save.read();
2046	}
2047	}
2048	break;
2049	}
2050	/////////////////////
2051	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
2052	{
2053	assert (not r_icache_cc_send_req.read() &&
2054	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
2055	"must not be set");
2056
2057	#ifdef INSTRUMENTATION
2058	m_cpt_icache_dir_read++;
2059	#endif
2060
2061	// Switch slot state to ZOMBI and send CLEANUP command
2062	r_icache.write_dir(r_icache_cc_way.read(),
2063	r_icache_cc_set.read(),
2064	CACHE_SLOT_STATE_ZOMBI);
2065
2066	// coherence request completed
2067	r_icache_cc_send_req = true;
2068	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2069	r_icache_cc_send_way = r_icache_cc_way.read();
2070	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2071
2072	r_icache_fsm = r_icache_fsm_save.read();
2073
2074	#if DEBUG_ICACHE
2075	if (m_debug_icache_fsm)
2076	{
2077	std::cout << " <PROC " << name()
2078	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
2079	<< " set = " << r_icache_cc_set.read()
2080	<< " / way = " << r_icache_cc_way.read() << std::endl;
2081	}
2082	#endif
2083
2084	break;
2085	}
2086	////////////////////
2087	case ICACHE_CC_UPDT: // hit update : write one word per cycle
2088	{
2089	assert (not r_icache_cc_send_req.read() &&
2090	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
2091	"must not be set");
2092
2093	if (not r_cc_receive_updt_fifo_be.rok()) break;
2094
2095
2096	size_t word = r_icache_cc_word.read();
2097	size_t way = r_icache_cc_way.read();
2098	size_t set = r_icache_cc_set.read();
2099
2100	if (r_icache_cc_need_write.read())
2101	{
2102	r_icache.write(way,
2103	set,
2104	word,
2105	r_cc_receive_updt_fifo_data.read(),
2106	r_cc_receive_updt_fifo_be.read());
2107
2108	r_icache_cc_word = word + 1;
2109
2110	#ifdef INSTRUMENTATION
2111	m_cpt_icache_data_write++;
2112	#endif
2113
2114	#if DEBUG_ICACHE
2115	if (m_debug_icache_fsm)
2116	{
2117	std::cout << " <PROC " << name()
2118	<< " ICACHE_CC_UPDT> Write one word "
2119	<< " set = " << r_icache_cc_set.read()
2120	<< " / way = " << r_icache_cc_way.read()
2121	<< " / word = " << r_icache_cc_word.read() << std::endl;
2122	}
2123	#endif
2124	}
2125
2126	if (r_cc_receive_updt_fifo_eop.read()) // last word
2127	{
2128	// no need to write in the cache anymore
2129	r_icache_cc_need_write = false;
2130
2131	// coherence request completed
2132	r_cc_receive_icache_req = false;
2133
2134	// request multicast acknowledgement
2135	r_icache_cc_send_req = true;
2136	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2137	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2138	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2139
2140	r_icache_fsm = r_icache_fsm_save.read();
2141	}
2142	//consume fifo if not eop
2143	cc_receive_updt_fifo_get = true;
2144
2145	break;
2146	}
2147
2148	} // end switch r_icache_fsm
2149
2150	////////////////////////////////////////////////////////////////////////////////////
2151	// DCACHE FSM
2152	//
2153	// 1/ Coherence operations
2154	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2155	// - There is a coherence request when r_tgt_dcache_req is set.
2156	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2157	// and SC_WAIT states.
2158	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2159	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2160	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2161	// - For both types of requests, actions associated to the pre-empted state
2162	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2163	// or CC_CLACK) to execute the requested coherence operation, and returns
2164	// to the pre-empted state.
2165	//
2166	// 2/ TLB miss
2167	// The page tables are generally cacheable.
2168	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2169	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2170	// this sub-fsm implement the table-walk...
2171	//
2172	// 3/ processor requests
2173	// Processor requests are taken in IDLE state only.
2174	// The IDLE state implements a two stages pipe-line to handle write bursts:
2175	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2176	// - The registration in wbuf and the dcache update is done in stage P1
2177	// (if the processor request is a write).
2178	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2179	// the operations that must be done in P1 stage, and the access type
2180	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2181	// READ requests are delayed if a cache update is requested.
2182	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2183	// that is done (before handling the processor request) by a dedicated sub-fsm.
2184	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2185	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2186	//
2187	// 4/ Atomic instructions LL/SC
2188	// The LL/SC address are non cacheable (systematic access to memory).
2189	// The llsc buffer contains a registration for an active LL/SC operation
2190	// (with an address, a registration key, an aging counter and a valid bit).
2191	// - LL requests from the processor are transmitted as a one flit VCI command
2192	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2193	// be 8 as the response is 2 flits long (data and registration key)
2194	// - SC requests from the processor are systematically transmitted to the
2195	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2196	// as PKTID value). The first flit contains the registration key, the second
2197	// flit contains the data to write in case of success.
2198	// The cache is not updated, as this is done in case of success by the
2199	// coherence transaction.
2200	//
2201	// 5/ Non cacheable access:
2202	// This component implement a strong order between non cacheable access
2203	// (read or write) : A new non cacheable VCI transaction starts only when
2204	// the previous non cacheable transaction is completed. After send the VCI
2205	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
2206	// So the processor is blocked until the respone arrives in CACHE L1.
2207	//
2208	// 6/ Error handling:
2209	// When the MMU is not activated, Read Bus Errors are synchronous events,
2210	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
2211	// but some Write Bus Errors are asynchronous events when the request is cacheable access
2212	// (processor is not frozen).
2213	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
2214	// r_vci_rsp_data_error flip-flop, without writing any data in the
2215	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2216	// by the DCACHE FSM.
2217	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
2218	// the asynchronous error using the setWriteBerr() method.
2219	// When the MMU is activated bus error are rare events, as the MMU
2220	// checks the physical address before the VCI transaction starts.
2221	////////////////////////////////////////////////////////////////////////////////////////
2222
2223	// default value for m_drsp
2224	m_drsp.valid = false;
2225	m_drsp.error = false;
2226	m_drsp.rdata = 0;
2227
2228	switch (r_dcache_fsm.read())
2229	{
2230	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2231	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2232	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2233	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2234	// 4) XTN request (processor) => DCACHE_XTN_*
2235	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2236	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2237	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2238	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
2239	// 9) LL access (processor) => DCACHE_LL_WAIT
2240	// 10) SC access (processor) => DCACHE_SC_WAIT
2241	//
2242	// There is a fixed priority to handle requests to DCACHE:
2243	// 1/ the ITLB/DTLB invalidate requests
2244	// 2/ the coherence requests,
2245	// 3/ the processor requests (including DTLB miss),
2246	// 4/ the ITLB miss requests,
2247	// The address space processor request are handled as follows:
2248	// - WRITE request is blocked if the Dirty bit mus be set.
2249	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2250	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2251	// - READ request generate a simultaneouss access to DCACHE.DATA
2252	// and DCACHE.DIR, but is delayed if DCACHE update required.
2253	//
2254	// There is 4 configurations defining the access type to
2255	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2256	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2257	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2258	// 0 / 0 / NOP / NOP / NOP /
2259	// 0 / 1 / NOP / NOP / WRITE /
2260	// 1 / 0 / READ / READ / NOP /
2261	// 1 / 1 / READ / READ / WRITE /
2262	// Those two registers are set at each cycle from the 3 signals
2263	// updt_request, wbuf_request, wbuf_write_miss.
2264	{
2265	paddr_t paddr;
2266	pte_info_t tlb_flags;
2267	size_t tlb_way;
2268	size_t tlb_set;
2269	paddr_t tlb_nline = 0;
2270	size_t cache_way;
2271	size_t cache_set;
2272	size_t cache_word;
2273	uint32_t cache_rdata = 0;
2274	bool tlb_hit = false;
2275	int cache_state = CACHE_SLOT_STATE_EMPTY;
2276
2277	bool tlb_inval_required = false; // request TLB inval after cache update
2278	bool wbuf_write_miss = false; // miss a WBUF write request
2279	bool updt_request = false; // request DCACHE update in P1 stage
2280	bool wbuf_request = false; // request WBUF write in P1 stage
2281
2282	// physical address computation : systematic DTLB access if activated
2283	paddr = (paddr_t) m_dreq.addr;
2284	if (m_dreq.valid)
2285	{
2286	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
2287	{
2288	tlb_hit = r_dtlb.translate(m_dreq.addr,
2289	&paddr,
2290	&tlb_flags,
2291	&tlb_nline,
2292	&tlb_way,
2293	&tlb_set);
2294	#ifdef INSTRUMENTATION
2295	m_cpt_dtlb_read++;
2296	#endif
2297	}
2298	else // identity mapping
2299	{
2300	// we take into account the paddr extension
2301	if (vci_param::N > 32)
2302	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
2303	}
2304	} // end physical address computation
2305
2306	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2307	if (r_mmu_mode.read() & DATA_CACHE_MASK)
2308	{
2309
2310	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
2311	{
2312	r_dcache.read_dir(paddr,
2313	&cache_state,
2314	&cache_way,
2315	&cache_set,
2316	&cache_word);
2317
2318	r_dcache.write(r_dcache_save_cache_way.read(),
2319	r_dcache_save_cache_set.read(),
2320	r_dcache_save_cache_word.read(),
2321	r_dcache_save_wdata.read(),
2322	r_dcache_save_be.read());
2323	#ifdef INSTRUMENTATION
2324	m_cpt_dcache_dir_read++;
2325	m_cpt_dcache_data_write++;
2326	#endif
2327	}
2328	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
2329	{
2330	r_dcache.read(paddr,
2331	&cache_rdata,
2332	&cache_way,
2333	&cache_set,
2334	&cache_word,
2335	&cache_state);
2336
2337	#ifdef INSTRUMENTATION
2338	m_cpt_dcache_dir_read++;
2339	m_cpt_dcache_data_read++;
2340	#endif
2341	}
2342	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
2343	{
2344	r_dcache.write(r_dcache_save_cache_way.read(),
2345	r_dcache_save_cache_set.read(),
2346	r_dcache_save_cache_word.read(),
2347	r_dcache_save_wdata.read(),
2348	r_dcache_save_be.read());
2349	#ifdef INSTRUMENTATION
2350	m_cpt_dcache_data_write++;
2351	#endif
2352	}
2353	} // end dcache access
2354
2355	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2356	if (r_dcache_updt_req.read())
2357	{
2358	size_t way = r_dcache_save_cache_way.read();
2359	size_t set = r_dcache_save_cache_set.read();
2360
2361	if (r_dcache_in_tlb[way * m_dcache_sets + set])
2362	{
2363	tlb_inval_required = true;
2364	r_dcache_tlb_inval_set = 0;
2365	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
2366	(uint32_log2(m_dcache_words << 2));
2367	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
2368	}
2369	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
2370	{
2371	r_itlb.reset();
2372	r_dtlb.reset();
2373	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
2374	}
2375
2376	#if DEBUG_DCACHE
2377	if (m_debug_dcache_fsm)
2378	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2379	<< " Cache update in P1 stage" << std::dec
2380	<< " / WAY = " << r_dcache_save_cache_way.read()
2381	<< " / SET = " << r_dcache_save_cache_set.read()
2382	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2383	<< " / WDATA = " << r_dcache_save_wdata.read()
2384	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2385	#endif
2386	} // end test TLB inval
2387
2388	// Try WBUF update in P1 stage
2389	// Miss if the write request is non cacheable, and there is a pending
2390	// non cacheable write, or if the write buffer is full.
2391	if (r_dcache_wbuf_req.read())
2392	{
2393	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
2394	r_dcache_save_be.read(),
2395	r_dcache_save_wdata.read(),
2396	true);
2397	#ifdef INSTRUMENTATION
2398	m_cpt_wbuf_write++;
2399	#endif
2400	if (not wok ) // miss if write buffer full
2401	{
2402	wbuf_write_miss = true;
2403	}
2404	} // end WBUF update
2405
2406	// Computing the response to processor,
2407	// and the next value for r_dcache_fsm
2408
2409	// itlb/dtlb invalidation self-request
2410	if (tlb_inval_required)
2411	{
2412	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2413	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2414	}
2415
2416	// coherence clack request (from DSPIN CLACK)
2417	else if (r_dcache_clack_req.read())
2418	{
2419	r_dcache_fsm = DCACHE_CC_CHECK;
2420	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2421	}
2422	// coherence request (from CC_RECEIVE FSM)
2423	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
2424	{
2425	r_dcache_fsm = DCACHE_CC_CHECK;
2426	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2427	}
2428
2429	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2430	// we don't take the processor request, and registers
2431	// are frozen in case of wbuf_write_miss
2432	else if (m_dreq.valid and not wbuf_write_miss)
2433	{
2434	// register processor request and DCACHE response
2435	r_dcache_save_vaddr = m_dreq.addr;
2436	r_dcache_save_be = m_dreq.be;
2437	r_dcache_save_wdata = m_dreq.wdata;
2438	r_dcache_save_paddr = paddr;
2439	r_dcache_save_cache_way = cache_way;
2440	r_dcache_save_cache_set = cache_set;
2441	r_dcache_save_cache_word = cache_word;
2442
2443	// READ XTN requests from processor
2444	// They are executed in this DCACHE_IDLE state.
2445	// The processor must not be in user mode
2446	if (m_dreq.type == iss_t::XTN_READ)
2447	{
2448	int xtn_opcode = (int) m_dreq.addr / 4;
2449
2450	// checking processor mode:
2451	if (m_dreq.mode == iss_t::MODE_USER)
2452	{
2453	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2454	r_mmu_dbvar = m_dreq.addr;
2455	m_drsp.valid = true;
2456	m_drsp.error = true;
2457	m_drsp.rdata = 0;
2458	r_dcache_fsm = DCACHE_IDLE;
2459	}
2460	else
2461	{
2462	switch (xtn_opcode)
2463	{
2464	case iss_t::XTN_INS_ERROR_TYPE:
2465	m_drsp.rdata = r_mmu_ietr.read();
2466	m_drsp.valid = true;
2467	m_drsp.error = false;
2468	break;
2469
2470	case iss_t::XTN_DATA_ERROR_TYPE:
2471	m_drsp.rdata = r_mmu_detr.read();
2472	m_drsp.valid = true;
2473	m_drsp.error = false;
2474	break;
2475
2476	case iss_t::XTN_INS_BAD_VADDR:
2477	m_drsp.rdata = r_mmu_ibvar.read();
2478	m_drsp.valid = true;
2479	m_drsp.error = false;
2480	break;
2481
2482	case iss_t::XTN_DATA_BAD_VADDR:
2483	m_drsp.rdata = r_mmu_dbvar.read();
2484	m_drsp.valid = true;
2485	m_drsp.error = false;
2486	break;
2487
2488	case iss_t::XTN_PTPR:
2489	m_drsp.rdata = r_mmu_ptpr.read();
2490	m_drsp.valid = true;
2491	m_drsp.error = false;
2492	break;
2493
2494	case iss_t::XTN_TLB_MODE:
2495	m_drsp.rdata = r_mmu_mode.read();
2496	m_drsp.valid = true;
2497	m_drsp.error = false;
2498	break;
2499
2500	case iss_t::XTN_MMU_PARAMS:
2501	m_drsp.rdata = r_mmu_params;
2502	m_drsp.valid = true;
2503	m_drsp.error = false;
2504	break;
2505
2506	case iss_t::XTN_MMU_RELEASE:
2507	m_drsp.rdata = r_mmu_release;
2508	m_drsp.valid = true;
2509	m_drsp.error = false;
2510	break;
2511
2512	case iss_t::XTN_MMU_WORD_LO:
2513	m_drsp.rdata = r_mmu_word_lo.read();
2514	m_drsp.valid = true;
2515	m_drsp.error = false;
2516	break;
2517
2518	case iss_t::XTN_MMU_WORD_HI:
2519	m_drsp.rdata = r_mmu_word_hi.read();
2520	m_drsp.valid = true;
2521	m_drsp.error = false;
2522	break;
2523
2524	case iss_t::XTN_DATA_PADDR_EXT:
2525	m_drsp.rdata = r_dcache_paddr_ext.read();
2526	m_drsp.valid = true;
2527	m_drsp.error = false;
2528	break;
2529
2530	case iss_t::XTN_INST_PADDR_EXT:
2531	m_drsp.rdata = r_icache_paddr_ext.read();
2532	m_drsp.valid = true;
2533	m_drsp.error = false;
2534	break;
2535
2536	case XTN_WDT_MAX:
2537	m_drsp.rdata = r_dcache_miss_wdt_max.read();
2538	m_drsp.valid = true;
2539	m_drsp.error = false;
2540	break;
2541
2542	default:
2543	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2544	r_mmu_dbvar = m_dreq.addr;
2545	m_drsp.valid = true;
2546	m_drsp.error = true;
2547	m_drsp.rdata = 0;
2548	break;
2549	} // end switch xtn_opcode
2550	} // end else
2551	} // end if XTN_READ
2552
2553	// Handling WRITE XTN requests from processor.
2554	// They are not executed in this DCACHE_IDLE state
2555	// if they require access to the caches or the TLBs
2556	// that are already accessed.
2557	// Caches can be invalidated or flushed in user mode,
2558	// and the sync instruction can be executed in user mode
2559	else if (m_dreq.type == iss_t::XTN_WRITE)
2560	{
2561	int xtn_opcode = (int)m_dreq.addr / 4;
2562	r_dcache_xtn_opcode = xtn_opcode;
2563
2564	// checking processor mode:
2565	if ((m_dreq.mode == iss_t::MODE_USER) &&
2566	(xtn_opcode != iss_t::XTN_SYNC) &&
2567	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2568	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2569	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2570	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
2571	{
2572	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2573	r_mmu_dbvar = m_dreq.addr;
2574	m_drsp.valid = true;
2575	m_drsp.error = true;
2576	m_drsp.rdata = 0;
2577	r_dcache_fsm = DCACHE_IDLE;
2578	}
2579	else
2580	{
2581	switch (xtn_opcode)
2582	{
2583	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2584	r_dcache_xtn_req = true;
2585	r_dcache_fsm = DCACHE_XTN_SWITCH;
2586	break;
2587
2588	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2589	r_mmu_mode = m_dreq.wdata;
2590	m_drsp.valid = true;
2591	r_dcache_fsm = DCACHE_IDLE;
2592	break;
2593
2594	case iss_t::XTN_DTLB_INVAL: // dtlb access
2595	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2596	break;
2597
2598	case iss_t::XTN_ITLB_INVAL: // itlb access
2599	r_dcache_xtn_req = true;
2600	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2601	break;
2602
2603	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2604	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2605	break;
2606
2607	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2608	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2609	if (sizeof(paddr_t) <= 32)
2610	{
2611	assert(r_mmu_word_hi.read() == 0 &&
2612	"high bits should be 0 for 32bit paddr");
2613	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2614	}
2615	else
2616	{
2617	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2618	(paddr_t)r_mmu_word_lo.read();
2619	}
2620	break;
2621
2622	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2623	r_dcache_flush_count = 0;
2624	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2625	break;
2626
2627	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2628	r_dcache_xtn_req = true;
2629	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2630	break;
2631
2632	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2633	r_dcache_xtn_req = true;
2634	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2635	break;
2636
2637	case iss_t::XTN_ICACHE_FLUSH: // icache access
2638	r_dcache_xtn_req = true;
2639	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2640	break;
2641
2642	case iss_t::XTN_SYNC: // wait until write buffer empty
2643	r_dcache_fsm = DCACHE_XTN_SYNC;
2644	break;
2645
2646	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2647	r_mmu_word_lo = m_dreq.wdata;
2648	m_drsp.valid = true;
2649	r_dcache_fsm = DCACHE_IDLE;
2650	break;
2651
2652	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2653	r_mmu_word_hi = m_dreq.wdata;
2654	m_drsp.valid = true;
2655	r_dcache_fsm = DCACHE_IDLE;
2656	break;
2657
2658	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2659	r_dcache_llsc_valid = false;
2660	m_drsp.valid = true;
2661	r_dcache_fsm = DCACHE_IDLE;
2662	break;
2663
2664	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2665	r_dcache_paddr_ext = m_dreq.wdata;
2666	m_drsp.valid = true;
2667	r_dcache_fsm = DCACHE_IDLE;
2668	break;
2669
2670	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
2671	r_dcache_xtn_req = true;
2672	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
2673	break;
2674
2675	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2676	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2677	m_drsp.valid = true;
2678	r_dcache_fsm = DCACHE_IDLE;
2679	break;
2680
2681	case XTN_WDT_MAX:
2682	r_dcache_miss_wdt_max = m_dreq.wdata;
2683	m_drsp.valid = true;
2684	r_dcache_fsm = DCACHE_IDLE;
2685	break;
2686
2687	case iss_t::XTN_DEBUG_MASK: // debug mask
2688	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2689	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2690	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2691	m_drsp.valid = true;
2692	r_dcache_fsm = DCACHE_IDLE;
2693	break;
2694
2695	default:
2696	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2697	r_mmu_dbvar = m_dreq.addr;
2698	m_drsp.valid = true;
2699	m_drsp.error = true;
2700	r_dcache_fsm = DCACHE_IDLE;
2701	break;
2702	} // end switch xtn_opcode
2703	} // end else
2704	} // end if XTN_WRITE
2705
2706	// Handling processor requests to address space (READ/WRITE/LL/SC)
2707	// The dtlb and dcache can be activated or not.
2708	// We compute the cacheability, and check processor request validity:
2709	// - If DTLB not activated : cacheability is defined by the segment table,
2710	// and there is no access rights checking.
2711	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2712	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2713	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2714	else
2715	{
2716	bool valid_req;
2717	bool cacheable;
2718
2719	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
2720	{
2721	valid_req = true;
2722
2723	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2724	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
2725	}
2726	else // dtlb activated
2727	{
2728	if (tlb_hit) // tlb hit
2729	{
2730	// cacheability
2731	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2732	else cacheable = tlb_flags.c;
2733
2734	// access rights checking
2735	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2736	{
2737	if ((m_dreq.type == iss_t::DATA_READ) or
2738	(m_dreq.type == iss_t::DATA_LL))
2739	{
2740	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2741	}
2742	else
2743	{
2744	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2745	}
2746	valid_req = false;
2747	r_mmu_dbvar = m_dreq.addr;
2748	m_drsp.valid = true;
2749	m_drsp.error = true;
2750	m_drsp.rdata = 0;
2751	#if DEBUG_DCACHE
2752	if (m_debug_dcache_fsm)
2753	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2754	<< " HIT in dtlb, but privilege violation" << std::endl;
2755	#endif
2756	}
2757	else if (not tlb_flags.w and
2758	((m_dreq.type == iss_t::DATA_WRITE) or
2759	(m_dreq.type == iss_t::DATA_SC)))
2760	{
2761	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2762	valid_req = false;
2763	r_mmu_dbvar = m_dreq.addr;
2764	m_drsp.valid = true;
2765	m_drsp.error = true;
2766	m_drsp.rdata = 0;
2767	#if DEBUG_DCACHE
2768	if (m_debug_dcache_fsm)
2769	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2770	<< " HIT in dtlb, but writable violation" << std::endl;
2771	#endif
2772	}
2773	else
2774	{
2775	valid_req = true;
2776	}
2777	}
2778	else // tlb miss
2779	{
2780	valid_req = false;
2781	r_dcache_tlb_vaddr = m_dreq.addr;
2782	r_dcache_tlb_ins = false;
2783	r_dcache_fsm = DCACHE_TLB_MISS;
2784	}
2785	} // end DTLB activated
2786
2787	if (valid_req) // processor request is valid (after MMU check)
2788	{
2789	// READ request
2790	// The read requests are taken only if there is no cache update.
2791	// We request a VCI transaction to CMD FSM if miss or uncachable
2792
2793	if (((m_dreq.type == iss_t::DATA_READ))
2794	and not r_dcache_updt_req.read())
2795	{
2796	if (cacheable) // cacheable read
2797	{
2798	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
2799	{
2800	#ifdef INSTRUMENTATION
2801	m_cpt_dcache_miss++;
2802	#endif
2803	// request a VCI DMISS transaction
2804	r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
2805
2806	r_dcache_vci_paddr = paddr;
2807	r_dcache_vci_miss_req = true;
2808	r_dcache_miss_type = PROC_MISS;
2809	r_dcache_fsm = DCACHE_MISS_SELECT;
2810	#if DEBUG_DCACHE
2811	if (m_debug_dcache_fsm)
2812	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2813	<< " READ MISS in dcache"
2814	<< " / PADDR = " << std::hex << paddr << std::endl;
2815	#endif
2816	}
2817	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
2818	{
2819	// stalled until cleanup is acknowledged
2820	r_dcache_fsm = DCACHE_IDLE;
2821	#if DEBUG_DCACHE
2822	if (m_debug_dcache_fsm)
2823	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2824	<< " Pending cleanup, stalled until cleanup acknowledge"
2825	<< " / PADDR = " << std::hex << paddr << std::endl;
2826	#endif
2827	}
2828	else // cache hit
2829	{
2830	#ifdef INSTRUMENTATION
2831	m_cpt_data_read++;
2832	#endif
2833	// returns data to processor
2834	m_drsp.valid = true;
2835	m_drsp.error = false;
2836	m_drsp.rdata = cache_rdata;
2837	#if DEBUG_DCACHE
2838	if (m_debug_dcache_fsm)
2839	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2840	<< " READ HIT in dcache"
2841	<< " : PADDR = " << std::hex << paddr
2842	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2843	#endif
2844	}
2845	}
2846	else // uncacheable read
2847	{
2848	r_dcache_vci_paddr = paddr;
2849	r_dcache_vci_unc_be = m_dreq.be;
2850	r_dcache_vci_unc_write = false;
2851	r_dcache_vci_unc_req = true;
2852	r_dcache_fsm = DCACHE_UNC_WAIT;
2853	#if DEBUG_DCACHE
2854	if (m_debug_dcache_fsm)
2855	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2856	<< " READ UNCACHEABLE in dcache"
2857	<< " / PADDR = " << std::hex << paddr << std::endl;
2858	#endif
2859	}
2860	} // end READ
2861
2862	// LL request (non cachable)
2863	// We request a VCI LL transaction to CMD FSM and register
2864	// the LL/SC operation in llsc buffer.
2865	else if (m_dreq.type == iss_t::DATA_LL)
2866	{
2867	// register paddr in LLSC buffer
2868	r_dcache_llsc_paddr = paddr;
2869	r_dcache_llsc_count = LLSC_TIMEOUT;
2870	r_dcache_llsc_valid = true;
2871
2872	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2873	r_dcache_vci_ll_req = true;
2874	r_dcache_vci_paddr = paddr;
2875	r_dcache_ll_rsp_count = 0;
2876	r_dcache_fsm = DCACHE_LL_WAIT;
2877
2878	}// end LL
2879
2880	// WRITE request:
2881	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2882	// the processor and set the Dirty bit before handling the write request,
2883	// going to the DCACHE_DIRTY_GT_PTE state.
2884	// If we don't need to set the Dirty bit, we can acknowledge
2885	// the processor request, as the write arguments (including the
2886	// physical address) are registered in r_dcache_save registers,
2887	// and the write will be done in the P1 pipeline stage.
2888	else if (m_dreq.type == iss_t::DATA_WRITE)
2889	{
2890	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2891	and not tlb_flags.d) // Dirty bit must be set
2892	{
2893	// The PTE physical address is obtained from the nline value (dtlb),
2894	// and from the virtual address (word index)
2895	if (tlb_flags.b ) // PTE1
2896	{
2897	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
2898	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
2899	}
2900	else // PTE2
2901	{
2902	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2903	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2904	}
2905	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2906	}
2907	else // Write request accepted
2908	{
2909	#ifdef INSTRUMENTATION
2910	m_cpt_data_write++;
2911	#endif
2912	// cleaning llsc buffer if address matching
2913	if (paddr == r_dcache_llsc_paddr.read())
2914	r_dcache_llsc_valid = false;
2915
2916	if (not cacheable) // uncacheable write
2917	{
2918	r_dcache_vci_paddr = paddr;
2919	r_dcache_vci_wdata = m_dreq.wdata;
2920	r_dcache_vci_unc_write = true;
2921	r_dcache_vci_unc_be = m_dreq.be;
2922	r_dcache_vci_unc_req = true;
2923	r_dcache_fsm = DCACHE_UNC_WAIT;
2924	}
2925	else
2926	{
2927	// response to processor
2928	m_drsp.valid = true;
2929	// activating P1 stage
2930	wbuf_request = true;
2931	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2932	}
2933	}
2934	} // end WRITE
2935
2936	// SC request:
2937	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2938	// the processor and set the Dirty bit before handling the write request,
2939	// going to the DCACHE_DIRTY_GT_PTE state.
2940	// If we don't need to set the Dirty bit, we test the llsc buffer:
2941	// If failure, we send a negative response to processor.
2942	// If success, we request a SC transaction to CMD FSM and go
2943	// to DCACHE_SC_WAIT state.
2944	// We don't check a possible write hit in dcache, as the cache update
2945	// is done by the coherence transaction induced by the SC...
2946	else if (m_dreq.type == iss_t::DATA_SC)
2947	{
2948	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2949	and not tlb_flags.d) // Dirty bit must be set
2950	{
2951	// The PTE physical address is obtained from the nline value (dtlb),
2952	// and the word index (virtual address)
2953	if (tlb_flags.b) // PTE1
2954	{
2955	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2956	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2957	}
2958	else // PTE2
2959	{
2960	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2961	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2962	}
2963	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2964	m_drsp.valid = false;
2965	m_drsp.error = false;
2966	m_drsp.rdata = 0;
2967	}
2968	else // SC request accepted
2969	{
2970	#ifdef INSTRUMENTATION
2971	m_cpt_data_sc++;
2972	#endif
2973	// checking local success
2974	if (r_dcache_llsc_valid.read() and
2975	(r_dcache_llsc_paddr.read() == paddr)) // local success
2976	{
2977	// request an SC CMD and go to DCACHE_SC_WAIT state
2978	r_dcache_vci_paddr = paddr;
2979	r_dcache_vci_sc_req = true;
2980	r_dcache_vci_sc_data = m_dreq.wdata;
2981	r_dcache_fsm = DCACHE_SC_WAIT;
2982	}
2983	else // local fail
2984	{
2985	m_drsp.valid = true;
2986	m_drsp.error = false;
2987	m_drsp.rdata = 0x1;
2988	}
2989	}
2990	} // end SC
2991	} // end valid_req
2992	} // end if read/write/ll/sc request
2993	} // end processor request
2994
2995	// itlb miss request
2996	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
2997	{
2998	r_dcache_tlb_ins = true;
2999	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3000	r_dcache_fsm = DCACHE_TLB_MISS;
3001	}
3002
3003	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
3004	r_dcache_updt_req = updt_request;
3005	r_dcache_wbuf_req = wbuf_request or
3006	(r_dcache_wbuf_req.read() and wbuf_write_miss);
3007	break;
3008	}
3009	/////////////////////
3010	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
3011	// Input arguments are:
3012	// - r_dcache_tlb_vaddr
3013	// - r_dcache_tlb_ins (true when itlb miss)
3014	// The sub-fsm access the dcache to find the missing TLB entry,
3015	// and activates the cache miss procedure in case of miss.
3016	// It bypass the first level page table access if possible.
3017	// It uses atomic access to update the R/L access bits
3018	// in the page table if required.
3019	// It directly updates the itlb or dtlb, and writes into the
3020	// r_mmu_ins_* or r_mmu_data* error reporting registers.
3021	{
3022	uint32_t ptba = 0;
3023	bool bypass;
3024	paddr_t pte_paddr;
3025
3026	// evaluate bypass in order to skip first level page table access
3027	if (r_dcache_tlb_ins.read()) // itlb miss
3028	{
3029	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3030	}
3031	else // dtlb miss
3032	{
3033	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3034	}
3035
3036	if (not bypass) // Try to read PTE1/PTD1 in dcache
3037	{
3038	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
3039	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
3040	r_dcache_tlb_paddr = pte_paddr;
3041	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3042	}
3043	else // Try to read PTE2 in dcache
3044	{
3045	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
3046	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
3047	r_dcache_tlb_paddr = pte_paddr;
3048	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3049	}
3050
3051	#if DEBUG_DCACHE
3052	if (m_debug_dcache_fsm)
3053	{
3054	if (r_dcache_tlb_ins.read())
3055	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
3056	else
3057	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
3058	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
3059	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
3060	<< " / BYPASS = " << bypass
3061	<< " / PTE_ADR = " << pte_paddr << std::endl;
3062	}
3063	#endif
3064
3065	break;
3066	}
3067	/////////////////////////
3068	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
3069	{
3070	// coherence clack request (from DSPIN CLACK)
3071	if (r_dcache_clack_req.read())
3072	{
3073	r_dcache_fsm = DCACHE_CC_CHECK;
3074	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3075	break;
3076	}
3077
3078	// coherence request (from CC_RECEIVE FSM)
3079	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3080	{
3081	r_dcache_fsm = DCACHE_CC_CHECK;
3082	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3083	break;
3084	}
3085
3086	uint32_t entry;
3087	size_t way;
3088	size_t set;
3089	size_t word;
3090	int cache_state;
3091	r_dcache.read(r_dcache_tlb_paddr.read(),
3092	&entry,
3093	&way,
3094	&set,
3095	&word,
3096	&cache_state);
3097	#ifdef INSTRUMENTATION
3098	m_cpt_dcache_data_read++;
3099	m_cpt_dcache_dir_read++;
3100	#endif
3101	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3102	{
3103	if (not (entry & PTE_V_MASK)) // unmapped
3104	{
3105	if (r_dcache_tlb_ins.read())
3106	{
3107	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
3108	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3109	r_icache_tlb_miss_req = false;
3110	r_icache_tlb_rsp_error = true;
3111	}
3112	else
3113	{
3114	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
3115	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3116	m_drsp.valid = true;
3117	m_drsp.error = true;
3118	}
3119	r_dcache_fsm = DCACHE_IDLE;
3120
3121	#if DEBUG_DCACHE
3122	if (m_debug_dcache_fsm)
3123	{
3124	std::cout << " <PROC " << name()
3125	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
3126	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3127	<< std::dec << " / way = " << way
3128	<< std::dec << " / set = " << set
3129	<< std::dec << " / word = " << word
3130	<< std::hex << " / PTE1 = " << entry << std::endl;
3131	}
3132	#endif
3133
3134	}
3135	else if (entry & PTE_T_MASK) // PTD : me must access PT2
3136	{
3137	// mark the cache line ac containing a PTD
3138	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
3139
3140	// register bypass
3141	if (r_dcache_tlb_ins.read()) // itlb
3142	{
3143	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3144	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3145	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
3146	}
3147	else // dtlb
3148	{
3149	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3150	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3151	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
3152	}
3153	r_dcache_tlb_paddr =
3154	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
3155	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3156	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3157
3158	#if DEBUG_DCACHE
3159	if (m_debug_dcache_fsm)
3160	{
3161	std::cout << " <PROC " << name()
3162	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3163	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3164	<< std::dec << " / way = " << way
3165	<< std::dec << " / set = " << set
3166	<< std::dec << " / word = " << word
3167	<< std::hex << " / PTD = " << entry << std::endl;
3168	}
3169	#endif
3170	}
3171	else // PTE1 : we must update the TLB
3172	{
3173	r_dcache_in_tlb[m_icache_sets * way + set] = true;
3174	r_dcache_tlb_pte_flags = entry;
3175	r_dcache_tlb_cache_way = way;
3176	r_dcache_tlb_cache_set = set;
3177	r_dcache_tlb_cache_word = word;
3178	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3179
3180	#if DEBUG_DCACHE
3181	if (m_debug_dcache_fsm)
3182	{
3183	std::cout << " <PROC " << name()
3184	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3185	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3186	<< std::dec << " / way = " << way
3187	<< std::dec << " / set = " << set
3188	<< std::dec << " / word = " << word
3189	<< std::hex << " / PTE1 = " << entry << std::endl;
3190	}
3191	#endif
3192	}
3193	}
3194	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3195	{
3196	// stalled until cleanup is acknowledged
3197	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3198	}
3199	else // we must load the missing cache line in dcache
3200	{
3201	r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
3202
3203	r_dcache_vci_miss_req = true;
3204	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3205	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3206	r_dcache_miss_type = PTE1_MISS;
3207	r_dcache_fsm = DCACHE_MISS_SELECT;
3208
3209	#if DEBUG_DCACHE
3210	if (m_debug_dcache_fsm)
3211	{
3212	std::cout << " <PROC " << name()
3213	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3214	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3215	}
3216	#endif
3217	}
3218	break;
3219	}
3220	////////////////////////////
3221	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3222	{
3223	size_t way;
3224	size_t set;
3225
3226	if (r_dcache_tlb_ins.read())
3227	{
3228	r_itlb.select(r_dcache_tlb_vaddr.read(),
3229	true, // PTE1
3230	&way,
3231	&set);
3232	#ifdef INSTRUMENTATION
3233	m_cpt_itlb_read++;
3234	#endif
3235	}
3236	else
3237	{
3238	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3239	true, // PTE1
3240	&way,
3241	&set);
3242	#ifdef INSTRUMENTATION
3243	m_cpt_dtlb_read++;
3244	#endif
3245	}
3246	r_dcache_tlb_way = way;
3247	r_dcache_tlb_set = set;
3248	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3249
3250	#if DEBUG_DCACHE
3251	if (m_debug_dcache_fsm)
3252	{
3253	if (r_dcache_tlb_ins.read())
3254	std::cout << " <PROC " << name()
3255	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3256	else
3257	std::cout << " <PROC " << name()
3258	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3259	std::cout << " way = " << std::dec << way
3260	<< " / set = " << set << std::endl;
3261	}
3262	#endif
3263	break;
3264	}
3265	//////////////////////////
3266	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3267	// - if L/R bit already set, exit the sub-fsm.
3268	// - if not, we update the page table but we dont write
3269	// neither in DCACHE, nor in TLB, as this will be done by
3270	// the coherence mechanism.
3271	{
3272	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3273	uint32_t pte = r_dcache_tlb_pte_flags.read();
3274	bool pt_updt = false;
3275	bool local = true;
3276
3277	// We should compute the access locality:
3278	// The PPN MSB bits define the destination cluster index.
3279	// The m_srcid MSB bits define the source cluster index.
3280	// The number of bits to compare depends on the number of clusters,
3281	// and can be obtained in the mapping table.
3282	// As long as this computation is not done, all access are local.
3283
3284	if (local) // local access
3285	{
3286	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3287	{
3288	pt_updt = true;
3289	r_dcache_vci_cas_old = pte;
3290	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3291	pte = pte \| PTE_L_MASK;
3292	r_dcache_tlb_pte_flags = pte;
3293	}
3294	}
3295	else // remote access
3296	{
3297	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3298	{
3299	pt_updt = true;
3300	r_dcache_vci_cas_old = pte;
3301	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3302	pte = pte \| PTE_R_MASK;
3303	r_dcache_tlb_pte_flags = pte;
3304	}
3305	}
3306
3307	if (not pt_updt) // update TLB and return
3308	{
3309	if (r_dcache_tlb_ins.read())
3310	{
3311	r_itlb.write(true, // 2M page
3312	pte,
3313	0, // argument unused for a PTE1
3314	r_dcache_tlb_vaddr.read(),
3315	r_dcache_tlb_way.read(),
3316	r_dcache_tlb_set.read(),
3317	nline);
3318	#ifdef INSTRUMENTATION
3319	m_cpt_itlb_write++;
3320	#endif
3321
3322	#if DEBUG_DCACHE
3323	if (m_debug_dcache_fsm)
3324	{
3325	std::cout << " <PROC " << name()
3326	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3327	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3328	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3329	r_itlb.printTrace();
3330	}
3331	#endif
3332	}
3333	else
3334	{
3335	r_dtlb.write(true, // 2M page
3336	pte,
3337	0, // argument unused for a PTE1
3338	r_dcache_tlb_vaddr.read(),
3339	r_dcache_tlb_way.read(),
3340	r_dcache_tlb_set.read(),
3341	nline);
3342	#ifdef INSTRUMENTATION
3343	m_cpt_dtlb_write++;
3344	#endif
3345
3346	#if DEBUG_DCACHE
3347	if (m_debug_dcache_fsm)
3348	{
3349	std::cout << " <PROC " << name()
3350	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3351	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3352	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3353	r_dtlb.printTrace();
3354	}
3355	#endif
3356	}
3357	r_dcache_fsm = DCACHE_TLB_RETURN;
3358	}
3359	else // update page table but not TLB
3360	{
3361	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3362
3363	#if DEBUG_DCACHE
3364	if (m_debug_dcache_fsm)
3365	{
3366	std::cout << " <PROC " << name()
3367	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3368	<< std::endl;
3369	}
3370	#endif
3371	}
3372	break;
3373	}
3374	/////////////////////////
3375	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3376	{
3377	// coherence clack request (from DSPIN CLACK)
3378	if (r_dcache_clack_req.read())
3379	{
3380	r_dcache_fsm = DCACHE_CC_CHECK;
3381	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3382	break;
3383	}
3384
3385	// coherence request (from CC_RECEIVE FSM)
3386	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3387	{
3388	r_dcache_fsm = DCACHE_CC_CHECK;
3389	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3390	break;
3391	}
3392
3393	uint32_t pte_flags;
3394	uint32_t pte_ppn;
3395	size_t way;
3396	size_t set;
3397	size_t word;
3398	int cache_state;
3399
3400	r_dcache.read(r_dcache_tlb_paddr.read(),
3401	&pte_flags,
3402	&pte_ppn,
3403	&way,
3404	&set,
3405	&word,
3406	&cache_state);
3407	#ifdef INSTRUMENTATION
3408	m_cpt_dcache_data_read++;
3409	m_cpt_dcache_dir_read++;
3410	#endif
3411	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3412	{
3413	if (not (pte_flags & PTE_V_MASK)) // unmapped
3414	{
3415	if (r_dcache_tlb_ins.read())
3416	{
3417	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3418	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3419	r_icache_tlb_miss_req = false;
3420	r_icache_tlb_rsp_error = true;
3421	}
3422	else
3423	{
3424	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3425	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3426	m_drsp.valid = true;
3427	m_drsp.error = true;
3428	}
3429	r_dcache_fsm = DCACHE_IDLE;
3430
3431	#if DEBUG_DCACHE
3432	if (m_debug_dcache_fsm)
3433	{
3434	std::cout << " <PROC " << name()
3435	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3436	<< " PTE_FLAGS = " << std::hex << pte_flags
3437	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3438	}
3439	#endif
3440	}
3441	else // mapped : we must update the TLB
3442	{
3443	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
3444	r_dcache_tlb_pte_flags = pte_flags;
3445	r_dcache_tlb_pte_ppn = pte_ppn;
3446	r_dcache_tlb_cache_way = way;
3447	r_dcache_tlb_cache_set = set;
3448	r_dcache_tlb_cache_word = word;
3449	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3450
3451	#if DEBUG_DCACHE
3452	if (m_debug_dcache_fsm)
3453	{
3454	std::cout << " <PROC " << name()
3455	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3456	<< " PTE_FLAGS = " << std::hex << pte_flags
3457	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3458	}
3459	#endif
3460	}
3461	}
3462	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3463	{
3464	// stalled until cleanup is acknowledged
3465	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3466
3467	#if DEBUG_DCACHE
3468	if (m_debug_dcache_fsm)
3469	{
3470	std::cout << " <PROC " << name()
3471	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3472	<< std::endl;
3473	}
3474	#endif
3475	}
3476	else // we must load the missing cache line in dcache
3477	{
3478	r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
3479
3480	r_dcache_fsm = DCACHE_MISS_SELECT;
3481	r_dcache_vci_miss_req = true;
3482	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3483	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3484	r_dcache_miss_type = PTE2_MISS;
3485
3486	#if DEBUG_DCACHE
3487	if (m_debug_dcache_fsm)
3488	{
3489	std::cout << " <PROC " << name()
3490	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3491	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3492	}
3493	#endif
3494	}
3495	break;
3496	}
3497	////////////////////////////
3498	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3499	{
3500	size_t way;
3501	size_t set;
3502
3503	if (r_dcache_tlb_ins.read())
3504	{
3505	r_itlb.select(r_dcache_tlb_vaddr.read(),
3506	false, // PTE2
3507	&way,
3508	&set);
3509	#ifdef INSTRUMENTATION
3510	m_cpt_itlb_read++;
3511	#endif
3512	}
3513	else
3514	{
3515	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3516	false, // PTE2
3517	&way,
3518	&set);
3519	#ifdef INSTRUMENTATION
3520	m_cpt_dtlb_read++;
3521	#endif
3522	}
3523
3524	#if DEBUG_DCACHE
3525	if (m_debug_dcache_fsm)
3526	{
3527	if (r_dcache_tlb_ins.read())
3528	std::cout << " <PROC " << name()
3529	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3530	else
3531	std::cout << " <PROC " << name()
3532	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3533	std::cout << " way = " << std::dec << way
3534	<< " / set = " << set << std::endl;
3535	}
3536	#endif
3537	r_dcache_tlb_way = way;
3538	r_dcache_tlb_set = set;
3539	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3540	break;
3541	}
3542	//////////////////////////
3543	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3544	// - if L/R bit already set, exit the sub-fsm.
3545	// - if not, we update the page table but we dont write
3546	// neither in DCACHE, nor in TLB, as this will be done by
3547	// the coherence mechanism.
3548	{
3549	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3550	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3551	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3552	bool pt_updt = false;
3553	bool local = true;
3554
3555	// We should compute the access locality:
3556	// The PPN MSB bits define the destination cluster index.
3557	// The m_srcid MSB bits define the source cluster index.
3558	// The number of bits to compare depends on the number of clusters,
3559	// and can be obtained in the mapping table.
3560	// As long as this computation is not done, all access are local.
3561
3562	if (local) // local access
3563	{
3564	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3565	{
3566	pt_updt = true;
3567	r_dcache_vci_cas_old = pte_flags;
3568	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3569	pte_flags = pte_flags \| PTE_L_MASK;
3570	r_dcache_tlb_pte_flags = pte_flags;
3571	}
3572	}
3573	else // remote access
3574	{
3575	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3576	{
3577	pt_updt = true;
3578	r_dcache_vci_cas_old = pte_flags;
3579	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3580	pte_flags = pte_flags \| PTE_R_MASK;
3581	r_dcache_tlb_pte_flags = pte_flags;
3582	}
3583	}
3584
3585	if (not pt_updt) // update TLB
3586	{
3587	if (r_dcache_tlb_ins.read())
3588	{
3589	r_itlb.write( false, // 4K page
3590	pte_flags,
3591	pte_ppn,
3592	r_dcache_tlb_vaddr.read(),
3593	r_dcache_tlb_way.read(),
3594	r_dcache_tlb_set.read(),
3595	nline );
3596	#ifdef INSTRUMENTATION
3597	m_cpt_itlb_write++;
3598	#endif
3599
3600	#if DEBUG_DCACHE
3601	if (m_debug_dcache_fsm)
3602	{
3603	std::cout << " <PROC " << name()
3604	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3605	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3606	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3607	r_itlb.printTrace();
3608	}
3609	#endif
3610	}
3611	else
3612	{
3613	r_dtlb.write(false, // 4K page
3614	pte_flags,
3615	pte_ppn,
3616	r_dcache_tlb_vaddr.read(),
3617	r_dcache_tlb_way.read(),
3618	r_dcache_tlb_set.read(),
3619	nline);
3620	#ifdef INSTRUMENTATION
3621	m_cpt_dtlb_write++;
3622	#endif
3623
3624	#if DEBUG_DCACHE
3625	if (m_debug_dcache_fsm)
3626	{
3627	std::cout << " <PROC " << name()
3628	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3629	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3630	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3631	r_dtlb.printTrace();
3632	}
3633	#endif
3634
3635	}
3636	r_dcache_fsm = DCACHE_TLB_RETURN;
3637	}
3638	else // update page table but not TLB
3639	{
3640	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3641
3642	#if DEBUG_DCACHE
3643	if (m_debug_dcache_fsm)
3644	{
3645	std::cout << " <PROC " << name()
3646	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3647	}
3648	#endif
3649	}
3650	break;
3651	}
3652	////////////////////////
3653	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3654	{
3655	#if DEBUG_DCACHE
3656	if (m_debug_dcache_fsm)
3657	{
3658	std::cout << " <PROC " << name()
3659	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3660	}
3661	#endif
3662	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3663	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3664
3665	// checking llsc reservation buffer
3666	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
3667	r_dcache_llsc_valid = false;
3668
3669	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3670	r_dcache_vci_cas_req = true;
3671	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3672	break;
3673	}
3674	////////////////////////
3675	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3676	// We consume the response in rsp FIFO,
3677	// and exit the sub-fsm, but we don't
3678	// analyse the response, because we don't
3679	// care if the L/R bit update is not done.
3680	// We must take the coherence requests because
3681	// there is a risk of dead-lock
3682
3683	{
3684	// coherence clack request (from DSPIN CLACK)
3685	if (r_dcache_clack_req.read())
3686	{
3687	r_dcache_fsm = DCACHE_CC_CHECK;
3688	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3689	break;
3690	}
3691
3692	// coherence request (from CC_RECEIVE FSM)
3693	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3694	{
3695	r_dcache_fsm = DCACHE_CC_CHECK;
3696	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3697	break;
3698	}
3699
3700	if (r_vci_rsp_data_error.read()) // bus error
3701	{
3702	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3703	std::cout << "This should not happen in this state" << std::endl;
3704	exit(0);
3705	}
3706	else if (r_vci_rsp_fifo_dcache.rok()) // response available
3707	{
3708	#if DEBUG_DCACHE
3709	if (m_debug_dcache_fsm)
3710	{
3711	std::cout << " <PROC " << name()
3712	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3713	}
3714	#endif
3715	vci_rsp_fifo_dcache_get = true;
3716	r_dcache_fsm = DCACHE_TLB_RETURN;
3717	}
3718	break;
3719	}
3720	///////////////////////
3721	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3722	{
3723	#if DEBUG_DCACHE
3724	if (m_debug_dcache_fsm)
3725	{
3726	std::cout << " <PROC " << name()
3727	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3728	}
3729	#endif
3730	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
3731	r_dcache_fsm = DCACHE_IDLE;
3732	break;
3733	}
3734	///////////////////////
3735	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3736	// and both itlb and dtlb must be flushed.
3737	// Caution : the itlb miss requests must be taken
3738	// to avoid dead-lock in case of simultaneous ITLB miss
3739	// Caution : the clack and cc requests must be taken
3740	// to avoid dead-lock
3741	{
3742	// coherence clack request (from DSPIN CLACK)
3743	if (r_dcache_clack_req.read())
3744	{
3745	r_dcache_fsm = DCACHE_CC_CHECK;
3746	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3747	break;
3748	}
3749
3750	// coherence request (from CC_RECEIVE FSM)
3751	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3752	{
3753	r_dcache_fsm = DCACHE_CC_CHECK;
3754	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3755	break;
3756	}
3757
3758	// itlb miss request
3759	if (r_icache_tlb_miss_req.read())
3760	{
3761	r_dcache_tlb_ins = true;
3762	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3763	r_dcache_fsm = DCACHE_TLB_MISS;
3764	break;
3765	}
3766
3767	if (not r_dcache_xtn_req.read())
3768	{
3769	r_dtlb.flush();
3770	r_mmu_ptpr = m_dreq.wdata;
3771	r_dcache_fsm = DCACHE_IDLE;
3772	m_drsp.valid = true;
3773	}
3774	break;
3775	}
3776	/////////////////////
3777	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3778	// The coherence request must be taken
3779	// as there is a risk of dead-lock
3780	{
3781	// coherence clack request (from DSPIN CLACK)
3782	if (r_dcache_clack_req.read())
3783	{
3784	r_dcache_fsm = DCACHE_CC_CHECK;
3785	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3786	break;
3787	}
3788
3789	// coherence request (from CC_RECEIVE FSM)
3790	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3791	{
3792	r_dcache_fsm = DCACHE_CC_CHECK;
3793	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3794	break;
3795	}
3796
3797	if (r_wbuf.empty())
3798	{
3799	m_drsp.valid = true;
3800	r_dcache_fsm = DCACHE_IDLE;
3801	}
3802	break;
3803	}
3804	////////////////////////
3805	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3806	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3807	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3808	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
3809	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
3810
3811	{
3812	// coherence clack request (from DSPIN CLACK)
3813	if (r_dcache_clack_req.read())
3814	{
3815	r_dcache_fsm = DCACHE_CC_CHECK;
3816	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3817	break;
3818	}
3819
3820	// coherence request (from CC_RECEIVE FSM)
3821	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3822	{
3823	r_dcache_fsm = DCACHE_CC_CHECK;
3824	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3825	break;
3826	}
3827
3828	// itlb miss request
3829	if (r_icache_tlb_miss_req.read())
3830	{
3831	r_dcache_tlb_ins = true;
3832	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3833	r_dcache_fsm = DCACHE_TLB_MISS;
3834	break;
3835	}
3836
3837	// test if XTN request to icache completed
3838	if (not r_dcache_xtn_req.read())
3839	{
3840	r_dcache_fsm = DCACHE_IDLE;
3841	m_drsp.valid = true;
3842	}
3843	break;
3844	}
3845	/////////////////////////
3846	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3847	// r_dcache_flush_count as a slot counter,
3848	// looping in this state until all slots have been visited.
3849	// It can require two cycles per slot:
3850	// We test here the slot state, and make the actual inval
3851	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3852	// A cleanup request is generated for each valid line.
3853	// returns to IDLE and flush TLBs when last slot
3854	{
3855	// coherence clack request (from DSPIN CLACK)
3856	if (r_dcache_clack_req.read())
3857	{
3858	r_dcache_fsm = DCACHE_CC_CHECK;
3859	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3860	break;
3861	}
3862
3863	// coherence request (from CC_RECEIVE FSM)
3864	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3865	{
3866	r_dcache_fsm = DCACHE_CC_CHECK;
3867	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3868	break;
3869	}
3870
3871	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
3872	{
3873	int state;
3874	paddr_t tag;
3875	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
3876	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
3877
3878	#ifdef INSTRUMENTATION
3879	m_cpt_dcache_dir_read++;
3880	#endif
3881	r_dcache.read_dir(way,
3882	set,
3883	&tag,
3884	&state);
3885
3886	if (state == CACHE_SLOT_STATE_VALID) // inval required
3887	{
3888	// request cleanup
3889	r_dcache_cc_send_req = true;
3890	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3891	r_dcache_cc_send_way = way;
3892	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3893
3894	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3895	r_dcache_miss_way = way;
3896	r_dcache_miss_set = set;
3897	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3898	}
3899	else if (r_dcache_flush_count.read() ==
3900	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3901	{
3902	r_dtlb.reset();
3903	r_itlb.reset();
3904	r_dcache_fsm = DCACHE_IDLE;
3905	m_drsp.valid = true;
3906	}
3907
3908	// saturation counter
3909	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
3910	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3911	}
3912	break;
3913	}
3914	////////////////////////////
3915	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3916	// and reset directory extension.
3917	// returns to IDLE and flush TLBs when last slot
3918	{
3919	size_t way = r_dcache_miss_way.read();
3920	size_t set = r_dcache_miss_set.read();
3921
3922	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
3923	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
3924
3925	#ifdef INSTRUMENTATION
3926	m_cpt_dcache_dir_write++;
3927	#endif
3928	r_dcache.write_dir(way,
3929	set,
3930	CACHE_SLOT_STATE_ZOMBI);
3931
3932	if (r_dcache_flush_count.read() ==
3933	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3934	{
3935	r_dtlb.reset();
3936	r_itlb.reset();
3937	r_dcache_fsm = DCACHE_IDLE;
3938	m_drsp.valid = true;
3939	}
3940	else
3941	{
3942	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3943	}
3944	break;
3945	}
3946	/////////////////////////
3947	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3948	{
3949	r_dtlb.inval(r_dcache_save_wdata.read());
3950	r_dcache_fsm = DCACHE_IDLE;
3951	m_drsp.valid = true;
3952	break;
3953	}
3954	////////////////////////////
3955	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3956	// requires 3 cycles: access tlb, read cache, inval cache
3957	// we compute the physical address in this state
3958	{
3959	paddr_t paddr;
3960	bool hit;
3961
3962	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
3963	{
3964
3965	#ifdef INSTRUMENTATION
3966	m_cpt_dtlb_read++;
3967	#endif
3968	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
3969	&paddr);
3970	}
3971	else // dtlb not activated
3972	{
3973	paddr = (paddr_t)r_dcache_save_wdata.read();
3974	if (vci_param::N > 32)
3975	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
3976	hit = true;
3977	}
3978
3979	if (hit) // tlb hit
3980	{
3981	r_dcache_save_paddr = paddr;
3982	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3983	}
3984	else // tlb miss
3985	{
3986
3987	#ifdef INSTRUMENTATION
3988	m_cpt_dtlb_miss++;
3989	#endif
3990	r_dcache_tlb_ins = false; // dtlb
3991	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3992	r_dcache_fsm = DCACHE_TLB_MISS;
3993	}
3994
3995	#if DEBUG_DCACHE
3996	if (m_debug_dcache_fsm)
3997	{
3998	std::cout << " <PROC " << name()
3999	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
4000	<< " / VADDR = " << r_dcache_save_wdata.read()
4001	<< " / PADDR = " << paddr << std::endl;
4002	}
4003	#endif
4004
4005	break;
4006	}
4007	////////////////////////////
4008	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
4009	// requires 2 cycles: read cache / inval cache
4010	// In this state we read dcache.
4011	{
4012	size_t way;
4013	size_t set;
4014	size_t word;
4015	int state;
4016
4017	#ifdef INSTRUMENTATION
4018	m_cpt_dcache_dir_read++;
4019	#endif
4020	r_dcache.read_dir(r_dcache_save_paddr.read(),
4021	&state,
4022	&way,
4023	&set,
4024	&word);
4025
4026	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
4027	{
4028	r_dcache_xtn_way = way;
4029	r_dcache_xtn_set = set;
4030	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
4031	}
4032	else // miss : nothing to do
4033	{
4034	r_dcache_fsm = DCACHE_IDLE;
4035	m_drsp.valid = true;
4036	}
4037
4038	#if DEBUG_DCACHE
4039	if (m_debug_dcache_fsm)
4040	{
4041	std::cout << " <PROC " << name()
4042	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
4043	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
4044	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
4045	<< " / SET = " << set
4046	<< " / WAY = " << way << std::endl;
4047	}
4048	#endif
4049	break;
4050	}
4051	////////////////////////////
4052	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
4053	// Blocked if previous cleanup not completed
4054	// Test if itlb or dtlb inval is required
4055	{
4056	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
4057	{
4058	size_t way = r_dcache_xtn_way.read();
4059	size_t set = r_dcache_xtn_set.read();
4060	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4061
4062	#ifdef INSTRUMENTATION
4063	m_cpt_dcache_dir_write++;
4064	#endif
4065	r_dcache.write_dir(way,
4066	set,
4067	CACHE_SLOT_STATE_ZOMBI);
4068
4069	// request cleanup
4070	r_dcache_cc_send_req = true;
4071	r_dcache_cc_send_nline = nline;
4072	r_dcache_cc_send_way = way;
4073	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4074
4075	// possible itlb & dtlb invalidate
4076	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4077	{
4078	r_dcache_tlb_inval_line = nline;
4079	r_dcache_tlb_inval_set = 0;
4080	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
4081	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4082	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4083	}
4084	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4085	{
4086	r_itlb.reset();
4087	r_dtlb.reset();
4088	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4089	r_dcache_fsm = DCACHE_IDLE;
4090	m_drsp.valid = true;
4091	}
4092	else
4093	{
4094	r_dcache_fsm = DCACHE_IDLE;
4095	m_drsp.valid = true;
4096	}
4097
4098	#if DEBUG_DCACHE
4099	if (m_debug_dcache_fsm)
4100	{
4101	std::cout << " <PROC " << name()
4102	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
4103	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
4104	}
4105	#endif
4106	}
4107	break;
4108	}
4109	//////////////////////////////
4110	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
4111	{
4112	r_dcache_fsm = DCACHE_IDLE;
4113	m_drsp.valid = true;
4114	break;
4115	}
4116	////////////////////////
4117	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
4118	// Waiting in this state if no slot available.
4119	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
4120	// we send the cleanup request in this state.
4121	// If not, a r_icache_cleanup_victim_req flip-flop is
4122	// utilized for saving this cleanup request, and it will be sent later
4123	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
4124	// The r_icache_miss_clack flip-flop is set
4125	// when a cleanup is required
4126	{
4127	if (m_dreq.valid) m_cost_data_miss_frz++;
4128
4129	// coherence clack request (from DSPIN CLACK)
4130	if (r_dcache_clack_req.read())
4131	{
4132	r_dcache_fsm = DCACHE_CC_CHECK;
4133	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4134	break;
4135	}
4136
4137	// coherence request (from CC_RECEIVE FSM)
4138	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4139	{
4140	r_dcache_fsm = DCACHE_CC_CHECK;
4141	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4142	break;
4143	}
4144
4145	bool found = false;
4146	bool cleanup = false;
4147	size_t way = 0;
4148	size_t set = 0;
4149	paddr_t victim = 0;
4150
4151	#ifdef INSTRUMENTATION
4152	m_cpt_dcache_dir_read++;
4153	#endif
4154	r_dcache.read_select(r_dcache_save_paddr.read(),
4155	&victim,
4156	&way,
4157	&set,
4158	&found,
4159	&cleanup);
4160
4161	if (not found)
4162	{
4163	break;
4164	}
4165	else
4166	{
4167	r_dcache_miss_way = way;
4168	r_dcache_miss_set = set;
4169
4170	// reset to 0 the miss watchdog timer
4171	r_dcache_miss_wdt = 0;
4172
4173	if (cleanup)
4174	{
4175	if (not r_dcache_cc_send_req.read())
4176	{
4177	r_dcache_cc_send_req = true;
4178	r_dcache_cc_send_nline = victim;
4179	r_dcache_cc_send_way = way;
4180	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4181
4182	}
4183	else
4184	{
4185	r_dcache_cleanup_victim_req = true;
4186	r_dcache_cleanup_victim_nline = victim;
4187	}
4188
4189	r_dcache_miss_clack = true;
4190	r_dcache_fsm = DCACHE_MISS_CLEAN;
4191	}
4192	else
4193	{
4194	r_dcache_fsm = DCACHE_MISS_WAIT;
4195	}
4196
4197	#if DEBUG_DCACHE
4198	if (m_debug_dcache_fsm)
4199	{
4200	std::cout << " <PROC " << name()
4201	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4202	<< " / WAY = " << way
4203	<< " / SET = " << set
4204	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4205	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4206	else std::cout << std::endl;
4207	}
4208	#endif
4209	} // end found
4210	break;
4211	}
4212	///////////////////////
4213	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4214	// and possibly request itlb or dtlb invalidate
4215	{
4216	if (m_dreq.valid) m_cost_data_miss_frz++;
4217
4218	size_t way = r_dcache_miss_way.read();
4219	size_t set = r_dcache_miss_set.read();
4220
4221	#ifdef INSTRUMENTATION
4222	m_cpt_dcache_dir_read++;
4223	#endif
4224	r_dcache.write_dir(way,
4225	set,
4226	CACHE_SLOT_STATE_ZOMBI);
4227	#if DEBUG_DCACHE
4228	if (m_debug_dcache_fsm)
4229	{
4230	std::cout << " <PROC " << name()
4231	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4232	<< " / way = " << way
4233	<< " / set = " << set << std::endl;
4234	}
4235	#endif
4236	// if selective itlb & dtlb invalidate are required
4237	// the miss response is not handled before invalidate completed
4238	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4239	{
4240	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4241
4242	if (not r_dcache_cleanup_victim_req.read())
4243	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
4244	else
4245	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
4246
4247	r_dcache_tlb_inval_set = 0;
4248	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4249	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4250	}
4251	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4252	{
4253	r_itlb.reset();
4254	r_dtlb.reset();
4255	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4256	r_dcache_fsm = DCACHE_MISS_WAIT;
4257	}
4258	else
4259	{
4260	r_dcache_fsm = DCACHE_MISS_WAIT;
4261	}
4262	break;
4263	}
4264	//////////////////////
4265	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4266	// This state is in charge of error signaling
4267	// There is 5 types of error depending on the requester
4268	{
4269	if (m_dreq.valid) m_cost_data_miss_frz++;
4270
4271	// send cleanup victim request
4272	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4273	{
4274	r_dcache_cc_send_req = true;
4275	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4276	r_dcache_cc_send_way = r_dcache_miss_way;
4277	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4278	r_dcache_cleanup_victim_req = false;
4279	}
4280
4281	// coherence clack request (from DSPIN CLACK)
4282	if (r_dcache_clack_req.read())
4283	{
4284	r_dcache_fsm = DCACHE_CC_CHECK;
4285	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4286	break;
4287	}
4288
4289	// coherence request (from CC_RECEIVE FSM)
4290	if (r_cc_receive_dcache_req.read() and
4291	not r_dcache_cc_send_req.read() and
4292	not r_dcache_cleanup_victim_req.read())
4293	{
4294	r_dcache_fsm = DCACHE_CC_CHECK;
4295	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4296	break;
4297	}
4298
4299	// increment MISS watchdog timer for black-hole detection
4300	r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1;
4301	if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) {
4302	r_mmu_detr = MMU_READ_DATA_TIMEOUT;
4303	r_mmu_dbvar = r_dcache_save_vaddr.read();
4304	m_drsp.valid = true;
4305	m_drsp.error = true;
4306	r_dcache_fsm = DCACHE_IDLE;
4307
4308	// debug: this counter is used to detect an early WDT timeout.
4309	// It is sent as the data miss transactions TRDID. When a data miss
4310	// response is treated by the RSP FSM, the RTRDID is compared to
4311	// this counter to determine if a timeout was triggered during the
4312	// transaction.
4313	r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
4314
4315	#if DEBUG_DCACHE
4316	if (m_debug_dcache_fsm)
4317	{
4318	std::cout << " <PROC " << name() << " DCACHE_MISS_WAIT>"
4319	" watchdog timer exception" << std::endl;
4320	}
4321	#endif
4322	break;
4323	}
4324
4325	if (r_vci_rsp_data_error.read()) // bus error
4326	{
4327	switch (r_dcache_miss_type.read())
4328	{
4329	case PROC_MISS:
4330	{
4331	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4332	r_mmu_dbvar = r_dcache_save_vaddr.read();
4333	m_drsp.valid = true;
4334	m_drsp.error = true;
4335	r_dcache_fsm = DCACHE_IDLE;
4336	break;
4337	}
4338	case PTE1_MISS:
4339	{
4340	if (r_dcache_tlb_ins.read())
4341	{
4342	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4343	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4344	r_icache_tlb_miss_req = false;
4345	r_icache_tlb_rsp_error = true;
4346	}
4347	else
4348	{
4349	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4350	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4351	m_drsp.valid = true;
4352	m_drsp.error = true;
4353	}
4354	r_dcache_fsm = DCACHE_IDLE;
4355	break;
4356	}
4357	case PTE2_MISS:
4358	{
4359	if (r_dcache_tlb_ins.read())
4360	{
4361	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4362	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4363	r_icache_tlb_miss_req = false;
4364	r_icache_tlb_rsp_error = true;
4365	}
4366	else
4367	{
4368	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4369	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4370	m_drsp.valid = true;
4371	m_drsp.error = true;
4372	}
4373	r_dcache_fsm = DCACHE_IDLE;
4374	break;
4375	}
4376	} // end switch type
4377	r_vci_rsp_data_error = false;
4378	}
4379	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
4380	{
4381	r_dcache_miss_word = 0;
4382	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4383	}
4384	break;
4385	}
4386	//////////////////////////
4387	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4388	{
4389	if (m_dreq.valid) m_cost_data_miss_frz++;
4390
4391	if (r_vci_rsp_fifo_dcache.rok()) // one word available
4392	{
4393	#ifdef INSTRUMENTATION
4394	m_cpt_dcache_data_write++;
4395	#endif
4396	r_dcache.write(r_dcache_miss_way.read(),
4397	r_dcache_miss_set.read(),
4398	r_dcache_miss_word.read(),
4399	r_vci_rsp_fifo_dcache.read());
4400	#if DEBUG_DCACHE
4401	if (m_debug_dcache_fsm)
4402	{
4403	std::cout << " <PROC " << name()
4404	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4405	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4406	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4407	<< " / SET = " << r_dcache_miss_set.read()
4408	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4409	}
4410	#endif
4411	vci_rsp_fifo_dcache_get = true;
4412	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4413
4414	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
4415	{
4416	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4417	}
4418	}
4419	break;
4420	}
4421	//////////////////////////
4422	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4423	// and the cleanup ack has not been received,
4424	// as indicated by the r_dcache_miss clack.
4425	// - If no matching coherence request (r_dcache_inval_miss)
4426	// switch directory slot to VALID state.
4427	// - If matching coherence request, switch directory slot
4428	// to ZOMBI state, and send a cleanup request.
4429	{
4430	if (m_dreq.valid) m_cost_data_miss_frz++;
4431
4432	// send cleanup victim request
4433	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4434	{
4435	r_dcache_cc_send_req = true;
4436	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4437	r_dcache_cc_send_way = r_dcache_miss_way;
4438	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4439	r_dcache_cleanup_victim_req = false;
4440	}
4441
4442	// coherence clack request (from DSPIN CLACK)
4443	if (r_dcache_clack_req.read())
4444	{
4445	r_dcache_fsm = DCACHE_CC_CHECK;
4446	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4447	break;
4448	}
4449
4450	// coherence request (from CC_RECEIVE FSM)
4451	if (r_cc_receive_dcache_req.read() and
4452	not r_dcache_cc_send_req.read() and
4453	not r_dcache_cleanup_victim_req.read())
4454	{
4455	r_dcache_fsm = DCACHE_CC_CHECK;
4456	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4457	break;
4458	}
4459
4460	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
4461	{
4462	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
4463	{
4464	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
4465	{
4466	r_dcache_miss_inval = false;
4467	// request cleanup
4468	r_dcache_cc_send_req = true;
4469	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4470	r_dcache_cc_send_way = r_dcache_miss_way.read();
4471	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4472
4473	#ifdef INSTRUMENTATION
4474	m_cpt_dcache_dir_write++;
4475	#endif
4476	r_dcache.write_dir( r_dcache_save_paddr.read(),
4477	r_dcache_miss_way.read(),
4478	r_dcache_miss_set.read(),
4479	CACHE_SLOT_STATE_ZOMBI );
4480	#if DEBUG_DCACHE
4481	if (m_debug_dcache_fsm)
4482	std::cout << " <PROC " << name()
4483	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4484	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4485	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4486	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4487	#endif
4488	}
4489	else
4490	break;
4491	}
4492	else // switch slot to VALID state
4493	{
4494
4495	#ifdef INSTRUMENTATION
4496	m_cpt_dcache_dir_write++;
4497	#endif
4498	r_dcache.write_dir(r_dcache_save_paddr.read(),
4499	r_dcache_miss_way.read(),
4500	r_dcache_miss_set.read(),
4501	CACHE_SLOT_STATE_VALID);
4502
4503	#if DEBUG_DCACHE
4504	if (m_debug_dcache_fsm)
4505	std::cout << " <PROC " << name()
4506	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4507	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4508	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4509	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4510	#endif
4511	// reset directory extension
4512	size_t way = r_dcache_miss_way.read();
4513	size_t set = r_dcache_miss_set.read();
4514	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4515	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4516	}
4517	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4518	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4519	else r_dcache_fsm = DCACHE_IDLE;
4520	}
4521	break;
4522	}
4523	/////////////////////
4524	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
4525	{
4526	// coherence clack request (from DSPIN CLACK)
4527	if (r_dcache_clack_req.read())
4528	{
4529	r_dcache_fsm = DCACHE_CC_CHECK;
4530	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4531	break;
4532	}
4533
4534	// coherence request (from CC_RECEIVE FSM)
4535	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4536	{
4537	r_dcache_fsm = DCACHE_CC_CHECK;
4538	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4539	break;
4540	}
4541
4542	if (r_vci_rsp_data_error.read()) // bus error
4543	{
4544	if (r_dcache_vci_unc_write.read())
4545	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
4546	else
4547	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4548
4549	r_mmu_dbvar = m_dreq.addr;
4550	r_vci_rsp_data_error = false;
4551	m_drsp.error = true;
4552	m_drsp.valid = true;
4553	r_dcache_fsm = DCACHE_IDLE;
4554	break;
4555	}
4556	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4557	{
4558	// consume data
4559	vci_rsp_fifo_dcache_get = true;
4560	r_dcache_fsm = DCACHE_IDLE;
4561
4562	// acknowledge the processor request if it has not been modified
4563	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4564	{
4565	m_drsp.valid = true;
4566	m_drsp.error = false;
4567	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4568	}
4569	}
4570	break;
4571	}
4572	/////////////////////
4573	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4574	{
4575	// coherence clack request (from DSPIN CLACK)
4576	if (r_dcache_clack_req.read())
4577	{
4578	r_dcache_fsm = DCACHE_CC_CHECK;
4579	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4580	break;
4581	}
4582
4583	// coherence request (from CC_RECEIVE FSM)
4584	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4585	{
4586	r_dcache_fsm = DCACHE_CC_CHECK;
4587	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4588	break;
4589	}
4590
4591	if (r_vci_rsp_data_error.read()) // bus error
4592	{
4593	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4594	r_mmu_dbvar = m_dreq.addr;
4595	r_vci_rsp_data_error = false;
4596	m_drsp.error = true;
4597	m_drsp.valid = true;
4598	r_dcache_fsm = DCACHE_IDLE;
4599	break;
4600	}
4601	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4602	{
4603	// consume data
4604	vci_rsp_fifo_dcache_get = true;
4605
4606	if (r_dcache_ll_rsp_count.read() == 0) // first flit
4607	{
4608	// set key value in llsc reservation buffer
4609	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4610	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
4611	}
4612	else // last flit
4613	{
4614	// acknowledge the processor request if it has not been modified
4615	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4616	{
4617	m_drsp.valid = true;
4618	m_drsp.error = false;
4619	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4620	}
4621	r_dcache_fsm = DCACHE_IDLE;
4622	}
4623	}
4624	break;
4625	}
4626	////////////////////
4627	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4628	{
4629	// coherence clack request (from DSPIN CLACK)
4630	if (r_dcache_clack_req.read())
4631	{
4632	r_dcache_fsm = DCACHE_CC_CHECK;
4633	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4634	break;
4635	}
4636
4637	// coherence request (from CC_RECEIVE FSM)
4638	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4639	{
4640	r_dcache_fsm = DCACHE_CC_CHECK;
4641	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4642	break;
4643	}
4644
4645	if (r_vci_rsp_data_error.read()) // bus error
4646	{
4647	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4648	r_mmu_dbvar = m_dreq.addr;
4649	r_vci_rsp_data_error = false;
4650	m_drsp.error = true;
4651	m_drsp.valid = true;
4652	r_dcache_fsm = DCACHE_IDLE;
4653	break;
4654	}
4655	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4656	{
4657	// consume response
4658	vci_rsp_fifo_dcache_get = true;
4659	m_drsp.valid = true;
4660	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4661	r_dcache_fsm = DCACHE_IDLE;
4662	}
4663	break;
4664	}
4665	//////////////////////////
4666	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4667	// before handling a processor WRITE or SC request
4668	// Input argument is r_dcache_dirty_paddr
4669	// In this first state, we get PTE value in dcache
4670	// and post a CAS request to CMD FSM
4671	{
4672	// get PTE in dcache
4673	uint32_t pte;
4674	size_t way;
4675	size_t set;
4676	size_t word; // unused
4677	int state;
4678
4679	#ifdef INSTRUMENTATION
4680	m_cpt_dcache_data_read++;
4681	m_cpt_dcache_dir_read++;
4682	#endif
4683	r_dcache.read(r_dcache_dirty_paddr.read(),
4684	&pte,
4685	&way,
4686	&set,
4687	&word,
4688	&state);
4689
4690	assert( (state == CACHE_SLOT_STATE_VALID) and
4691	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4692
4693	// request CAS transaction to CMD_FSM
4694	r_dcache_dirty_way = way;
4695	r_dcache_dirty_set = set;
4696
4697	// check llsc reservation buffer
4698	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
4699	r_dcache_llsc_valid = false;
4700
4701	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4702	r_dcache_vci_cas_req = true;
4703	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4704	r_dcache_vci_cas_old = pte;
4705	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4706	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4707
4708	#if DEBUG_DCACHE
4709	if (m_debug_dcache_fsm)
4710	{
4711	std::cout << " <PROC " << name()
4712	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4713	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4714	<< " / PTE_VALUE = " << pte << std::dec
4715	<< " / SET = " << set
4716	<< " / WAY = " << way << std::endl;
4717	}
4718	#endif
4719	break;
4720	}
4721	///////////////////////
4722	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4723	// and return to IDLE state when response is received.
4724	// we don't care if the CAS is a failure:
4725	// - if the CAS is a success, the coherence mechanism
4726	// updates the local copy.
4727	// - if the CAS is a failure, we just retry the write.
4728	{
4729	// coherence clack request (from DSPIN CLACK)
4730	if (r_dcache_clack_req.read())
4731	{
4732	r_dcache_fsm = DCACHE_CC_CHECK;
4733	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4734	break;
4735	}
4736
4737	// coherence request (from CC_RECEIVE FSM)
4738	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4739	{
4740	r_dcache_fsm = DCACHE_CC_CHECK;
4741	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4742	break;
4743	}
4744
4745	if (r_vci_rsp_data_error.read()) // bus error
4746	{
4747	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4748	std::cout << "This should not happen in this state" << std::endl;
4749	exit(0);
4750	}
4751	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4752	{
4753	vci_rsp_fifo_dcache_get = true;
4754	r_dcache_fsm = DCACHE_IDLE;
4755
4756	#if DEBUG_DCACHE
4757	if (m_debug_dcache_fsm)
4758	{
4759	std::cout << " <PROC " << name()
4760	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4761	}
4762	#endif
4763	}
4764	break;
4765	}
4766	/////////////////////
4767	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4768	// handling coherence requests for DCACHE.
4769	// If there is a matching pending miss on the modified cache
4770	// line this is signaled in the r_dcache_miss inval flip-flop.
4771	// If the updated (or invalidated) cache line has copies in TLBs
4772	// these TLB copies are invalidated.
4773	// The return state is defined in r_dcache_fsm_cc_save
4774	{
4775	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4776	paddr_t mask = ~((m_dcache_words << 2) - 1);
4777
4778	// CLACK handler
4779	// We switch the directory slot to EMPTY state and reset
4780	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
4781	if (r_dcache_clack_req.read())
4782	{
4783	if (m_dreq.valid ) m_cost_data_miss_frz++;
4784
4785	#ifdef INSTRUMENTATION
4786	m_cpt_dcache_dir_write++;
4787	#endif
4788	r_dcache.write_dir(0,
4789	r_dcache_clack_way.read(),
4790	r_dcache_clack_set.read(),
4791	CACHE_SLOT_STATE_EMPTY);
4792
4793	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4794	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
4795	{
4796	r_dcache_miss_clack = false;
4797	}
4798
4799	r_dcache_clack_req = false;
4800
4801	// return to cc_save state
4802	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4803
4804	#if DEBUG_DCACHE
4805	if (m_debug_dcache_fsm)
4806	{
4807	std::cout << " <PROC " << name()
4808	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
4809	<< " Switch slot to EMPTY state : "
4810	<< " set = " << r_dcache_clack_set.read()
4811	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4812	}
4813	#endif
4814	break;
4815	}
4816
4817	assert(not r_dcache_cc_send_req.read() and
4818	"CC_SEND must be available in DCACHE_CC_CHECK");
4819
4820	// Match between MISS address and CC address
4821	if (r_cc_receive_dcache_req.read() and
4822	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4823	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4824	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4825	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
4826	{
4827	// signaling matching
4828	r_dcache_miss_inval = true;
4829
4830	// in case of update, go to CC_UPDT
4831	// JUST TO POP THE FIFO
4832	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4833	{
4834	r_dcache_fsm = DCACHE_CC_UPDT;
4835	r_dcache_cc_word = r_cc_receive_word_idx.read();
4836
4837	// just pop the fifo , don't write in icache
4838	r_dcache_cc_need_write = false;
4839	}
4840	// the request is dealt with
4841	else
4842	{
4843	r_cc_receive_dcache_req = false;
4844	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4845	}
4846
4847	#if DEBUG_DCACHE
4848	if (m_debug_dcache_fsm)
4849	{
4850	std::cout << " <PROC " << name()
4851	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4852	<< " PADDR = " << std::hex << paddr << std::endl;
4853	}
4854	#endif
4855	}
4856
4857	// CC request handler
4858
4859	int state = 0;
4860	size_t way = 0;
4861	size_t set = 0;
4862	size_t word = 0;
4863
4864	#ifdef INSTRUMENTATION
4865	m_cpt_dcache_dir_read++;
4866	#endif
4867	r_dcache.read_dir(paddr,
4868	&state,
4869	&way,
4870	&set,
4871	&word); // unused
4872
4873	r_dcache_cc_way = way;
4874	r_dcache_cc_set = set;
4875
4876	if (state == CACHE_SLOT_STATE_VALID) // hit
4877	{
4878	// need to update the cache state
4879	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4880	{
4881	r_dcache_cc_need_write = true;
4882	r_dcache_fsm = DCACHE_CC_UPDT;
4883	r_dcache_cc_word = r_cc_receive_word_idx.read();
4884	}
4885	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4886	{
4887	r_dcache_fsm = DCACHE_CC_INVAL;
4888	}
4889	}
4890	else // miss
4891	{
4892	// multicast acknowledgement required in case of update
4893	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4894	{
4895	r_dcache_fsm = DCACHE_CC_UPDT;
4896	r_dcache_cc_word = r_cc_receive_word_idx.read();
4897
4898	// just pop the fifo , don't write in icache
4899	r_dcache_cc_need_write = false;
4900	}
4901	else // No response needed
4902	{
4903	r_cc_receive_dcache_req = false;
4904	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4905	}
4906	}
4907
4908	#if DEBUG_DCACHE
4909	if (m_debug_dcache_fsm)
4910	{
4911	std::cout << " <PROC " << name()
4912	<< " DCACHE_CC_CHECK> Coherence request received:"
4913	<< " PADDR = " << std::hex << paddr
4914	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4915	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4916	}
4917	#endif
4918
4919	break;
4920	}
4921	/////////////////////
4922	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
4923	// CLEANUP after possible invalidation of copies in
4924	// TLBs
4925	{
4926	size_t way = r_dcache_cc_way.read();
4927	size_t set = r_dcache_cc_set.read();
4928
4929	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4930	{
4931	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4932	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4933	r_dcache_tlb_inval_set = 0;
4934	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4935	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4936	break;
4937	}
4938
4939	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4940	{
4941	r_itlb.reset();
4942	r_dtlb.reset();
4943	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4944
4945	#if DEBUG_DCACHE
4946	if (m_debug_dcache_fsm)
4947	{
4948	std::cout << " <PROC " << name()
4949	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4950	}
4951	#endif
4952	}
4953
4954	assert(not r_dcache_cc_send_req.read() &&
4955	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4956	"must not be set");
4957
4958	// Switch slot state to ZOMBI and send CLEANUP command
4959	r_dcache.write_dir(way,
4960	set,
4961	CACHE_SLOT_STATE_ZOMBI);
4962
4963	// coherence request completed
4964	r_cc_receive_dcache_req = false;
4965	r_dcache_cc_send_req = true;
4966	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4967	r_dcache_cc_send_way = r_dcache_cc_way.read();
4968	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4969	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4970
4971	#if DEBUG_DCACHE
4972	if (m_debug_dcache_fsm)
4973	{
4974	std::cout << " <PROC " << name()
4975	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4976	<< " / WAY = " << way
4977	<< " / SET = " << set << std::endl;
4978	}
4979	#endif
4980	break;
4981	}
4982	///////////////////
4983	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4984	// after possible invalidation of copies in TLBs
4985	{
4986	size_t word = r_dcache_cc_word.read();
4987	size_t way = r_dcache_cc_way.read();
4988	size_t set = r_dcache_cc_set.read();
4989
4990	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4991	{
4992	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4993	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4994	r_dcache_tlb_inval_set = 0;
4995	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4996	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4997
4998	break;
4999	}
5000
5001	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
5002	{
5003	r_itlb.reset();
5004	r_dtlb.reset();
5005	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
5006
5007	#if DEBUG_DCACHE
5008	if (m_debug_dcache_fsm)
5009	{
5010	std::cout << " <PROC " << name()
5011	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
5012	}
5013	#endif
5014	}
5015
5016	assert (not r_dcache_cc_send_req.read() &&
5017	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
5018	"must not be set");
5019
5020	if (not r_cc_receive_updt_fifo_be.rok()) break;
5021
5022	if (r_dcache_cc_need_write.read())
5023	{
5024
5025	#ifdef INSTRUMENTATION
5026	m_cpt_dcache_data_write++;
5027	#endif
5028	r_dcache.write(way,
5029	set,
5030	word,
5031	r_cc_receive_updt_fifo_data.read(),
5032	r_cc_receive_updt_fifo_be.read());
5033
5034	r_dcache_cc_word = word + 1;
5035
5036	#if DEBUG_DCACHE
5037	if (m_debug_dcache_fsm)
5038	{
5039	std::cout << " <PROC " << name()
5040	<< " DCACHE_CC_UPDT> Write one word" << std::dec
5041	<< " / WAY = " << way
5042	<< " / SET = " << set
5043	<< " / WORD = " << word
5044	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
5045	}
5046	#endif
5047	}
5048
5049	if (r_cc_receive_updt_fifo_eop.read()) // last word
5050	{
5051	// no need to write in the cache anymore
5052	r_dcache_cc_need_write = false;
5053
5054	// coherence request completed
5055	r_cc_receive_dcache_req = false;
5056
5057	// request multicast acknowledgement
5058	r_dcache_cc_send_req = true;
5059	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5060	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
5061	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
5062	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5063	}
5064
5065	//consume fifo if not eop
5066	cc_receive_updt_fifo_get = true;
5067
5068	break;
5069	}
5070	///////////////////////////
5071	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
5072	// It makes assumption: m_itlb_sets == m_dtlb_sets
5073	// All ways are handled in parallel.
5074	// We enter this state when a DCACHE line is modified,
5075	// and there is a copy in itlb or dtlb.
5076	// It can be caused by:
5077	// - a coherence inval or updt transaction,
5078	// - a line inval caused by a cache miss
5079	// - a processor XTN inval request,
5080	// - a WRITE hit,
5081	// - a Dirty bit update
5082	// Input arguments are:
5083	// - r_dcache_tlb_inval_line
5084	// - r_dcache_tlb_inval_set
5085	// - r_dcache_fsm_scan_save
5086	{
5087	paddr_t line = r_dcache_tlb_inval_line.read();
5088	size_t set = r_dcache_tlb_inval_set.read();
5089	size_t way;
5090	bool ok;
5091
5092	for (way = 0; way < m_itlb_ways; way++)
5093	{
5094	ok = r_itlb.inval(line, way, set);
5095
5096	#if DEBUG_DCACHE
5097	if (m_debug_dcache_fsm and ok)
5098	{
5099	std::cout << " <PROC " << name()
5100	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
5101	<< " line = " << line << std::dec
5102	<< " / set = " << set
5103	<< " / way = " << way << std::endl;
5104	}
5105	#endif
5106	}
5107
5108	for (way = 0; way < m_dtlb_ways; way++)
5109	{
5110	ok = r_dtlb.inval( line, way, set);
5111
5112	#if DEBUG_DCACHE
5113	if (m_debug_dcache_fsm and ok)
5114	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
5115	<< " Invalidate DTLB entry" << std::hex
5116	<< " / line = " << line << std::dec
5117	<< " / set = " << set
5118	<< " / way = " << way << std::endl;
5119	#endif
5120	}
5121
5122	// return to the calling state when TLB inval completed
5123	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
5124	{
5125	r_dcache_fsm = r_dcache_fsm_scan_save.read();
5126	}
5127	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
5128	break;
5129	}
5130	} // end switch r_dcache_fsm
5131
5132	///////////////// wbuf update ///////////////////////////////////////////////////////
5133	r_wbuf.update();
5134
5135	///////////////// llsc update ///////////////////////////////////////////////////////
5136	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
5137	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
5138
5139	//////////////// test processor frozen //////////////////////////////////////////////
5140	// The simulation exit if the number of consecutive frozen cycles
5141	// is larger than the m_max_frozen_cycles (constructor parameter)
5142	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
5143	{
5144	m_cpt_frz_cycles++; // used for instrumentation
5145	m_cpt_stop_simulation++; // used for debug
5146	if (m_cpt_stop_simulation > m_max_frozen_cycles)
5147	{
5148	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
5149	<< " stop at cycle " << m_cpt_total_cycles << std::endl
5150	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
5151	<< std::endl;
5152	r_iss.dump();
5153	exit(1);
5154	}
5155	}
5156	else
5157	{
5158	m_cpt_stop_simulation = 0;
5159	}
5160
5161	/////////// execute one iss cycle /////////////////////////////////
5162	{
5163	uint32_t it = 0;
5164	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
5165	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
5166	}
5167
5168	////////////////////////////////////////////////////////////////////////////
5169	// The VCI_CMD FSM controls the following ressources:
5170	// - r_vci_cmd_fsm
5171	// - r_vci_cmd_min
5172	// - r_vci_cmd_max
5173	// - r_vci_cmd_cpt
5174	// - r_vci_cmd_imiss_prio
5175	// - wbuf (reset)
5176	// - r_icache_miss_req (reset)
5177	// - r_icache_unc_req (reset)
5178	// - r_dcache_vci_miss_req (reset)
5179	// - r_dcache_vci_unc_req (reset)
5180	// - r_dcache_vci_ll_req (reset)
5181	// - r_dcache_vci_sc_req (reset in case of local sc fail)
5182	// - r_dcache_vci_cas_req (reset)
5183	//
5184	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
5185	// There are 8 request types, with the following priorities :
5186	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
5187	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
5188	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
5189	// 4 - Instruction Uncachable : r_icache_unc_req
5190	// 5 - Data Write : r_wbuf.rok()
5191	// 6 - Data Linked Load : r_dcache_vci_ll_req
5192	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
5193	// 8 - Compare And Swap : r_dcache_vci_cas_req
5194	//
5195	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
5196	// and the VCI_RSP_FSM are fully desynchronized.
5197	//
5198	// VCI formats:
5199	// According to the VCI advanced specification, all read requests packets
5200	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
5201	// are one word packets.
5202	// For write burst packets, all words are in the same cache line,
5203	// and addresses must be contiguous (the BE field is 0 in case of "holes").
5204	// The sc command packet implements actually a compare-and-swap mechanism
5205	// and the packet contains two flits.
5206	////////////////////////////////////////////////////////////////////////////////////
5207
5208
5209	switch (r_vci_cmd_fsm.read())
5210	{
5211	//////////////
5212	case CMD_IDLE:
5213	{
5214	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5215	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5216	// to check a possible pending write on the same cache line.
5217	// As there is only one possible access per cycle to write buffer, we implement
5218	// a round-robin priority between DCACHE and ICACHE for this access,
5219	// using the r_vci_cmd_imiss_prio flip-flop.
5220
5221	size_t wbuf_min;
5222	size_t wbuf_max;
5223
5224	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5225	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5226
5227	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5228	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5229
5230	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
5231	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5232
5233	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
5234	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5235
5236	bool icache_miss_req = r_icache_miss_req.read() and
5237	(not (r_dcache_vci_miss_req.read() or
5238	r_dcache_vci_ll_req.read() or
5239	r_dcache_vci_cas_req.read() or
5240	r_dcache_vci_sc_req.read()) or
5241	r_vci_cmd_imiss_prio.read());
5242
5243	// 1 - Data unc write
5244	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
5245	{
5246	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
5247	r_dcache_vci_unc_req = false;
5248	}
5249	// 2 data read miss
5250	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5251	{
5252	r_vci_cmd_fsm = CMD_DATA_MISS;
5253	r_dcache_vci_miss_req = false;
5254	r_vci_cmd_imiss_prio = true;
5255	}
5256	// 3 - Data Read Uncachable
5257	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
5258	{
5259	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
5260	r_dcache_vci_unc_req = false;
5261	}
5262	// 4 - Data Linked Load
5263	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5264	{
5265	r_vci_cmd_fsm = CMD_DATA_LL;
5266	r_dcache_vci_ll_req = false;
5267	r_vci_cmd_imiss_prio = true;
5268	}
5269	// 5 - Instruction Miss
5270	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
5271	{
5272	r_vci_cmd_fsm = CMD_INS_MISS;
5273	r_icache_miss_req = false;
5274	r_vci_cmd_imiss_prio = false;
5275	}
5276	// 6 - Instruction Uncachable
5277	else if (r_icache_unc_req.read())
5278	{
5279	r_vci_cmd_fsm = CMD_INS_UNC;
5280	r_icache_unc_req = false;
5281	}
5282	// 7 - Data Write
5283	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
5284	{
5285	r_vci_cmd_fsm = CMD_DATA_WRITE;
5286	r_vci_cmd_cpt = wbuf_min;
5287	r_vci_cmd_min = wbuf_min;
5288	r_vci_cmd_max = wbuf_max;
5289	}
5290	// 8 - Data Store Conditionnal
5291	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5292	{
5293	r_vci_cmd_fsm = CMD_DATA_SC;
5294	r_dcache_vci_sc_req = false;
5295	r_vci_cmd_imiss_prio = true;
5296	r_vci_cmd_cpt = 0;
5297	}
5298	// 9 - Compare And Swap
5299	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5300	{
5301	r_vci_cmd_fsm = CMD_DATA_CAS;
5302	r_dcache_vci_cas_req = false;
5303	r_vci_cmd_imiss_prio = true;
5304	r_vci_cmd_cpt = 0;
5305	}
5306
5307	#if DEBUG_CMD
5308	if (m_debug_cmd_fsm )
5309	{
5310	std::cout << " <PROC " << name() << " CMD_IDLE>"
5311	<< " / dmiss_req = " << dcache_miss_req
5312	<< " / imiss_req = " << icache_miss_req
5313	<< std::endl;
5314	}
5315	#endif
5316	break;
5317	}
5318	////////////////////
5319	case CMD_DATA_WRITE:
5320	{
5321	if (p_vci.cmdack.read())
5322	{
5323	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5324	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5325	{
5326	r_vci_cmd_fsm = CMD_IDLE;
5327	r_wbuf.sent();
5328	}
5329	}
5330	break;
5331	}
5332	/////////////////
5333	case CMD_DATA_SC:
5334	case CMD_DATA_CAS:
5335	{
5336	// The CAS and SC VCI commands contain two flits
5337	if (p_vci.cmdack.read())
5338	{
5339	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5340	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5341	}
5342	break;
5343	}
5344	//////////////////
5345	case CMD_INS_MISS:
5346	case CMD_INS_UNC:
5347	case CMD_DATA_MISS:
5348	case CMD_DATA_UNC_READ:
5349	case CMD_DATA_UNC_WRITE:
5350	case CMD_DATA_LL:
5351	{
5352	// all read VCI commands contain one single flit
5353	if (p_vci.cmdack.read()) {
5354	r_vci_cmd_fsm = CMD_IDLE;
5355	}
5356	break;
5357	}
5358
5359	} // end switch r_vci_cmd_fsm
5360
5361	//////////////////////////////////////////////////////////////////////////
5362	// The VCI_RSP FSM controls the following ressources:
5363	// - r_vci_rsp_fsm:
5364	// - r_vci_rsp_fifo_icache (push)
5365	// - r_vci_rsp_fifo_dcache (push)
5366	// - r_vci_rsp_data_error (set)
5367	// - r_vci_rsp_ins_error (set)
5368	// - r_vci_rsp_cpt
5369	// - r_dcache_vci_sc_req (reset when SC response recieved)
5370	//
5371	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5372	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5373	// to identify the transactions.
5374	//
5375	// VCI vormat:
5376	// This component checks the response packet length and accepts only
5377	// single word packets for write response packets.
5378	//
5379	// Error handling:
5380	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5381	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5382	// flip_flop and the error is signaled by the DCACHE FSM.
5383	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5384	// flip_flop and the error is signaled by the ICACHE FSM.
5385	// In case of Cleanup Error, the simulation stops with an error message...
5386	//////////////////////////////////////////////////////////////////////////
5387
5388	switch (r_vci_rsp_fsm.read())
5389	{
5390	//////////////
5391	case RSP_IDLE:
5392	{
5393	if (p_vci.rspval.read())
5394	{
5395	r_vci_rsp_cpt = 0;
5396
5397	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
5398	{
5399	r_vci_rsp_fsm = RSP_DATA_UNC;
5400	}
5401	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
5402	{
5403	// debug: verify that the available response concerns the current transaction.
5404	assert(r_dcache_wdt_timeout.read() == p_vci.rtrdid.read());
5405
5406	r_vci_rsp_fsm = RSP_DATA_MISS;
5407	}
5408	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
5409	{
5410	r_vci_rsp_fsm = RSP_INS_UNC;
5411	}
5412	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
5413	{
5414	r_vci_rsp_fsm = RSP_INS_MISS;
5415	}
5416	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
5417	{
5418	r_vci_rsp_fsm = RSP_DATA_WRITE;
5419	}
5420	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
5421	{
5422	r_vci_rsp_fsm = RSP_DATA_UNC;
5423	}
5424	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
5425	{
5426	r_vci_rsp_fsm = RSP_DATA_LL;
5427	}
5428	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
5429	{
5430	r_vci_rsp_fsm = RSP_DATA_UNC;
5431	}
5432	else
5433	{
5434	assert(false and "Unexpected VCI response");
5435	}
5436	}
5437	break;
5438	}
5439	//////////////////
5440	case RSP_INS_MISS:
5441	{
5442	if (p_vci.rspval.read())
5443	{
5444	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5445	{
5446	r_vci_rsp_ins_error = true;
5447	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5448	}
5449	else // no error reported
5450	{
5451	if (r_vci_rsp_fifo_icache.wok())
5452	{
5453	if (r_vci_rsp_cpt.read() >= m_icache_words)
5454	{
5455	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5456	<< " VCI response packet too long "
5457	<< " for instruction miss" << std::endl;
5458	exit(0);
5459	}
5460	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5461	vci_rsp_fifo_icache_put = true,
5462	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5463	if (p_vci.reop.read())
5464	{
5465	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
5466	{
5467	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5468	<< " VCI response packet too short"
5469	<< " for instruction miss" << std::endl;
5470	exit(0);
5471	}
5472	r_vci_rsp_fsm = RSP_IDLE;
5473	}
5474	}
5475	}
5476	}
5477	break;
5478	}
5479	/////////////////
5480	case RSP_INS_UNC:
5481	{
5482	if (p_vci.rspval.read())
5483	{
5484	assert(p_vci.reop.read() and
5485	"illegal VCI response packet for uncachable instruction");
5486
5487	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5488	{
5489	r_vci_rsp_ins_error = true;
5490	r_vci_rsp_fsm = RSP_IDLE;
5491	}
5492	else // no error reported
5493	{
5494	if (r_vci_rsp_fifo_icache.wok())
5495	{
5496	vci_rsp_fifo_icache_put = true;
5497	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5498	r_vci_rsp_fsm = RSP_IDLE;
5499	}
5500	}
5501	}
5502	break;
5503	}
5504	///////////////////
5505	case RSP_DATA_MISS:
5506	{
5507	if (p_vci.rspval.read())
5508	{
5509	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5510	{
5511	r_vci_rsp_data_error = true;
5512	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5513	}
5514	else // no error reported
5515	{
5516	if (r_vci_rsp_fifo_dcache.wok())
5517	{
5518	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
5519	"The VCI response packet for data miss is too long");
5520
5521	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5522	vci_rsp_fifo_dcache_put = true,
5523	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5524	if (p_vci.reop.read())
5525	{
5526	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5527	"The VCI response packet for data miss is too short");
5528
5529	r_vci_rsp_fsm = RSP_IDLE;
5530	}
5531	}
5532	}
5533	}
5534	break;
5535	}
5536	//////////////////
5537	case RSP_DATA_UNC:
5538	{
5539	if (p_vci.rspval.read())
5540	{
5541	assert(p_vci.reop.read() and
5542	"illegal VCI response packet for uncachable read data");
5543
5544	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5545	{
5546	r_vci_rsp_data_error = true;
5547	r_vci_rsp_fsm = RSP_IDLE;
5548	}
5549	else // no error reported
5550	{
5551	if (r_vci_rsp_fifo_dcache.wok())
5552	{
5553	vci_rsp_fifo_dcache_put = true;
5554	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5555	r_vci_rsp_fsm = RSP_IDLE;
5556	}
5557	}
5558	}
5559	break;
5560	}
5561	/////////////////
5562	case RSP_DATA_LL:
5563	{
5564	if (p_vci.rspval.read())
5565	{
5566	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5567	{
5568	r_vci_rsp_data_error = true;
5569	r_vci_rsp_fsm = RSP_IDLE;
5570	break;
5571	}
5572	if (r_vci_rsp_cpt.read() == 0) //first flit
5573	{
5574	if (r_vci_rsp_fifo_dcache.wok())
5575	{
5576	assert(!p_vci.reop.read() &&
5577	"illegal VCI response packet for LL");
5578	vci_rsp_fifo_dcache_put = true;
5579	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5580	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5581	}
5582	break;
5583	}
5584	else // last flit
5585	{
5586	if (r_vci_rsp_fifo_dcache.wok())
5587	{
5588	assert(p_vci.reop.read() &&
5589	"illegal VCI response packet for LL");
5590	vci_rsp_fifo_dcache_put = true;
5591	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5592	r_vci_rsp_fsm = RSP_IDLE;
5593	}
5594	break;
5595	}
5596	}
5597	break;
5598	}
5599	////////////////////
5600	case RSP_DATA_WRITE:
5601	{
5602	if (p_vci.rspval.read())
5603	{
5604	assert(p_vci.reop.read() and
5605	"a VCI response packet must contain one flit for a write transaction");
5606
5607	r_vci_rsp_fsm = RSP_IDLE;
5608	uint32_t wbuf_index = p_vci.rtrdid.read();
5609	r_wbuf.completed(wbuf_index);
5610	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
5611	}
5612	break;
5613	}
5614	} // end switch r_vci_rsp_fsm
5615
5616	/////////////////////////////////////////////////////////////////////////////////////
5617	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5618	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5619	// and ICACHE FSM) that are served with a round-robin priority.
5620	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5621	// soon as the request has been sent.
5622	/////////////////////////////////////////////////////////////////////////////////////
5623	switch (r_cc_send_fsm.read())
5624	{
5625	///////////////////////////
5626	case CC_SEND_IDLE:
5627	{
5628	///////////////////////////////////////////////////////
5629	// handling round robin between icache and dcache : //
5630	// we first check for the last client and listen for //
5631	// a request of the other, then update the client //
5632	// r_cc_send_last_client : 0 dcache / 1 icache
5633	///////////////////////////////////////////////////////
5634	bool update_last_client = r_cc_send_last_client.read();
5635	if (r_cc_send_last_client.read() == 0) // last client was dcache
5636	{
5637	if (r_icache_cc_send_req.read()) // request from icache
5638	update_last_client = 1; // update last client to icache
5639	}
5640	else // last client was icache
5641	{
5642	if (r_dcache_cc_send_req.read()) // request from dcache
5643	update_last_client = 0; // update last client to dcache
5644	}
5645	r_cc_send_last_client = update_last_client;
5646
5647	// if there is an actual request
5648	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5649	{
5650	// the new client is dcache and has a cleanup request
5651	if ((update_last_client == 0) and
5652	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5653	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5654	// the new client is dcache and has a multi acknowledgement request
5655	else if ((update_last_client == 0) and
5656	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5657	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5658	// the new client is icache and has a cleanup request
5659	else if ((update_last_client == 1) and
5660	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5661	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5662	// the new client is icache and has a multi acknowledgement request
5663	else if ((update_last_client == 1) and
5664	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5665	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5666	}
5667	break;
5668	}
5669	///////////////////////////
5670	case CC_SEND_CLEANUP_1:
5671	{
5672	// wait for the first flit to be consumed
5673	if (p_dspin_p2m.read.read())
5674	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5675
5676	break;
5677	}
5678	///////////////////////////
5679	case CC_SEND_CLEANUP_2:
5680	{
5681	// wait for the second flit to be consumed
5682	if (p_dspin_p2m.read.read())
5683	{
5684	if (r_cc_send_last_client.read() == 0) // dcache active request
5685	r_dcache_cc_send_req = false; // reset dcache request
5686	else // icache active request
5687	r_icache_cc_send_req = false; // reset icache request
5688
5689	// go back to idle state
5690	r_cc_send_fsm = CC_SEND_IDLE;
5691	}
5692	break;
5693	}
5694	///////////////////////////
5695	case CC_SEND_MULTI_ACK:
5696	{
5697	// wait for the flit to be consumed
5698	if (p_dspin_p2m.read.read())
5699	{
5700	if (r_cc_send_last_client.read() == 0) // dcache active request
5701	r_dcache_cc_send_req = false; // reset dcache request
5702	else // icache active request
5703	r_icache_cc_send_req = false; // reset icache request
5704	// go back to idle state
5705	r_cc_send_fsm = CC_SEND_IDLE;
5706	}
5707	break;
5708	}
5709	} // end switch CC_SEND FSM
5710
5711	///////////////////////////////////////////////////////////////////////////////
5712	// CC_RECEIVE FSM
5713	// This FSM receive all coherence packets on a DSPIN40 port.
5714	// There is 5 packet types:
5715	// - CC_DATA_INVAL : DCACHE invalidate request
5716	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5717	// - CC_INST_INVAL : ICACHE invalidate request
5718	// - CC_INST_UPDT : ICACHE update request (multi-words)
5719	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5720	//////////////////////////////////////////////////////////////////////////////
5721	switch (r_cc_receive_fsm.read())
5722	{
5723	/////////////////////
5724	case CC_RECEIVE_IDLE:
5725	{
5726	// a coherence request has arrived
5727	if (p_dspin_m2p.write.read())
5728	{
5729	// initialize dspin received data
5730	uint64_t receive_data = p_dspin_m2p.data.read();
5731	// initialize coherence packet type
5732	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5733	DspinDhccpParam::M2P_TYPE);
5734	// test for a broadcast
5735	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5736	{
5737	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5738	}
5739	// test for a multi updt
5740	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5741	{
5742	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5743	}
5744	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5745	{
5746	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5747	}
5748	// test for a multi inval
5749	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5750	{
5751	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5752	}
5753	else
5754	{
5755	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5756	}
5757	}
5758	break;
5759	}
5760	///////////////////////////////
5761	case CC_RECEIVE_BRDCAST_HEADER:
5762	{
5763	// no actual data in the HEADER, just skip to second flit
5764	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5765	break;
5766	}
5767	//////////////////////////////
5768	case CC_RECEIVE_BRDCAST_NLINE:
5769	{
5770	// initialize dspin received data
5771	uint64_t receive_data = p_dspin_m2p.data.read();
5772	// wait for both dcache and icache to take the request
5773	// TODO maybe we need to wait for both only to leave the state, but
5774	// not to actually post a request to an available cache => need a
5775	// flip_flop to check that ?
5776	if (not (r_cc_receive_icache_req.read()) and
5777	not (r_cc_receive_dcache_req.read()) and
5778	(p_dspin_m2p.write.read()))
5779	{
5780	// request dcache to handle the BROADCAST
5781	r_cc_receive_dcache_req = true;
5782	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5783	DspinDhccpParam::BROADCAST_NLINE);
5784	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5785	// request icache to handle the BROADCAST
5786	r_cc_receive_icache_req = true;
5787	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5788	DspinDhccpParam::BROADCAST_NLINE);
5789	r_cc_receive_icache_type = CC_TYPE_INVAL;
5790	// get back to idle state
5791	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5792	break;
5793	}
5794	// keep waiting for the caches to accept the request
5795	break;
5796	}
5797	/////////////////////////////
5798	case CC_RECEIVE_DATA_INVAL_HEADER:
5799	{
5800	// sample updt tab index in the HEADER, then skip to second flit
5801	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5802	break;
5803	}
5804	/////////////////////////////
5805	case CC_RECEIVE_INS_INVAL_HEADER:
5806	{
5807	// sample updt tab index in the HEADER, then skip to second flit
5808	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5809	break;
5810	}
5811	////////////////////////////
5812	case CC_RECEIVE_DATA_INVAL_NLINE:
5813	{
5814	// sample nline in the second flit
5815	uint64_t receive_data = p_dspin_m2p.data.read();
5816	// for data INVAL, wait for dcache to take the request
5817	if (p_dspin_m2p.write.read() and
5818	not r_cc_receive_dcache_req.read())
5819	{
5820	// request dcache to handle the INVAL
5821	r_cc_receive_dcache_req = true;
5822	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5823	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5824	// get back to idle state
5825	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5826	break;
5827	}
5828	break;
5829	}
5830	//////////////////////////////
5831	case CC_RECEIVE_INS_INVAL_NLINE:
5832	{
5833	// sample nline in the second flit
5834	uint64_t receive_data = p_dspin_m2p.data.read();
5835	// for ins INVAL, wait for icache to take the request
5836	if (p_dspin_m2p.write.read() and
5837	not r_cc_receive_icache_req.read())
5838	{
5839	// request icache to handle the INVAL
5840	r_cc_receive_icache_req = true;
5841	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5842	r_cc_receive_icache_type = CC_TYPE_INVAL;
5843	// get back to idle state
5844	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5845	break;
5846	}
5847	break;
5848	}
5849	////////////////////////////
5850	case CC_RECEIVE_DATA_UPDT_HEADER:
5851	{
5852	// sample updt tab index in the HEADER, than skip to second flit
5853	uint64_t receive_data = p_dspin_m2p.data.read();
5854	// for data INVAL, wait for dcache to take the request and fifo to
5855	// be empty
5856	if (not r_cc_receive_dcache_req.read())
5857	{
5858	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5859	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
5860	break;
5861	}
5862	break;
5863	}
5864	////////////////////////////
5865	case CC_RECEIVE_INS_UPDT_HEADER:
5866	{
5867	// sample updt tab index in the HEADER, than skip to second flit
5868	uint64_t receive_data = p_dspin_m2p.data.read();
5869	// for ins INVAL, wait for icache to take the request and fifo to be
5870	// empty
5871	if (not r_cc_receive_icache_req.read())
5872	{
5873	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5874	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
5875	break;
5876	}
5877	// keep waiting for the correct cache to accept the request
5878	break;
5879	}
5880	///////////////////////////
5881	case CC_RECEIVE_DATA_UPDT_NLINE:
5882	{
5883	// sample nline and word index in the second flit
5884	uint64_t receive_data = p_dspin_m2p.data.read();
5885	// for data INVAL, wait for dcache to take the request and fifo to
5886	// be empty
5887	if (r_cc_receive_updt_fifo_be.empty() and
5888	p_dspin_m2p.write.read())
5889	{
5890	r_cc_receive_dcache_req = true;
5891	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5892	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5893	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5894	// get back to idle state
5895	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
5896	break;
5897	}
5898	break;
5899	}
5900	////////////////////////////
5901	case CC_RECEIVE_INS_UPDT_NLINE:
5902	{
5903	// sample nline and word index in the second flit
5904	uint64_t receive_data = p_dspin_m2p.data.read();
5905	// for ins INVAL, wait for icache to take the request and fifo to be
5906	// empty
5907	if (r_cc_receive_updt_fifo_be.empty() and
5908	p_dspin_m2p.write.read())
5909	{
5910	r_cc_receive_icache_req = true;
5911	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5912	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5913	r_cc_receive_icache_type = CC_TYPE_UPDT;
5914	// get back to idle state
5915	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
5916	break;
5917	}
5918	break;
5919	}
5920	//////////////////////////
5921	case CC_RECEIVE_DATA_UPDT_DATA:
5922	{
5923	// wait for the fifo
5924	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5925	{
5926	uint64_t receive_data = p_dspin_m2p.data.read();
5927	bool receive_eop = p_dspin_m2p.eop.read();
5928	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5929	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5930	cc_receive_updt_fifo_eop = receive_eop;
5931	cc_receive_updt_fifo_put = true;
5932	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5933	}
5934	break;
5935	}
5936	//////////////////////////
5937	case CC_RECEIVE_INS_UPDT_DATA:
5938	{
5939	// wait for the fifo
5940	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5941	{
5942	uint64_t receive_data = p_dspin_m2p.data.read();
5943	bool receive_eop = p_dspin_m2p.eop.read();
5944	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5945	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5946	cc_receive_updt_fifo_eop = receive_eop;
5947	cc_receive_updt_fifo_put = true;
5948	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5949	}
5950	break;
5951	}
5952
5953	} // end switch CC_RECEIVE FSM
5954
5955	///////////////// DSPIN CLACK interface ///////////////
5956
5957	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5958	DspinDhccpParam::CLACK_TYPE);
5959
5960	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5961	DspinDhccpParam::CLACK_WAY);
5962
5963	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5964	DspinDhccpParam::CLACK_SET);
5965
5966	bool dspin_clack_get = false;
5967	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
5968	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
5969
5970	if (r_dspin_clack_req.read())
5971	{
5972	// CLACK DATA: Send request to DCACHE FSM
5973	if (dcache_clack_request and not r_dcache_clack_req.read())
5974	{
5975	r_dcache_clack_req = true;
5976	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
5977	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
5978	dspin_clack_get = true;
5979	}
5980
5981	// CLACK INST: Send request to ICACHE FSM
5982	else if (icache_clack_request and not r_icache_clack_req.read())
5983	{
5984	r_icache_clack_req = true;
5985	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5986	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5987	dspin_clack_get = true;
5988	}
5989	}
5990	else
5991	{
5992	dspin_clack_get = true;
5993	}
5994
5995	if (dspin_clack_get)
5996	{
5997	r_dspin_clack_req = p_dspin_clack.write.read();
5998	r_dspin_clack_flit = p_dspin_clack.data.read();
5999	}
6000
6001	///////////////// Response FIFOs update //////////////////////
6002	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
6003	vci_rsp_fifo_icache_put,
6004	vci_rsp_fifo_icache_data);
6005
6006	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
6007	vci_rsp_fifo_dcache_put,
6008	vci_rsp_fifo_dcache_data);
6009
6010	///////////////// updt FIFO update //////////////////////
6011	//TODO check this
6012	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
6013	cc_receive_updt_fifo_put,
6014	cc_receive_updt_fifo_be);
6015	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
6016	cc_receive_updt_fifo_put,
6017	cc_receive_updt_fifo_data);
6018	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
6019	cc_receive_updt_fifo_put,
6020	cc_receive_updt_fifo_eop);
6021
6022	} // end transition()
6023
6024	///////////////////////
6025	tmpl(void)::genMoore()
6026	///////////////////////
6027	{
6028
6029	// VCI initiator command on the direct network
6030	// it depends on the CMD FSM state
6031
6032	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
6033	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
6034
6035	p_vci.pktid = 0;
6036	p_vci.srcid = m_srcid;
6037	p_vci.cons = is_sc_or_cas;
6038	p_vci.contig = not is_sc_or_cas;
6039	p_vci.wrap = false;
6040	p_vci.clen = 0;
6041	p_vci.cfixed = false;
6042
6043	if (m_monitor_ok) {
6044	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
6045	if (((p_vci.address.read()) >= m_monitor_base) and
6046	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
6047	std::cout << "CC_VCACHE Monitor " << name() << std::hex
6048	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
6049	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
6050	<< " : address = " << p_vci.address.read()
6051	<< " / be = " << p_vci.be.read();
6052	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
6053	std::cout << " / data = " << p_vci.wdata.read();
6054	}
6055	std::cout << std::dec << std::endl;
6056	}
6057	}
6058	}
6059
6060	switch (r_vci_cmd_fsm.read()) {
6061
6062	case CMD_IDLE:
6063	p_vci.cmdval = false;
6064	p_vci.address = 0;
6065	p_vci.wdata = 0;
6066	p_vci.be = 0;
6067	p_vci.trdid = 0;
6068	p_vci.pktid = 0;
6069	p_vci.plen = 0;
6070	p_vci.cmd = vci_param::CMD_NOP;
6071	p_vci.eop = false;
6072	break;
6073
6074	case CMD_INS_MISS:
6075	p_vci.cmdval = true;
6076	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
6077	p_vci.wdata = 0;
6078	p_vci.be = 0xF;
6079	p_vci.trdid = 0;
6080	p_vci.pktid = TYPE_READ_INS_MISS;
6081	p_vci.plen = m_icache_words << 2;
6082	p_vci.cmd = vci_param::CMD_READ;
6083	p_vci.eop = true;
6084	break;
6085
6086	case CMD_INS_UNC:
6087	p_vci.cmdval = true;
6088	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
6089	p_vci.wdata = 0;
6090	p_vci.be = 0xF;
6091	p_vci.trdid = 0;
6092	p_vci.pktid = TYPE_READ_INS_UNC;
6093	p_vci.plen = 4;
6094	p_vci.cmd = vci_param::CMD_READ;
6095	p_vci.eop = true;
6096	break;
6097
6098	case CMD_DATA_MISS:
6099	p_vci.cmdval = true;
6100	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
6101	p_vci.wdata = 0;
6102	p_vci.be = 0xF;
6103	p_vci.trdid = r_dcache_vci_miss_trdid.read();
6104	p_vci.pktid = TYPE_READ_DATA_MISS;
6105	p_vci.plen = m_dcache_words << 2;
6106	p_vci.cmd = vci_param::CMD_READ;
6107	p_vci.eop = true;
6108	break;
6109
6110	case CMD_DATA_UNC_READ:
6111	p_vci.cmdval = true;
6112	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6113	p_vci.wdata = 0;
6114	p_vci.be = r_dcache_vci_unc_be.read();
6115	p_vci.trdid = 0;
6116	p_vci.pktid = TYPE_DATA_UNC;
6117	p_vci.plen = 4;
6118	p_vci.cmd = vci_param::CMD_READ;
6119	p_vci.eop = true;
6120	break;
6121
6122	case CMD_DATA_UNC_WRITE:
6123	p_vci.cmdval = true;
6124	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6125	p_vci.wdata = r_dcache_vci_wdata.read();
6126	p_vci.be = r_dcache_vci_unc_be.read();
6127	p_vci.trdid = 0;
6128	p_vci.pktid = TYPE_DATA_UNC;
6129	p_vci.plen = 4;
6130	p_vci.cmd = vci_param::CMD_WRITE;
6131	p_vci.eop = true;
6132	break;
6133
6134	case CMD_DATA_WRITE:
6135	p_vci.cmdval = true;
6136	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
6137	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
6138	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
6139	p_vci.trdid = r_wbuf.getIndex();
6140	p_vci.pktid = TYPE_WRITE;
6141	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
6142	p_vci.cmd = vci_param::CMD_WRITE;
6143	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
6144	break;
6145
6146	case CMD_DATA_LL:
6147	p_vci.cmdval = true;
6148	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6149	p_vci.wdata = 0;
6150	p_vci.be = 0xF;
6151	p_vci.trdid = 0;
6152	p_vci.pktid = TYPE_LL;
6153	p_vci.plen = 8;
6154	p_vci.cmd = vci_param::CMD_LOCKED_READ;
6155	p_vci.eop = true;
6156	break;
6157
6158	case CMD_DATA_SC:
6159	p_vci.cmdval = true;
6160	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6161	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
6162	else p_vci.wdata = r_dcache_vci_sc_data.read();
6163	p_vci.be = 0xF;
6164	p_vci.trdid = 0;
6165	p_vci.pktid = TYPE_SC;
6166	p_vci.plen = 8;
6167	p_vci.cmd = vci_param::CMD_NOP;
6168	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6169	break;
6170
6171	case CMD_DATA_CAS:
6172	p_vci.cmdval = true;
6173	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6174	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
6175	else p_vci.wdata = r_dcache_vci_cas_new.read();
6176	p_vci.be = 0xF;
6177	p_vci.trdid = 0;
6178	p_vci.pktid = TYPE_CAS;
6179	p_vci.plen = 8;
6180	p_vci.cmd = vci_param::CMD_NOP;
6181	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6182	break;
6183	} // end switch r_vci_cmd_fsm
6184
6185	// VCI initiator response on the direct network
6186	// it depends on the VCI_RSP FSM
6187
6188	switch (r_vci_rsp_fsm.read())
6189	{
6190	case RSP_DATA_WRITE : p_vci.rspack = true; break;
6191	case RSP_INS_MISS �