1 | |
---|
2 | # -*- python -*- |
---|
3 | |
---|
4 | __id__ = "$Id: vci_mem_cache.sd 295 2013-02-14 15:05:05Z cfuguet $" |
---|
5 | __version__ = "$Revision: 295 $" |
---|
6 | |
---|
7 | Module('caba:reconf:vci_mem_cache', |
---|
8 | classname = 'soclib::caba::VciMemCache', |
---|
9 | |
---|
10 | tmpl_parameters = [ |
---|
11 | parameter.Module('vci_param_int', default = 'caba:vci_param', |
---|
12 | cell_size = parameter.Reference('memc_cell_size_int') |
---|
13 | ), |
---|
14 | parameter.Module('vci_param_ext', default = 'caba:vci_param', |
---|
15 | cell_size = parameter.Reference('memc_cell_size_ext') |
---|
16 | ), |
---|
17 | parameter.Int('memc_dspin_in_width'), |
---|
18 | parameter.Int('memc_dspin_out_width'), |
---|
19 | ], |
---|
20 | |
---|
21 | header_files = [ |
---|
22 | '../source/include/vci_mem_cache.h', |
---|
23 | '../source/include/xram_transaction.h', |
---|
24 | '../source/include/mem_cache_directory.h', |
---|
25 | '../source/include/update_tab.h' |
---|
26 | ], |
---|
27 | |
---|
28 | interface_files = [ |
---|
29 | '../../include/soclib/mem_cache.h', |
---|
30 | ], |
---|
31 | |
---|
32 | implementation_files = [ |
---|
33 | '../source/src/vci_mem_cache.cpp' |
---|
34 | ], |
---|
35 | |
---|
36 | uses = [ |
---|
37 | Uses('caba:base_module'), |
---|
38 | Uses('common:loader'), |
---|
39 | Uses('common:mapping_table'), |
---|
40 | Uses('caba:generic_fifo'), |
---|
41 | Uses('caba:generic_llsc_global_table'), |
---|
42 | Uses('caba:reconf:dspin_dhccp_param') |
---|
43 | ], |
---|
44 | |
---|
45 | ports = [ |
---|
46 | Port('caba:clock_in' , 'p_clk' , auto = 'clock' ), |
---|
47 | Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), |
---|
48 | Port('caba:vci_target' , 'p_vci_tgt'), |
---|
49 | Port('caba:vci_initiator', 'p_vci_ixr'), |
---|
50 | Port('caba:dspin_input', |
---|
51 | 'p_dspin_p2m', |
---|
52 | dspin_data_size = parameter.Reference('memc_dspin_in_width') |
---|
53 | ), |
---|
54 | Port('caba:dspin_output', |
---|
55 | 'p_dspin_m2p', |
---|
56 | dspin_data_size = parameter.Reference('memc_dspin_out_width') |
---|
57 | ), |
---|
58 | Port('caba:dspin_output', |
---|
59 | 'p_dspin_clack', |
---|
60 | dspin_data_size = parameter.Reference('memc_dspin_out_width') |
---|
61 | ), |
---|
62 | ], |
---|
63 | |
---|
64 | instance_parameters = [ |
---|
65 | parameter.Module('mtp', 'common:mapping_table'), |
---|
66 | parameter.Module('mtc', 'common:mapping_table'), |
---|
67 | parameter.Module('mtx', 'common:mapping_table'), |
---|
68 | parameter.IntTab('vci_ixr_index'), |
---|
69 | parameter.IntTab('vci_ini_index'), |
---|
70 | parameter.IntTab('vci_tgt_index'), |
---|
71 | parameter.IntTab('vci_tgt_index_cleanup'), |
---|
72 | parameter.Int ('nways'), |
---|
73 | parameter.Int ('nsets'), |
---|
74 | parameter.Int ('nwords'), |
---|
75 | parameter.Int ('heap_size'), |
---|
76 | ], |
---|
77 | ) |
---|