1 | /////////////////////////////////////////////////////////////////////////////// |
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2 | // File: top.cpp (for tsar_generic_iob platform) |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : august 2013 |
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6 | // This program is released under the GNU public license |
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7 | /////////////////////////////////////////////////////////////////////////////// |
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8 | // This file define a generic TSAR architecture with an IO network emulating |
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9 | // an external bus (i.e. Hypertransport) to access 7 external peripherals: |
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10 | // |
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11 | // - FBUF : Frame Buffer |
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12 | // - MTTY : multi TTY (one channel) |
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13 | // - MNIC : Network controller (up to 2 channels) |
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14 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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15 | // - BDEV : Dlock Device controler (one channel) |
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16 | // - IOPI : HWI to SWI translator. |
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17 | // |
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18 | // The internal physical address space is 40 bits, and the cluster index |
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19 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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20 | // Y is encodes on 4 bits, whatever the actual mesh size. |
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21 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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22 | // |
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23 | // It contains 3 networks: |
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24 | // |
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25 | // 1) the "INT" network supports Read/Write transactions |
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26 | // between processors and L2 caches or peripherals. |
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27 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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28 | // It supports also coherence transactions between L1 & L2 caches. |
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29 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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30 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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31 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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32 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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33 | // 4) the IOX network connects the two IO bridge components to the |
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34 | // 7 external peripheral controllers. |
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35 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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36 | // |
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37 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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38 | // external IOPIC component, that must be configured by the OS to route |
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39 | // these WTI ITQS to one or several internal XICU components. |
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40 | // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] |
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41 | // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] |
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42 | // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] |
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43 | // - IOPIC HWI[8] connected to IRQ_BDEV |
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44 | // - IOPIC HWI[9] connected to IRQ_TTY_RX[0] |
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45 | // - IOPIC HWI[31:9] unused (grounded) |
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46 | // |
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47 | // Besides the external peripherals, each cluster contains one XICU component, |
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48 | // and one multi channels DMA component. |
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49 | // The XICU component is mainly used to handle WTI IRQs, as only 5 HWI IRQs |
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50 | // are connected to XICU in each cluster: |
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51 | // - IRQ_IN[0] : MMC |
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52 | // - IRQ_IN[1] : DMA channel 0 |
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53 | // - IRQ_IN[2] : DMA channel 1 |
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54 | // - IRQ_IN[3] : DMA channel 2 |
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55 | // - IRQ_IN[4] : DMA channel 3 |
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56 | // |
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57 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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58 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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59 | // connected to the three networks (INT, RAM, IOX). |
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60 | // |
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61 | // - It uses two dspin_local_crossbar per cluster to implement the |
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62 | // local interconnect correponding to the INT network. |
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63 | // - It uses three dspin_local_crossbar per cluster to implement the |
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64 | // local interconnect correponding to the coherence INT network. |
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65 | // - It uses two virtual_dspin_router per cluster to implement |
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66 | // the INT network (routing both the direct and coherence trafic). |
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67 | // - It uses two dspin_router per cluster to implement the RAM network. |
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68 | // - It uses the vci_cc_vcache_wrapper. |
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69 | // - It uses the vci_mem_cache. |
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70 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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71 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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72 | // |
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73 | // The TsarIobCluster component is defined in files |
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74 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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75 | // |
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76 | // The main hardware parameters must be defined in the hard_config.h file : |
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77 | // - X_SIZE : number of clusters in a row |
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78 | // - Y_SIZE : number of clusters in a column |
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79 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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80 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (must be 1) |
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81 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) |
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82 | // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) |
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83 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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84 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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85 | // - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs |
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86 | // |
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87 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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88 | // - XRAM_LATENCY : external ram latency |
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89 | // - MEMC_WAYS : L2 cache number of ways |
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90 | // - MEMC_SETS : L2 cache number of sets |
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91 | // - L1_IWAYS |
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92 | // - L1_ISETS |
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93 | // - L1_DWAYS |
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94 | // - L1_DSETS |
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95 | // - BDEV_IMAGE_NAME : file pathname for block device |
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96 | // - NIC_RX_NAME : file pathname for NIC received packets |
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97 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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98 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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99 | // |
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100 | // General policy for 40 bits physical address decoding: |
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101 | // All physical segments base addresses are multiple of 1 Mbytes |
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102 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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103 | // The (x_width + y_width) MSB bits (left aligned) define |
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104 | // the cluster index, and the LADR bits define the local index: |
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105 | // |X_ID|Y_ID| LADR | OFFSET | |
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106 | // | 4 | 4 | 8 | 24 | |
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107 | // |
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108 | // General policy for 14 bits SRCID decoding: |
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109 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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110 | // |X_ID|Y_ID| L_ID | |
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111 | // | 4 | 4 | 6 | |
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112 | ///////////////////////////////////////////////////////////////////////// |
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113 | |
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114 | #include <systemc> |
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115 | #include <sys/time.h> |
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116 | #include <iostream> |
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117 | #include <sstream> |
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118 | #include <cstdlib> |
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119 | #include <cstdarg> |
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120 | #include <stdint.h> |
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121 | |
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122 | #include "gdbserver.h" |
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123 | #include "mapping_table.h" |
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124 | |
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125 | #include "tsar_iob_cluster.h" |
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126 | #include "vci_chbuf_dma.h" |
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127 | #include "vci_multi_tty.h" |
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128 | #include "vci_multi_nic.h" |
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129 | #include "vci_simple_rom.h" |
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130 | #include "vci_block_device_tsar.h" |
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131 | #include "vci_framebuffer.h" |
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132 | #include "vci_iox_network.h" |
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133 | #include "vci_iox_network.h" |
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134 | #include "vci_iopic.h" |
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135 | |
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136 | #include "alloc_elems.h" |
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137 | |
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138 | /////////////////////////////////////////////////// |
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139 | // OS |
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140 | /////////////////////////////////////////////////// |
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141 | #define USE_ALMOS 0 |
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142 | |
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143 | #define almos_bootloader_pathname "bootloader.bin" |
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144 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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145 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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146 | |
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147 | /////////////////////////////////////////////////// |
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148 | // Parallelisation |
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149 | /////////////////////////////////////////////////// |
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150 | #define USE_OPENMP 0 |
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151 | |
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152 | #if USE_OPENMP |
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153 | #include <omp.h> |
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154 | #endif |
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155 | |
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156 | /////////////////////////////////////////////////////////// |
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157 | // DSPIN parameters |
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158 | /////////////////////////////////////////////////////////// |
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159 | |
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160 | #define dspin_int_cmd_width 39 |
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161 | #define dspin_int_rsp_width 32 |
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162 | |
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163 | #define dspin_ram_cmd_width 64 |
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164 | #define dspin_ram_rsp_width 64 |
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165 | |
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166 | /////////////////////////////////////////////////////////// |
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167 | // VCI fields width for the 3 VCI networks |
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168 | /////////////////////////////////////////////////////////// |
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169 | |
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170 | #define vci_cell_width_int 4 |
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171 | #define vci_cell_width_ext 8 |
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172 | |
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173 | #define vci_plen_width 8 |
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174 | #define vci_address_width 40 |
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175 | #define vci_rerror_width 1 |
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176 | #define vci_clen_width 1 |
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177 | #define vci_rflag_width 1 |
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178 | #define vci_srcid_width 14 |
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179 | #define vci_pktid_width 4 |
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180 | #define vci_trdid_width 4 |
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181 | #define vci_wrplen_width 1 |
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182 | |
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183 | //////////////////////////////////////////////////////////// |
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184 | // Main Hardware Parameters values |
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185 | //////////////////////i///////////////////////////////////// |
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186 | |
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187 | #include "hard_config.h" |
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188 | |
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189 | //////////////////////////////////////////////////////////// |
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190 | // Secondary Hardware Parameters values |
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191 | //////////////////////i///////////////////////////////////// |
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192 | |
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193 | #define XMAX X_SIZE |
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194 | #define YMAX Y_SIZE |
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195 | |
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196 | #define XRAM_LATENCY 0 |
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197 | |
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198 | #define MEMC_WAYS 16 |
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199 | #define MEMC_SETS 256 |
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200 | |
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201 | #define L1_IWAYS 4 |
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202 | #define L1_ISETS 64 |
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203 | |
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204 | #define L1_DWAYS 4 |
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205 | #define L1_DSETS 64 |
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206 | |
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207 | #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" |
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208 | |
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209 | #define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" |
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210 | #define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" |
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211 | #define NIC_TIMEOUT 10000 |
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212 | |
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213 | #define NORTH 0 |
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214 | #define SOUTH 1 |
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215 | #define EAST 2 |
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216 | #define WEST 3 |
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217 | |
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218 | #define cluster(x,y) ((y) + ((x) << 4)) |
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219 | |
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220 | //////////////////////////////////////////////////////////// |
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221 | // Software to be loaded in ROM & RAM |
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222 | //////////////////////i///////////////////////////////////// |
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223 | |
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224 | #define BOOT_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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225 | |
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226 | //////////////////////////////////////////////////////////// |
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227 | // DEBUG Parameters default values |
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228 | //////////////////////i///////////////////////////////////// |
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229 | |
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230 | #define MAX_FROZEN_CYCLES 200000 |
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231 | |
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232 | ///////////////////////////////////////////////////////// |
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233 | // Physical segments definition |
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234 | ///////////////////////////////////////////////////////// |
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235 | |
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236 | // All physical segments base addresses and sizes are defined |
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237 | // in the hard_config.h file. For replicated segments, the |
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238 | // base address is incremented by a cluster offset: |
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239 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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240 | |
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241 | //////////////////////////////////////////////////////////////////////// |
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242 | // SRCID definition |
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243 | //////////////////////////////////////////////////////////////////////// |
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244 | // All initiators are in the same indexing space (14 bits). |
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245 | // The SRCID is structured in two fields: |
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246 | // - The 10 MSB bits define the cluster index (left aligned) |
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247 | // - The 4 LSB bits define the local index. |
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248 | // Two different initiators cannot have the same SRCID, but a given |
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249 | // initiator can have two alias SRCIDs: |
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250 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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251 | // and each initiator has one single SRCID. |
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252 | // - External initiators (bdev, cdma) are not replicated, but can be |
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253 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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254 | // They have the same local index, but two different cluster indexes. |
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255 | // |
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256 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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257 | // and external initiators, they must have different local indexes. |
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258 | // Consequence: For a local interconnect, the INI_ID port index |
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259 | // is NOT equal to the SRCID local index, and the local interconnect |
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260 | // must make a translation: SRCID => INI_ID |
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261 | //////////////////////////////////////////////////////////////////////// |
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262 | |
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263 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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264 | #define MDMA_LOCAL_SRCID 0x8 |
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265 | #define IOBX_LOCAL_SRCID 0x9 |
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266 | #define MEMC_LOCAL_SRCID 0xA |
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267 | #define CDMA_LOCAL_SRCID 0xB |
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268 | #define BDEV_LOCAL_SRCID 0xC |
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269 | #define IOPI_LOCAL_SRCID 0xD |
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270 | |
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271 | /////////////////////////////////////////////////////////////////////// |
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272 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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273 | /////////////////////////////////////////////////////////////////////// |
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274 | |
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275 | #define INT_MEMC_TGT_ID 0 |
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276 | #define INT_XICU_TGT_ID 1 |
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277 | #define INT_MDMA_TGT_ID 2 |
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278 | #define INT_BROM_TGT_ID 3 |
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279 | #define INT_IOBX_TGT_ID 4 |
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280 | |
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281 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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282 | #define INT_MDMA_INI_ID (NB_PROCS_MAX) |
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283 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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284 | |
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285 | /////////////////////////////////////////////////////////////////////// |
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286 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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287 | /////////////////////////////////////////////////////////////////////// |
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288 | |
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289 | #define RAM_XRAM_TGT_ID 0 |
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290 | |
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291 | #define RAM_MEMC_INI_ID 0 |
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292 | #define RAM_IOBX_INI_ID 1 |
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293 | |
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294 | /////////////////////////////////////////////////////////////////////// |
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295 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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296 | /////////////////////////////////////////////////////////////////////// |
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297 | |
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298 | #define IOX_FBUF_TGT_ID 0 |
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299 | #define IOX_BDEV_TGT_ID 1 |
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300 | #define IOX_MNIC_TGT_ID 2 |
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301 | #define IOX_CDMA_TGT_ID 3 |
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302 | #define IOX_MTTY_TGT_ID 4 |
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303 | #define IOX_IOPI_TGT_ID 5 |
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304 | #define IOX_IOB0_TGT_ID 6 |
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305 | #define IOX_IOB1_TGT_ID 7 |
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306 | |
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307 | #define IOX_BDEV_INI_ID 0 |
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308 | #define IOX_CDMA_INI_ID 1 |
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309 | #define IOX_IOPI_INI_ID 2 |
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310 | #define IOX_IOB0_INI_ID 3 |
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311 | #define IOX_IOB1_INI_ID 4 |
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312 | |
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313 | //////////////////////////////////////////////////////////////////////// |
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314 | int _main(int argc, char *argv[]) |
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315 | //////////////////////////////////////////////////////////////////////// |
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316 | { |
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317 | using namespace sc_core; |
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318 | using namespace soclib::caba; |
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319 | using namespace soclib::common; |
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320 | |
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321 | |
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322 | char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code |
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323 | size_t ncycles = 1000000000; // simulated cycles |
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324 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image |
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325 | char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file |
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326 | char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file |
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327 | ssize_t threads_nr = 1; // simulator's threads number |
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328 | bool debug_ok = false; // trace activated |
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329 | size_t debug_period = 1; // trace period |
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330 | size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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331 | size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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332 | size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram |
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333 | bool debug_iob = false; // trace iob0 & iob1 when true |
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334 | uint32_t debug_from = 0; // trace start cycle |
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335 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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336 | size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 |
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337 | size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 |
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338 | size_t x_width = 4; // at most 256 clusters |
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339 | size_t y_width = 4; // at most 256 clusters |
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340 | |
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341 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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342 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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343 | |
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344 | ////////////// command line arguments ////////////////////// |
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345 | if (argc > 1) |
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346 | { |
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347 | for (int n = 1; n < argc; n = n + 2) |
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348 | { |
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349 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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350 | { |
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351 | ncycles = strtol(argv[n+1], NULL, 0); |
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352 | } |
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353 | else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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354 | { |
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355 | strcpy(soft_name, argv[n+1]); |
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356 | } |
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357 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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358 | { |
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359 | debug_ok = true; |
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360 | debug_from = strtol(argv[n+1], NULL, 0); |
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361 | } |
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362 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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363 | { |
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364 | strcpy(disk_name, argv[n+1]); |
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365 | } |
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366 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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367 | { |
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368 | debug_memc_id = strtol(argv[n+1], NULL, 0); |
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369 | size_t x = debug_memc_id >> 4; |
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370 | size_t y = debug_memc_id & 0xF; |
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371 | if( (x>=XMAX) || (y>=YMAX) ) |
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372 | { |
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373 | std::cout << "MEMCID parameter does'nt fit XMAX/YMAX" << std::endl; |
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374 | exit(0); |
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375 | } |
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376 | } |
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377 | else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1<argc) ) |
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378 | { |
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379 | debug_xram_id = strtol(argv[n+1], NULL, 0); |
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380 | size_t x = debug_xram_id >> 4; |
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381 | size_t y = debug_xram_id & 0xF; |
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382 | if( (x>=XMAX) || (y>=YMAX) ) |
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383 | { |
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384 | std::cout << "XRAMID parameter does'nt fit XMAX/YMAX" << std::endl; |
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385 | exit(0); |
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386 | } |
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387 | } |
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388 | else if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
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389 | { |
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390 | debug_iob = strtol(argv[n+1], NULL, 0); |
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391 | } |
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392 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
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393 | { |
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394 | debug_proc_id = strtol(argv[n+1], NULL, 0); |
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395 | size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; |
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396 | size_t x = cluster_xy >> 4; |
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397 | size_t y = cluster_xy & 0xF; |
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398 | if( (x>=XMAX) || (y>=YMAX) ) |
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399 | { |
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400 | std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; |
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401 | exit(0); |
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402 | } |
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403 | } |
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404 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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405 | { |
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406 | threads_nr = strtol(argv[n+1], NULL, 0); |
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407 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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408 | } |
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409 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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410 | { |
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411 | frozen_cycles = strtol(argv[n+1], NULL, 0); |
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412 | } |
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413 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
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414 | { |
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415 | debug_period = strtol(argv[n+1], NULL, 0); |
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416 | } |
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417 | else |
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418 | { |
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419 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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420 | std::cout << " The order is not important." << std::endl; |
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421 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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422 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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423 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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424 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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425 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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426 | std::cout << " -THREADS simulator's threads number" << std::endl; |
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427 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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428 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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429 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
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430 | std::cout << " -XRAMID index_xram_to_be_traced" << std::endl; |
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431 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
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432 | std::cout << " -IOB non_zero_value" << std::endl; |
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433 | exit(0); |
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434 | } |
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435 | } |
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436 | } |
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437 | |
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438 | // Activate Distributed Boot (set by environment variable) |
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439 | // When this is activated, every processor boots with its instruction and data |
---|
440 | // physical address extension register initialized to its cluster index |
---|
441 | // (X_LOCAL, Y_LOCAL). To support this feature, a distributed ROM is |
---|
442 | // implemented in each cluster. |
---|
443 | |
---|
444 | const bool distributed_boot = (getenv("DISTRIBUTED_BOOT") != NULL); |
---|
445 | |
---|
446 | // checking hardware parameters |
---|
447 | assert( (XMAX <= 16) and |
---|
448 | "The XMAX parameter cannot be larger than 16" ); |
---|
449 | |
---|
450 | assert( (YMAX <= 16) and |
---|
451 | "The YMAX parameter cannot be larger than 16" ); |
---|
452 | |
---|
453 | assert( (NB_PROCS_MAX <= 8) and |
---|
454 | "The NB_PROCS_MAX parameter cannot be larger than 8" ); |
---|
455 | |
---|
456 | assert( (NB_DMA_CHANNELS <= 4) and |
---|
457 | "The NB_DMA_CHANNELS parameter cannot be larger than 4" ); |
---|
458 | |
---|
459 | assert( (NB_TTY_CHANNELS == 1) and |
---|
460 | "The NB_TTY_CHANNELS parameter must be 1" ); |
---|
461 | |
---|
462 | assert( (NB_NIC_CHANNELS == 2) and |
---|
463 | "The NB_NIC_CHANNELS parameter must be 2" ); |
---|
464 | |
---|
465 | std::cout << std::endl << std::dec |
---|
466 | << " - XMAX = " << XMAX << std::endl |
---|
467 | << " - YMAX = " << YMAX << std::endl |
---|
468 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
469 | << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl |
---|
470 | << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl |
---|
471 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
472 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
473 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
474 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
475 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
476 | << " - DIST_BOOT = " << distributed_boot << std::endl |
---|
477 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
478 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl |
---|
479 | << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; |
---|
480 | |
---|
481 | std::cout << std::endl; |
---|
482 | |
---|
483 | #if USE_OPENMP |
---|
484 | omp_set_dynamic(false); |
---|
485 | omp_set_num_threads(threads_nr); |
---|
486 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
487 | #endif |
---|
488 | |
---|
489 | // Define VciParams objects |
---|
490 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
491 | vci_plen_width, |
---|
492 | vci_address_width, |
---|
493 | vci_rerror_width, |
---|
494 | vci_clen_width, |
---|
495 | vci_rflag_width, |
---|
496 | vci_srcid_width, |
---|
497 | vci_pktid_width, |
---|
498 | vci_trdid_width, |
---|
499 | vci_wrplen_width> vci_param_int; |
---|
500 | |
---|
501 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
502 | vci_plen_width, |
---|
503 | vci_address_width, |
---|
504 | vci_rerror_width, |
---|
505 | vci_clen_width, |
---|
506 | vci_rflag_width, |
---|
507 | vci_srcid_width, |
---|
508 | vci_pktid_width, |
---|
509 | vci_trdid_width, |
---|
510 | vci_wrplen_width> vci_param_ext; |
---|
511 | |
---|
512 | ///////////////////////////////////////////////////////////////////// |
---|
513 | // INT network mapping table |
---|
514 | // - two levels address decoding for commands |
---|
515 | // - two levels srcid decoding for responses |
---|
516 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
517 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
518 | ///////////////////////////////////////////////////////////////////// |
---|
519 | MappingTable maptab_int( vci_address_width, |
---|
520 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
521 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
522 | 0x00FF000000); |
---|
523 | |
---|
524 | for (size_t x = 0; x < XMAX; x++) |
---|
525 | { |
---|
526 | for (size_t y = 0; y < YMAX; y++) |
---|
527 | { |
---|
528 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
529 | << (vci_address_width-x_width-y_width); |
---|
530 | bool config = true; |
---|
531 | bool cacheable = true; |
---|
532 | |
---|
533 | // the four following segments are defined in all clusters |
---|
534 | |
---|
535 | std::ostringstream smemc_conf; |
---|
536 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
537 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
538 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
539 | |
---|
540 | std::ostringstream smemc_xram; |
---|
541 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
542 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
543 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); |
---|
544 | |
---|
545 | std::ostringstream sxicu; |
---|
546 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
547 | maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, |
---|
548 | IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); |
---|
549 | |
---|
550 | std::ostringstream smdma; |
---|
551 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
552 | maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, |
---|
553 | IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); |
---|
554 | |
---|
555 | std::ostringstream sbrom; |
---|
556 | sbrom << "int_seg_brom_" << x << "_" << y; |
---|
557 | maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
558 | IntTab(cluster(x,y), INT_BROM_TGT_ID), cacheable)); |
---|
559 | |
---|
560 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
561 | |
---|
562 | if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) |
---|
563 | { |
---|
564 | std::ostringstream siobx; |
---|
565 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
566 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
567 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
568 | |
---|
569 | std::ostringstream stty; |
---|
570 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
571 | maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, |
---|
572 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
573 | |
---|
574 | std::ostringstream sfbf; |
---|
575 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
576 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
577 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
578 | |
---|
579 | std::ostringstream sbdv; |
---|
580 | sbdv << "int_seg_bdev_" << x << "_" << y; |
---|
581 | maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
582 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
583 | |
---|
584 | std::ostringstream snic; |
---|
585 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
586 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
587 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
588 | |
---|
589 | std::ostringstream sdma; |
---|
590 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
591 | maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, |
---|
592 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
593 | |
---|
594 | std::ostringstream spic; |
---|
595 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
596 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
597 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
598 | } |
---|
599 | |
---|
600 | // This define the mapping between the SRCIDs |
---|
601 | // and the port index on the local interconnect. |
---|
602 | |
---|
603 | maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), |
---|
604 | IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); |
---|
605 | |
---|
606 | maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), |
---|
607 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
608 | |
---|
609 | maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), |
---|
610 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
611 | |
---|
612 | for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) |
---|
613 | maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), |
---|
614 | IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); |
---|
615 | } |
---|
616 | } |
---|
617 | std::cout << "INT network " << maptab_int << std::endl; |
---|
618 | |
---|
619 | ///////////////////////////////////////////////////////////////////////// |
---|
620 | // RAM network mapping table |
---|
621 | // - two levels address decoding for commands |
---|
622 | // - two levels srcid decoding for responses |
---|
623 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
624 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
625 | // - 1 local target (XRAM) per cluster |
---|
626 | //////////////////////////////////////////////////////////////////////// |
---|
627 | MappingTable maptab_ram( vci_address_width, |
---|
628 | IntTab(x_width+y_width, 0), |
---|
629 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
---|
630 | 0x00FF000000); |
---|
631 | |
---|
632 | for (size_t x = 0; x < XMAX; x++) |
---|
633 | { |
---|
634 | for (size_t y = 0; y < YMAX ; y++) |
---|
635 | { |
---|
636 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
637 | << (vci_address_width-x_width-y_width); |
---|
638 | |
---|
639 | std::ostringstream sxram; |
---|
640 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
641 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
642 | SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); |
---|
643 | } |
---|
644 | } |
---|
645 | |
---|
646 | // This define the mapping between the initiators SRCID |
---|
647 | // and the port index on the RAM local interconnect. |
---|
648 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
649 | |
---|
650 | maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), |
---|
651 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
652 | |
---|
653 | maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), |
---|
654 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
655 | |
---|
656 | maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), |
---|
657 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
658 | |
---|
659 | maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), |
---|
660 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
661 | |
---|
662 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
663 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
664 | |
---|
665 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
666 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
667 | |
---|
668 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
669 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
670 | |
---|
671 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
672 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
673 | |
---|
674 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
675 | |
---|
676 | /////////////////////////////////////////////////////////////////////// |
---|
677 | // IOX network mapping table |
---|
678 | // - two levels address decoding for commands (9, 7) bits |
---|
679 | // - two levels srcid decoding for responses |
---|
680 | // - 5 initiators (IOB0, IOB1, BDEV, CDMA, IOPI) |
---|
681 | // - 9 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
682 | // |
---|
683 | // Address bit 32 is used to determine if a command must be routed to |
---|
684 | // IOB0 or IOB1. |
---|
685 | /////////////////////////////////////////////////////////////////////// |
---|
686 | MappingTable maptab_iox( |
---|
687 | vci_address_width, |
---|
688 | IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), |
---|
689 | IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), |
---|
690 | 0x00FF000000); |
---|
691 | |
---|
692 | // External peripherals segments |
---|
693 | // When there is more than one cluster, external peripherals can be accessed |
---|
694 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
695 | |
---|
696 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
697 | << (vci_address_width - x_width - y_width); |
---|
698 | |
---|
699 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, |
---|
700 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
701 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
702 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
703 | maptab_iox.add(Segment("iox_seg_bdev_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
704 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
705 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
706 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
707 | maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, |
---|
708 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
709 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
710 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
711 | |
---|
712 | if ( cluster_iob0 != cluster_iob1 ) |
---|
713 | { |
---|
714 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
715 | << (vci_address_width - x_width - y_width); |
---|
716 | |
---|
717 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, |
---|
718 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
719 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
720 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
721 | maptab_iox.add(Segment("iox_seg_bdev_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
722 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
723 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
724 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
725 | maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, |
---|
726 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
727 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
728 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
729 | } |
---|
730 | |
---|
731 | // If there is more than one cluster, external peripherals |
---|
732 | // can access RAM through two segments (IOB0 / IOB1). |
---|
733 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
734 | // and the choice depends on address bit A[32]. |
---|
735 | for (size_t x = 0; x < XMAX; x++) |
---|
736 | { |
---|
737 | for (size_t y = 0; y < YMAX ; y++) |
---|
738 | { |
---|
739 | const bool wti = true; |
---|
740 | const bool cacheable = true; |
---|
741 | |
---|
742 | const uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
743 | << (vci_address_width-x_width-y_width); |
---|
744 | |
---|
745 | const uint64_t xicu_base = SEG_XCU_BASE + offset; |
---|
746 | |
---|
747 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
748 | { |
---|
749 | std::ostringstream sxcu0; |
---|
750 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
751 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, |
---|
752 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
753 | |
---|
754 | std::ostringstream siob0; |
---|
755 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
756 | maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, |
---|
757 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
758 | } |
---|
759 | else // USE IOB1 |
---|
760 | { |
---|
761 | std::ostringstream sxcu1; |
---|
762 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
763 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, |
---|
764 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
765 | |
---|
766 | std::ostringstream siob1; |
---|
767 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
768 | maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, |
---|
769 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
770 | } |
---|
771 | } |
---|
772 | } |
---|
773 | |
---|
774 | // This define the mapping between the external initiators (SRCID) |
---|
775 | // and the port index on the IOX local interconnect. |
---|
776 | |
---|
777 | maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , |
---|
778 | IntTab( 0, IOX_CDMA_INI_ID ) ); |
---|
779 | maptab_iox.srcid_map( IntTab( 0, BDEV_LOCAL_SRCID ) , |
---|
780 | IntTab( 0, IOX_BDEV_INI_ID ) ); |
---|
781 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
782 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
783 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
784 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
785 | |
---|
786 | if ( cluster_iob0 != cluster_iob1 ) |
---|
787 | { |
---|
788 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
789 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
790 | } |
---|
791 | |
---|
792 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
793 | |
---|
794 | //////////////////// |
---|
795 | // Signals |
---|
796 | /////////////////// |
---|
797 | |
---|
798 | sc_clock signal_clk("clk"); |
---|
799 | sc_signal<bool> signal_resetn("resetn"); |
---|
800 | |
---|
801 | sc_signal<bool> signal_irq_false; |
---|
802 | sc_signal<bool> signal_irq_bdev; |
---|
803 | sc_signal<bool> signal_irq_mtty_rx; |
---|
804 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
805 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
806 | sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; |
---|
807 | |
---|
808 | // VCI signals for IOX network |
---|
809 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
810 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
811 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
812 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
813 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
814 | |
---|
815 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
816 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
817 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
818 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
819 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
820 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
821 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
822 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_ini_iopi"); |
---|
823 | |
---|
824 | // Horizontal inter-clusters INT network DSPIN |
---|
825 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
826 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); |
---|
827 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
828 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); |
---|
829 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
830 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); |
---|
831 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
832 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); |
---|
833 | |
---|
834 | // Vertical inter-clusters INT network DSPIN |
---|
835 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
836 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); |
---|
837 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
838 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); |
---|
839 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
840 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); |
---|
841 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
842 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); |
---|
843 | |
---|
844 | // Mesh boundaries INT network DSPIN |
---|
845 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
846 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); |
---|
847 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
848 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); |
---|
849 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
850 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); |
---|
851 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
852 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); |
---|
853 | |
---|
854 | |
---|
855 | // Horizontal inter-clusters RAM network DSPIN |
---|
856 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
857 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); |
---|
858 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
859 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); |
---|
860 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
861 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); |
---|
862 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
863 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); |
---|
864 | |
---|
865 | // Vertical inter-clusters RAM network DSPIN |
---|
866 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
867 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); |
---|
868 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
869 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); |
---|
870 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
871 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); |
---|
872 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
873 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); |
---|
874 | |
---|
875 | // Mesh boundaries RAM network DSPIN |
---|
876 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
877 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); |
---|
878 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
879 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); |
---|
880 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
881 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); |
---|
882 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
883 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); |
---|
884 | |
---|
885 | //////////////////////////// |
---|
886 | // Loader |
---|
887 | //////////////////////////// |
---|
888 | |
---|
889 | #if USE_ALMOS |
---|
890 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
891 | almos_archinfo_pathname, |
---|
892 | almos_kernel_pathname); |
---|
893 | #else |
---|
894 | soclib::common::Loader loader(soft_name); |
---|
895 | #endif |
---|
896 | |
---|
897 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
898 | proc_iss::set_loader(loader); |
---|
899 | |
---|
900 | //////////////////////////////////////// |
---|
901 | // Instanciated Hardware Components |
---|
902 | //////////////////////////////////////// |
---|
903 | |
---|
904 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
905 | |
---|
906 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
907 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 8 : 7; |
---|
908 | |
---|
909 | // IOX network |
---|
910 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
911 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
912 | maptab_iox, |
---|
913 | nb_iox_targets, |
---|
914 | nb_iox_initiators ); |
---|
915 | |
---|
916 | // Network Controller |
---|
917 | VciMultiNic<vci_param_ext>* mnic; |
---|
918 | mnic = new VciMultiNic<vci_param_ext>( "mnic", |
---|
919 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
920 | maptab_iox, |
---|
921 | NB_NIC_CHANNELS, |
---|
922 | 0, // mac_4 address |
---|
923 | 0, // mac_2 address |
---|
924 | nic_rx_name, |
---|
925 | nic_tx_name); |
---|
926 | |
---|
927 | // Frame Buffer |
---|
928 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
929 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
930 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
931 | maptab_iox, |
---|
932 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
933 | |
---|
934 | // Block Device |
---|
935 | // for AHCI |
---|
936 | // std::vector<std::string> filenames; |
---|
937 | // filenames.push_back(disk_name); // one single disk |
---|
938 | VciBlockDeviceTsar<vci_param_ext>* bdev; |
---|
939 | bdev = new VciBlockDeviceTsar<vci_param_ext>( "bdev", |
---|
940 | maptab_iox, |
---|
941 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
942 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
943 | disk_name, |
---|
944 | 512, // block size |
---|
945 | 64, // burst size (bytes) |
---|
946 | 0 ); // disk latency |
---|
947 | |
---|
948 | // Chained Buffer DMA controller |
---|
949 | VciChbufDma<vci_param_ext>* cdma; |
---|
950 | cdma = new VciChbufDma<vci_param_ext>( "cdma", |
---|
951 | maptab_iox, |
---|
952 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
953 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
954 | 64, // burst size (bytes) |
---|
955 | 2*NB_NIC_CHANNELS ); |
---|
956 | // Multi-TTY controller |
---|
957 | std::vector<std::string> vect_names; |
---|
958 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
959 | { |
---|
960 | std::ostringstream term_name; |
---|
961 | term_name << "term" << tid; |
---|
962 | vect_names.push_back(term_name.str().c_str()); |
---|
963 | } |
---|
964 | VciMultiTty<vci_param_ext>* mtty; |
---|
965 | mtty = new VciMultiTty<vci_param_ext>( "mtty", |
---|
966 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
967 | maptab_iox, |
---|
968 | vect_names); |
---|
969 | |
---|
970 | // IOPIC |
---|
971 | VciIopic<vci_param_ext>* iopi; |
---|
972 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
973 | maptab_iox, |
---|
974 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
975 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
976 | 32 ); // number of input HWI |
---|
977 | |
---|
978 | // Clusters |
---|
979 | TsarIobCluster<vci_param_int, |
---|
980 | vci_param_ext, |
---|
981 | dspin_int_cmd_width, |
---|
982 | dspin_int_rsp_width, |
---|
983 | dspin_ram_cmd_width, |
---|
984 | dspin_ram_rsp_width>* clusters[XMAX][YMAX]; |
---|
985 | |
---|
986 | #if USE_OPENMP |
---|
987 | #pragma omp parallel |
---|
988 | { |
---|
989 | #pragma omp for |
---|
990 | #endif |
---|
991 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
---|
992 | { |
---|
993 | size_t x = i / YMAX; |
---|
994 | size_t y = i % YMAX; |
---|
995 | |
---|
996 | #if USE_OPENMP |
---|
997 | #pragma omp critical |
---|
998 | { |
---|
999 | #endif |
---|
1000 | std::cout << std::endl; |
---|
1001 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
1002 | std::cout << std::endl; |
---|
1003 | |
---|
1004 | const bool is_iob0 = (cluster(x,y) == cluster_iob0); |
---|
1005 | const bool is_iob1 = (cluster(x,y) == cluster_iob1); |
---|
1006 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
1007 | |
---|
1008 | const int iox_iob_ini_id = is_iob0 ? |
---|
1009 | IOX_IOB0_INI_ID : |
---|
1010 | IOX_IOB1_INI_ID ; |
---|
1011 | const int iox_iob_tgt_id = is_iob0 ? |
---|
1012 | IOX_IOB0_TGT_ID : |
---|
1013 | IOX_IOB1_TGT_ID ; |
---|
1014 | |
---|
1015 | std::ostringstream sc; |
---|
1016 | sc << "cluster_" << x << "_" << y; |
---|
1017 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
1018 | vci_param_ext, |
---|
1019 | dspin_int_cmd_width, |
---|
1020 | dspin_int_rsp_width, |
---|
1021 | dspin_ram_cmd_width, |
---|
1022 | dspin_ram_rsp_width> |
---|
1023 | ( |
---|
1024 | sc.str().c_str(), |
---|
1025 | NB_PROCS_MAX, |
---|
1026 | NB_DMA_CHANNELS, |
---|
1027 | x, |
---|
1028 | y, |
---|
1029 | XMAX, |
---|
1030 | YMAX, |
---|
1031 | |
---|
1032 | maptab_int, |
---|
1033 | maptab_ram, |
---|
1034 | maptab_iox, |
---|
1035 | |
---|
1036 | x_width, |
---|
1037 | y_width, |
---|
1038 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
1039 | |
---|
1040 | INT_MEMC_TGT_ID, |
---|
1041 | INT_XICU_TGT_ID, |
---|
1042 | INT_MDMA_TGT_ID, |
---|
1043 | INT_BROM_TGT_ID, |
---|
1044 | INT_IOBX_TGT_ID, |
---|
1045 | |
---|
1046 | INT_PROC_INI_ID, |
---|
1047 | INT_MDMA_INI_ID, |
---|
1048 | INT_IOBX_INI_ID, |
---|
1049 | |
---|
1050 | RAM_XRAM_TGT_ID, |
---|
1051 | |
---|
1052 | RAM_MEMC_INI_ID, |
---|
1053 | RAM_IOBX_INI_ID, |
---|
1054 | |
---|
1055 | is_io_cluster, |
---|
1056 | iox_iob_tgt_id, |
---|
1057 | iox_iob_ini_id, |
---|
1058 | |
---|
1059 | MEMC_WAYS, |
---|
1060 | MEMC_SETS, |
---|
1061 | L1_IWAYS, |
---|
1062 | L1_ISETS, |
---|
1063 | L1_DWAYS, |
---|
1064 | L1_DSETS, |
---|
1065 | XRAM_LATENCY, |
---|
1066 | XCU_NB_INPUTS, |
---|
1067 | |
---|
1068 | distributed_boot, |
---|
1069 | |
---|
1070 | loader, |
---|
1071 | |
---|
1072 | frozen_cycles, |
---|
1073 | debug_from, |
---|
1074 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
1075 | debug_ok and (cluster(x,y) == debug_proc_id), |
---|
1076 | debug_ok and debug_iob |
---|
1077 | ); |
---|
1078 | |
---|
1079 | #if USE_OPENMP |
---|
1080 | } // end critical |
---|
1081 | #endif |
---|
1082 | } // end for |
---|
1083 | #if USE_OPENMP |
---|
1084 | } |
---|
1085 | #endif |
---|
1086 | |
---|
1087 | std::cout << std::endl; |
---|
1088 | |
---|
1089 | /////////////////////////////////////////////////////////////////////////////// |
---|
1090 | // Net-list |
---|
1091 | /////////////////////////////////////////////////////////////////////////////// |
---|
1092 | |
---|
1093 | // IOX network connexion |
---|
1094 | iox_network->p_clk (signal_clk); |
---|
1095 | iox_network->p_resetn (signal_resetn); |
---|
1096 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
1097 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
1098 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
1099 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
1100 | |
---|
1101 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
1102 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
1103 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
1104 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
1105 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
1106 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
1107 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
1108 | |
---|
1109 | if (cluster_iob0 != cluster_iob1) |
---|
1110 | { |
---|
1111 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
1112 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
1113 | } |
---|
1114 | |
---|
1115 | // BDEV connexion |
---|
1116 | bdev->p_clk (signal_clk); |
---|
1117 | bdev->p_resetn (signal_resetn); |
---|
1118 | bdev->p_irq (signal_irq_bdev); |
---|
1119 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
1120 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
1121 | |
---|
1122 | std::cout << " - BDEV connected" << std::endl; |
---|
1123 | |
---|
1124 | // FBUF connexion |
---|
1125 | fbuf->p_clk (signal_clk); |
---|
1126 | fbuf->p_resetn (signal_resetn); |
---|
1127 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
1128 | |
---|
1129 | std::cout << " - FBUF connected" << std::endl; |
---|
1130 | |
---|
1131 | // MNIC connexion |
---|
1132 | mnic->p_clk (signal_clk); |
---|
1133 | mnic->p_resetn (signal_resetn); |
---|
1134 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
1135 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
1136 | { |
---|
1137 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
1138 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
1139 | } |
---|
1140 | |
---|
1141 | std::cout << " - MNIC connected" << std::endl; |
---|
1142 | |
---|
1143 | // MTTY connexion |
---|
1144 | mtty->p_clk (signal_clk); |
---|
1145 | mtty->p_resetn (signal_resetn); |
---|
1146 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
1147 | mtty->p_irq[0] (signal_irq_mtty_rx); |
---|
1148 | |
---|
1149 | std::cout << " - MTTY connected" << std::endl; |
---|
1150 | |
---|
1151 | // CDMA connexion |
---|
1152 | cdma->p_clk (signal_clk); |
---|
1153 | cdma->p_resetn (signal_resetn); |
---|
1154 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
1155 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
1156 | for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) |
---|
1157 | { |
---|
1158 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
1159 | } |
---|
1160 | |
---|
1161 | std::cout << " - CDMA connected" << std::endl; |
---|
1162 | |
---|
1163 | // IOPI connexion |
---|
1164 | iopi->p_clk (signal_clk); |
---|
1165 | iopi->p_resetn (signal_resetn); |
---|
1166 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
1167 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
1168 | for ( size_t i=0 ; i<32 ; i++) |
---|
1169 | { |
---|
1170 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
1171 | else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); |
---|
1172 | else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
1173 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
1174 | else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
1175 | else if(i < 8) iopi->p_hwi[i] (signal_irq_false); |
---|
1176 | else if(i == 8) iopi->p_hwi[i] (signal_irq_bdev); |
---|
1177 | else if(i == 9) iopi->p_hwi[i] (signal_irq_mtty_rx); |
---|
1178 | else iopi->p_hwi[i] (signal_irq_false); |
---|
1179 | } |
---|
1180 | |
---|
1181 | std::cout << " - IOPIC connected" << std::endl; |
---|
1182 | |
---|
1183 | |
---|
1184 | // IOB0 cluster connexion to IOX network |
---|
1185 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
1186 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
1187 | |
---|
1188 | // IOB1 cluster connexion to IOX network |
---|
1189 | // (only when there is more than 1 cluster) |
---|
1190 | if ( cluster_iob0 != cluster_iob1 ) |
---|
1191 | { |
---|
1192 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
1193 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
1194 | } |
---|
1195 | |
---|
1196 | // All clusters Clock & RESET connexions |
---|
1197 | for ( size_t x = 0; x < (XMAX); x++ ) |
---|
1198 | { |
---|
1199 | for (size_t y = 0; y < YMAX; y++) |
---|
1200 | { |
---|
1201 | clusters[x][y]->p_clk (signal_clk); |
---|
1202 | clusters[x][y]->p_resetn (signal_resetn); |
---|
1203 | } |
---|
1204 | } |
---|
1205 | |
---|
1206 | // Inter Clusters horizontal connections |
---|
1207 | if (XMAX > 1) |
---|
1208 | { |
---|
1209 | for (size_t x = 0; x < (XMAX-1); x++) |
---|
1210 | { |
---|
1211 | for (size_t y = 0; y < YMAX; y++) |
---|
1212 | { |
---|
1213 | for (size_t k = 0; k < 3; k++) |
---|
1214 | { |
---|
1215 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
1216 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
1217 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
1218 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
1219 | } |
---|
1220 | |
---|
1221 | for (size_t k = 0; k < 2; k++) |
---|
1222 | { |
---|
1223 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
1224 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
1225 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
1226 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
1227 | } |
---|
1228 | |
---|
1229 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
1230 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
1231 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
1232 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
1233 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
1234 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
1235 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
1236 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
1237 | } |
---|
1238 | } |
---|
1239 | } |
---|
1240 | |
---|
1241 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
1242 | |
---|
1243 | // Inter Clusters vertical connections |
---|
1244 | if (YMAX > 1) |
---|
1245 | { |
---|
1246 | for (size_t y = 0; y < (YMAX-1); y++) |
---|
1247 | { |
---|
1248 | for (size_t x = 0; x < XMAX; x++) |
---|
1249 | { |
---|
1250 | for (size_t k = 0; k < 3; k++) |
---|
1251 | { |
---|
1252 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
1253 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
1254 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
1255 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
1256 | } |
---|
1257 | |
---|
1258 | for (size_t k = 0; k < 2; k++) |
---|
1259 | { |
---|
1260 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
1261 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
1262 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
1263 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
1264 | } |
---|
1265 | |
---|
1266 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
1267 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
1268 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
1269 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
1270 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
1271 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
1272 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
1273 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
1274 | } |
---|
1275 | } |
---|
1276 | } |
---|
1277 | |
---|
1278 | std::cout << "Vertical connections established" << std::endl; |
---|
1279 | |
---|
1280 | // East & West boundary cluster connections |
---|
1281 | for (size_t y = 0; y < YMAX; y++) |
---|
1282 | { |
---|
1283 | for (size_t k = 0; k < 3; k++) |
---|
1284 | { |
---|
1285 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
1286 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
1287 | clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); |
---|
1288 | clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); |
---|
1289 | } |
---|
1290 | |
---|
1291 | for (size_t k = 0; k < 2; k++) |
---|
1292 | { |
---|
1293 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
1294 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
1295 | clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); |
---|
1296 | clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); |
---|
1297 | } |
---|
1298 | |
---|
1299 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
1300 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
1301 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
1302 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
1303 | |
---|
1304 | clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); |
---|
1305 | clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); |
---|
1306 | clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); |
---|
1307 | clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); |
---|
1308 | } |
---|
1309 | |
---|
1310 | std::cout << "East & West boundaries established" << std::endl; |
---|
1311 | |
---|
1312 | // North & South boundary clusters connections |
---|
1313 | for (size_t x = 0; x < XMAX; x++) |
---|
1314 | { |
---|
1315 | for (size_t k = 0; k < 3; k++) |
---|
1316 | { |
---|
1317 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
1318 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
1319 | clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); |
---|
1320 | clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); |
---|
1321 | } |
---|
1322 | |
---|
1323 | for (size_t k = 0; k < 2; k++) |
---|
1324 | { |
---|
1325 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
1326 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
1327 | clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); |
---|
1328 | clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); |
---|
1329 | } |
---|
1330 | |
---|
1331 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
1332 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
1333 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
1334 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
1335 | |
---|
1336 | clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); |
---|
1337 | clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); |
---|
1338 | clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); |
---|
1339 | clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); |
---|
1340 | } |
---|
1341 | |
---|
1342 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
1343 | |
---|
1344 | //////////////////////////////////////////////////////// |
---|
1345 | // Simulation |
---|
1346 | /////////////////////////////////////////////////////// |
---|
1347 | |
---|
1348 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
1349 | |
---|
1350 | signal_resetn = false; |
---|
1351 | signal_irq_false = false; |
---|
1352 | |
---|
1353 | // network boundaries signals |
---|
1354 | for (size_t x = 0; x < XMAX ; x++) |
---|
1355 | { |
---|
1356 | for (size_t y = 0; y < YMAX ; y++) |
---|
1357 | { |
---|
1358 | for (size_t a = 0; a < 4; a++) |
---|
1359 | { |
---|
1360 | for (size_t k = 0; k < 3; k++) |
---|
1361 | { |
---|
1362 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
1363 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
1364 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
1365 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
1366 | } |
---|
1367 | |
---|
1368 | for (size_t k = 0; k < 2; k++) |
---|
1369 | { |
---|
1370 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
1371 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
1372 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
1373 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
1374 | } |
---|
1375 | |
---|
1376 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
1377 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
1378 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
1379 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
1380 | |
---|
1381 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
1382 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
1383 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
1384 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
1385 | } |
---|
1386 | } |
---|
1387 | } |
---|
1388 | |
---|
1389 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
1390 | signal_resetn = true; |
---|
1391 | |
---|
1392 | |
---|
1393 | // simulation loop |
---|
1394 | struct timeval t1,t2; |
---|
1395 | gettimeofday(&t1, NULL); |
---|
1396 | |
---|
1397 | for (size_t n = 1; n < ncycles; n++) |
---|
1398 | { |
---|
1399 | // stats display |
---|
1400 | if( (n % 1000000) == 0) |
---|
1401 | { |
---|
1402 | gettimeofday(&t2, NULL); |
---|
1403 | |
---|
1404 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
---|
1405 | (uint64_t) t1.tv_usec / 1000; |
---|
1406 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
---|
1407 | (uint64_t) t2.tv_usec / 1000; |
---|
1408 | std::cerr << "### cycle = " << n |
---|
1409 | << " / frequency = " |
---|
1410 | << (double) 1000000 / (double) (ms2 - ms1) << "Khz" |
---|
1411 | << std::endl; |
---|
1412 | |
---|
1413 | gettimeofday(&t1, NULL); |
---|
1414 | } |
---|
1415 | |
---|
1416 | // Monitor a specific address for one L1 cache |
---|
1417 | // clusters[1][1]->proc[0]->cache_monitor(0x50090ULL); |
---|
1418 | |
---|
1419 | // Monitor a specific address for one L2 cache |
---|
1420 | // clusters[0][0]->memc->cache_monitor( 0x170000ULL); |
---|
1421 | |
---|
1422 | // Monitor a specific address for one XRAM |
---|
1423 | // if (n == 3000000) clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); |
---|
1424 | |
---|
1425 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
1426 | { |
---|
1427 | std::cout << "****************** cycle " << std::dec << n ; |
---|
1428 | std::cout << " ************************************************" << std::endl; |
---|
1429 | |
---|
1430 | // trace proc[debug_proc_id] |
---|
1431 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
1432 | { |
---|
1433 | size_t l = debug_proc_id % NB_PROCS_MAX ; |
---|
1434 | size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; |
---|
1435 | size_t x = cluster_xy >> 4; |
---|
1436 | size_t y = cluster_xy & 0xF; |
---|
1437 | |
---|
1438 | clusters[x][y]->proc[l]->print_trace(1); |
---|
1439 | std::ostringstream proc_signame; |
---|
1440 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
1441 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
1442 | |
---|
1443 | clusters[x][y]->xicu->print_trace(l); |
---|
1444 | std::ostringstream xicu_signame; |
---|
1445 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
1446 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
1447 | |
---|
1448 | // clusters[x][y]->mdma->print_trace(); |
---|
1449 | // std::ostringstream mdma_signame; |
---|
1450 | // mdma_signame << "[SIG]MDMA_" << x << "_" << y; |
---|
1451 | // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); |
---|
1452 | |
---|
1453 | if( clusters[x][y]->signal_proc_it[l].read() ) |
---|
1454 | std::cout << "### IRQ_PROC_" << std::dec |
---|
1455 | << x << "_" << y << "_" << l << " ACTIVE" << std::endl; |
---|
1456 | } |
---|
1457 | |
---|
1458 | // trace memc[debug_memc_id] |
---|
1459 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
1460 | { |
---|
1461 | size_t x = debug_memc_id >> 4; |
---|
1462 | size_t y = debug_memc_id & 0xF; |
---|
1463 | |
---|
1464 | clusters[x][y]->memc->print_trace(0); |
---|
1465 | std::ostringstream smemc_tgt; |
---|
1466 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
1467 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
1468 | std::ostringstream smemc_ini; |
---|
1469 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
1470 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
1471 | |
---|
1472 | clusters[x][y]->xram->print_trace(); |
---|
1473 | std::ostringstream sxram_tgt; |
---|
1474 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
1475 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
1476 | } |
---|
1477 | |
---|
1478 | |
---|
1479 | // trace XRAM and XRAM network routers in cluster[debug_xram_id] |
---|
1480 | if ( debug_xram_id != 0xFFFFFFFF ) |
---|
1481 | { |
---|
1482 | size_t x = debug_xram_id >> 4; |
---|
1483 | size_t y = debug_xram_id & 0xF; |
---|
1484 | |
---|
1485 | clusters[x][y]->xram->print_trace(); |
---|
1486 | std::ostringstream sxram_tgt; |
---|
1487 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
1488 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
1489 | |
---|
1490 | clusters[x][y]->ram_router_cmd->print_trace(); |
---|
1491 | clusters[x][y]->ram_router_rsp->print_trace(); |
---|
1492 | } |
---|
1493 | |
---|
1494 | // trace iob, iox and external peripherals |
---|
1495 | if ( debug_iob ) |
---|
1496 | { |
---|
1497 | clusters[0][0]->iob->print_trace(); |
---|
1498 | clusters[XMAX-1][YMAX-1]->iob->print_trace(); |
---|
1499 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
---|
1500 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
---|
1501 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
---|
1502 | |
---|
1503 | signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
1504 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
1505 | |
---|
1506 | // cdma->print_trace(); |
---|
1507 | // signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); |
---|
1508 | // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); |
---|
1509 | |
---|
1510 | // mtty->print_trace(); |
---|
1511 | // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); |
---|
1512 | |
---|
1513 | bdev->print_trace(); |
---|
1514 | signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
1515 | signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
1516 | |
---|
1517 | mnic->print_trace(); |
---|
1518 | signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
---|
1519 | |
---|
1520 | // fbuf->print_trace(); |
---|
1521 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); |
---|
1522 | |
---|
1523 | iopi->print_trace(); |
---|
1524 | signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
1525 | signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
1526 | iox_network->print_trace(); |
---|
1527 | |
---|
1528 | // interrupts |
---|
1529 | if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; |
---|
1530 | if (signal_irq_mtty_rx) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; |
---|
1531 | if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; |
---|
1532 | if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; |
---|
1533 | if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; |
---|
1534 | if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; |
---|
1535 | } |
---|
1536 | } |
---|
1537 | |
---|
1538 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
1539 | } |
---|
1540 | return EXIT_SUCCESS; |
---|
1541 | } |
---|
1542 | |
---|
1543 | int sc_main (int argc, char *argv[]) |
---|
1544 | { |
---|
1545 | try { |
---|
1546 | return _main(argc, argv); |
---|
1547 | } catch (std::exception &e) { |
---|
1548 | std::cout << e.what() << std::endl; |
---|
1549 | } catch (...) { |
---|
1550 | std::cout << "Unknown exception occured" << std::endl; |
---|
1551 | throw; |
---|
1552 | } |
---|
1553 | return 1; |
---|
1554 | } |
---|
1555 | |
---|
1556 | |
---|
1557 | // Local Variables: |
---|
1558 | // tab-width: 3 |
---|
1559 | // c-basic-offset: 3 |
---|
1560 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
1561 | // indent-tabs-mode: nil |
---|
1562 | // End: |
---|
1563 | |
---|
1564 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
1565 | |
---|
1566 | |
---|
1567 | |
---|