[747] | 1 | |
---|
| 2 | # -*- python -*- |
---|
| 3 | |
---|
[748] | 4 | Module('caba:reconfiguration:tsar_iob_cluster', |
---|
[747] | 5 | classname = 'soclib::caba::TsarIobCluster', |
---|
| 6 | |
---|
| 7 | tmpl_parameters = [ |
---|
| 8 | parameter.Module('vci_param_int', default = 'caba:vci_param', |
---|
| 9 | cell_size = parameter.Reference('vci_data_width_int')), |
---|
| 10 | parameter.Module('vci_param_ext', default = 'caba:vci_param', |
---|
| 11 | cell_size = parameter.Reference('vci_data_width_ext')), |
---|
| 12 | parameter.Int('dspin_int_cmd_width'), |
---|
| 13 | parameter.Int('dspin_int_rsp_width'), |
---|
| 14 | parameter.Int('dspin_ram_cmd_width'), |
---|
| 15 | parameter.Int('dspin_ram_rsp_width'), |
---|
| 16 | ], |
---|
| 17 | |
---|
| 18 | header_files = [ |
---|
| 19 | '../source/include/tsar_iob_cluster.h', |
---|
| 20 | ], |
---|
| 21 | |
---|
| 22 | implementation_files = [ |
---|
| 23 | '../source/src/tsar_iob_cluster.cpp', |
---|
| 24 | ], |
---|
| 25 | |
---|
| 26 | uses = [ |
---|
| 27 | Uses('caba:base_module'), |
---|
| 28 | Uses('common:mapping_table'), |
---|
| 29 | Uses('common:iss2'), |
---|
| 30 | Uses('common:elf_file_loader'), |
---|
| 31 | |
---|
| 32 | # internal network components |
---|
| 33 | Uses('caba:vci_cc_vcache_wrapper', |
---|
| 34 | cell_size = parameter.Reference('vci_data_width_int'), |
---|
| 35 | dspin_in_width = parameter.Reference('dspin_int_cmd_width'), |
---|
| 36 | dspin_out_width = parameter.Reference('dspin_int_rsp_width'), |
---|
| 37 | iss_t = 'common:gdb_iss', |
---|
| 38 | gdb_iss_t = 'common:mips32el'), |
---|
| 39 | |
---|
| 40 | Uses('caba:vci_mem_cache', |
---|
| 41 | memc_cell_size_int = parameter.Reference('vci_data_width_int'), |
---|
| 42 | memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), |
---|
| 43 | dspin_in_width = parameter.Reference('dspin_int_rsp_width'), |
---|
| 44 | dspin_out_width = parameter.Reference('dspin_int_cmd_width')), |
---|
| 45 | |
---|
| 46 | Uses('caba:vci_xicu', |
---|
| 47 | cell_size = parameter.Reference('vci_data_width_int')), |
---|
| 48 | |
---|
| 49 | Uses('caba:vci_multi_dma', |
---|
| 50 | cell_size = parameter.Reference('vci_data_width_int')), |
---|
| 51 | |
---|
[748] | 52 | Uses('caba:vci_simple_rom', |
---|
| 53 | cell_size = parameter.Reference('vci_data_width_int')), |
---|
| 54 | |
---|
[747] | 55 | Uses('caba:vci_local_crossbar', |
---|
| 56 | cell_size = parameter.Reference('vci_data_width_int')), |
---|
| 57 | |
---|
| 58 | Uses('caba:dspin_local_crossbar', |
---|
| 59 | flit_width = parameter.Reference('dspin_int_cmd_width')), |
---|
| 60 | |
---|
| 61 | Uses('caba:dspin_local_crossbar', |
---|
| 62 | flit_width = parameter.Reference('dspin_int_rsp_width')), |
---|
| 63 | |
---|
| 64 | Uses('caba:dspin_local_crossbar', |
---|
| 65 | flit_width = parameter.Reference('dspin_ram_cmd_width')), |
---|
| 66 | |
---|
| 67 | Uses('caba:dspin_local_crossbar', |
---|
| 68 | flit_width = parameter.Reference('dspin_ram_rsp_width')), |
---|
| 69 | |
---|
| 70 | Uses('caba:vci_dspin_initiator_wrapper', |
---|
| 71 | cell_size = parameter.Reference('vci_data_width_int'), |
---|
| 72 | dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), |
---|
| 73 | dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), |
---|
| 74 | |
---|
| 75 | Uses('caba:vci_dspin_target_wrapper', |
---|
| 76 | cell_size = parameter.Reference('vci_data_width_int'), |
---|
| 77 | dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), |
---|
| 78 | dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), |
---|
| 79 | |
---|
| 80 | Uses('caba:virtual_dspin_router', |
---|
| 81 | flit_width = parameter.Reference('dspin_int_cmd_width')), |
---|
| 82 | |
---|
| 83 | Uses('caba:virtual_dspin_router', |
---|
| 84 | flit_width = parameter.Reference('dspin_int_rsp_width')), |
---|
| 85 | |
---|
| 86 | # RAM network components |
---|
| 87 | Uses('caba:vci_dspin_initiator_wrapper', |
---|
| 88 | cell_size = parameter.Reference('vci_data_width_ext'), |
---|
| 89 | dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), |
---|
| 90 | dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), |
---|
| 91 | |
---|
| 92 | Uses('caba:vci_dspin_target_wrapper', |
---|
| 93 | cell_size = parameter.Reference('vci_data_width_ext'), |
---|
| 94 | dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), |
---|
| 95 | dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), |
---|
| 96 | |
---|
| 97 | Uses('caba:dspin_router', |
---|
| 98 | flit_width = parameter.Reference('dspin_ram_cmd_width')), |
---|
| 99 | |
---|
| 100 | Uses('caba:dspin_router', |
---|
| 101 | flit_width = parameter.Reference('dspin_ram_rsp_width')), |
---|
| 102 | |
---|
| 103 | Uses('caba:vci_simple_ram', |
---|
| 104 | cell_size = parameter.Reference('vci_data_width_ext')), |
---|
| 105 | |
---|
| 106 | # IOX network components |
---|
| 107 | Uses('caba:vci_io_bridge', |
---|
| 108 | iob_cell_size_int = parameter.Reference('vci_data_width_int'), |
---|
| 109 | iob_cell_size_ext = parameter.Reference('vci_data_width_ext')), |
---|
| 110 | ], |
---|
| 111 | |
---|
| 112 | ports = [ |
---|
| 113 | Port('caba:bit_in', 'p_resetn', auto = 'resetn'), |
---|
| 114 | Port('caba:clock_in', 'p_clk', auto = 'clock'), |
---|
| 115 | |
---|
| 116 | Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], |
---|
| 117 | dspin_data_size = parameter.Reference('dspin_int_cmd_width')), |
---|
| 118 | Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], |
---|
| 119 | dspin_data_size = parameter.Reference('dspin_int_cmd_width')), |
---|
| 120 | Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], |
---|
| 121 | dspin_data_size = parameter.Reference('dspin_int_rsp_width')), |
---|
| 122 | Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], |
---|
| 123 | dspin_data_size = parameter.Reference('dspin_int_rsp_width')), |
---|
| 124 | |
---|
| 125 | Port('caba:dspin_output', 'p_ram_cmd_out', [4], |
---|
| 126 | dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), |
---|
| 127 | Port('caba:dspin_input', 'p_ram_cmd_in', [4], |
---|
| 128 | dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), |
---|
| 129 | Port('caba:dspin_output', 'p_ram_rsp_out', [4], |
---|
| 130 | dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), |
---|
| 131 | Port('caba:dspin_input', 'p_ram_rsp_in', [4], |
---|
| 132 | dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), |
---|
| 133 | ], |
---|
| 134 | ) |
---|
| 135 | |
---|
| 136 | |
---|